JPH0620248B2 - Vertical sync signal presence detection circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical sync signal presence / absence detection circuit, and more particularly to a composite video signal (or a luminance signal in which a chroma signal is separated; In this specification, a horizontal sync signal or a vertical sync signal is extracted from a composite signal), the presence or absence of a vertical sync signal is checked, and a vertical sync signal is internally generated when there is no vertical sync signal. In video equipment such as
The present invention relates to a vertical sync signal presence / absence detection circuit capable of easily detecting the presence / absence of a vertical sync signal even when a television signal (hereinafter, TV signal) is received in a weak electric field.

[Prior Art] In a television receiver, a video device, etc., a horizontal synchronizing signal or a vertical synchronizing signal is extracted from a composite signal, and horizontal and vertical deflection currents are generated in synchronization with these synchronizing signals. Also, in processing such as superimposing of characters,
In order to synchronize the video signal with the character generator, the synchronization signal is extracted from the composite signal and this synchronization signal is added to the character generator to generate a character signal synchronized with the video signal to generate characters and A composite image or the like is displayed.

[Problems to be solved] In operations such as superimpose, the presence or absence of a vertical sync signal is detected, and when the vertical sync signal cannot be detected, an internal image is displayed in synchronization with the internally generated horizontal and vertical sync signals. However, in a video device such as a television receiver, when a TV signal is received in a weak electric field, even if the composite signal is obtained by demodulating the TV signal, the horizontal and vertical sync signals are close to the noise level. Therefore, the noise and the sync signal cannot be distinguished.

Therefore, in a video device having a function of internally generating a video such as a superimpose or the like, it becomes difficult to detect the vertical synchronization signal in the state of receiving the TV signal of the weak electric field, and it is detected or not detected. Therefore, in a device that detects the vertical synchronization signal and takes internal synchronization when there is no vertical synchronization signal, either the internal synchronization signal is generated and the image is displayed, or the external synchronization (synchronization with the synchronization signal of the received composite signal is performed. It is difficult to determine whether to display an image in a state where the image is displayed), and the switching may or may not be performed according to the variation of the electric field in the weak electric field (in other words, the presence or absence of the vertical synchronization signal detection).

Therefore, a synchronization error occurs between the internally generated video and the received video signal, or switching between the internal video and the received video does not work properly, and a clear video cannot be displayed.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems of the prior art, and an object thereof is to provide a vertical sync signal presence / absence detection circuit capable of detecting the presence / absence of a vertical sync signal even in a weak electric field state.

[Means for Solving the Problems] In the structure of the vertical sync signal presence / absence detection circuit of the present invention for achieving such an object, is the horizontal sync signal extracted from the composite signal within a predetermined pulse width range? Horizontal sync signal presence / absence determination circuit for determining the presence / absence of a horizontal sync signal depending on whether or not, and a pseudo horizontal sync signal generation for generating a pulse signal having the same frequency or a corresponding frequency in synchronization with the horizontal sync signal The circuit and the vertical sync signal extracted from the composite signal are received, the pulse signal is counted when the horizontal sync signal determination circuit determines that the horizontal sync signal is present, and the vertical sync signal has a predetermined pulse width range. And a vertical synchronization signal presence / absence determining circuit for determining the presence / absence of a vertical synchronization signal depending on whether or not

[Operation] As described above, the horizontal sync signal presence / absence determining circuit for determining the presence / absence of the horizontal sync signal depending on whether the horizontal sync signal is within the predetermined pulse width range and the vertical sync signal are within the predetermined pulse width range. A vertical sync signal presence / absence determination circuit for determining the presence / absence of a vertical sync signal depending on whether or not a two-stage determination is performed,
Moreover, since the vertical synchronization signal presence / absence determination circuit determines the pulse width of the vertical synchronization signal with reference to the pulse from the pseudo horizontal synchronization signal generation circuit, even if the electric field is weak, It is possible to make a judgment that is not easily affected by noise, and for the vertical sync signal, the existence of the vertical sync signal can be judged more accurately based on the pseudo horizontal sync signal that is generated at an accurate timing that is not affected by the electric field according to the judgment result of the horizontal sync signal. Can be accurate.

As a result, it is possible to detect the presence or absence of the vertical synchronization signal with high accuracy even in a weak electric field without affecting noise.

If a register is provided in each of the vertical sync signal presence / absence decision circuit and the horizontal sync signal presence / absence decision circuit so that the decision timing can be set later, further appropriate decision conditions can be set according to the reception state. It is possible to detect the presence / absence of a vertical synchronization signal with high accuracy in response to the reception state.

[Embodiment] An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of a vertical sync signal presence / absence detection circuit to which the present invention is applied.

In FIG. 1, reference numeral 1 denotes a vertical sync signal presence / absence detection circuit, a horizontal sync signal presence / absence determination circuit 2, a clock generation circuit 3 for supplying a clock to this circuit, and a pseudo horizontal circuit having a PLL circuit synchronized with the horizontal sync signal. Sync signal generation circuit 4,
It is composed of a switch circuit 5 composed of analog switches and the like, and a vertical sync signal presence / absence judgment circuit 6, and its input terminal 7 receives a horizontal sync signal from a horizontal sync separation circuit, and its input terminal 8 receives a vertical sync signal. The vertical synchronizing signal is received from the separating circuit, and the vertical synchronizing signal detection output is generated at the output terminal 9.

The horizontal sync signal presence / absence determination circuit 2 receives the horizontal sync signal from the horizontal sync separation circuit via the input terminal 7, counts the clock from the clock generation circuit 3, and counts the pulse interval of the horizontal sync signal with this clock as a reference. By measuring, it is determined whether or not the horizontal synchronizing signal is within a predetermined pulse width range. As a result of this determination, when the received horizontal synchronizing signal is within the range of the predetermined pulse width, the switch circuit 5 is driven to turn it on.

The pseudo horizontal sync signal generation circuit 4 has a PLL circuit including an AFC (automatic frequency control circuit) and a VCO (voltage controlled oscillator circuit), and outputs the horizontal sync signal from the horizontal sync separation circuit to the AFC via the input terminal 7. In response to this, a pulse having a horizontal frequency of 15.75 kHz which is synchronized with the horizontal synchronizing signal is generated, and this pulse is sent to the vertical synchronizing signal presence / absence determining circuit 6 via the switch circuit 5.

The vertical sync signal presence / absence determination circuit 6 receives the vertical sync signal input through the input terminal 8 from the vertical sync separation circuit, counts the pulses (pseudo horizontal sync signal) from the pseudo horizontal sync signal generation circuit 4, and The pseudo horizontal sync signal is timed with reference to the sync signal to determine whether the vertical sync signal is within a predetermined pulse width range.
As a result of this judgment, when the received vertical synchronizing signal is within the range of the predetermined pulse width, the detection signal with the vertical synchronizing signal is sent to the output terminal 9 in synchronization with the timing of the vertical synchronizing signal.

Here, the horizontal sync signal presence / absence determination circuit 3 includes a counter 31
And a lower limit value setting register 32, a lower limit value detection circuit 33, an upper limit value setting register 34, an upper limit value detection circuit 35, a flip-flop (F / F) 36, a data latch circuit 37, an inverter 38, and a delay circuit 39. It is configured.

The counter 31 is a counter that receives a clock sent from the clock generation circuit 3 at its clock terminal (CK) and counts it, and the lower limit value detection circuit 33 is an AN.
It is composed of a D gate circuit, and when the value at each digit position of the counter 31 is received and coincides with the value set in the lower limit value setting register 32, the lower limit value detection output is generated. The upper limit value detection circuit 35 is composed of an AND gate circuit and generates an upper limit value detection output when receiving the value of each digit position of the counter 31 and matching with the value set in the upper limit value setting register 34. To do.

The flip-flop 36 is set to the lower limit value according to the output of the lower limit value detection circuit 33 (input to the set terminal (S terminal) of the flip flop 36), and the upper limit value detection circuit 35.
Is reset at the upper limit value according to the output (input to the reset terminal (R terminal) of the flip-flop 36). The data latch circuit 37 receives the horizontal synchronizing signal received from the input terminal 7 via the inverter 38 and the delay circuit 39 at its clock terminal (CK), and delays the Q output of the flip-flop 36 set at the lower limit value. The horizontal synchronizing signal is latched at the falling edge (or rising edge, in this example, falling edge, and the same applies hereinafter), and an output is generated. The counter 31 has the reset terminal (R) connected to the inverter 3
The horizontal synchronizing signal is input via the input terminal 7 via 8 and its count value is reset at the falling (or rising) timing thereof, and the clock of the clock generation circuit 3 starts counting from zero.

Here, the lower limit value register 32 stores the data of the lower limit timing position of the horizontal synchronizing signal, and the upper limit value register 34 stores the data of the upper limit timing position of the horizontal synchronizing signal. For example, the lower limit value register 32 has a μsec,
Data for bμsec is set in the upper limit register 34. In this way, the width of the horizontal synchronizing signal is a to bμ.
Flip-flop 36 when it is within the pulse width of sec
Q output is generated, the data is latched, the switch circuit 5 is turned “ON”, and a pseudo horizontal synchronizing signal of 15.73426 kHz is sent to the vertical synchronizing signal presence / absence determining circuit 6.

As for the overall operation, the counter 31 operates the input terminal 7
From the falling edge (or rising edge) of the horizontal synchronizing signal to the next falling edge (or rising edge) of the horizontal synchronizing signal, the clock of the clock generation circuit 3 is counted, and the count value is the lower limit value or the upper limit value. When it is between the values, the Q output to the flip-flop 36 (here, H output
An IGH level (hereinafter "H") is generated, and the data latch circuit 37 latches the Q output ("H") at the falling (or rising) of the horizontal synchronizing signal delayed from it. As a result, it is detected that the horizontal synchronizing signal arrives at a regular timing within the pulse width range of a to b μsec, and it is determined that the horizontal synchronizing signal is present. This determination signal is sent from the output terminal 40 to the switch circuit 5, and the switch circuit 5 outputs "O".
A pseudo horizontal sync signal synchronized with the horizontal sync signal is sent from the pseudo horizontal sync signal generation circuit 4 to the vertical sync signal presence / absence determination circuit 6. When there is no horizontal sync signal, the data latch circuit 37 , Q output (LOW level (hereinafter “L”)) is latched. Therefore, the switch circuit 5 remains “OFF” and the pseudo horizontal sync signal is not sent to the vertical sync signal presence / absence determination circuit 6.

The vertical synchronization signal presence / absence determination circuit 6 has the same configuration as the horizontal synchronization signal presence / absence determination circuit 3, and the difference is that the pseudo synchronization is obtained via the switch circuit 5 instead of receiving the clock from the clock generation circuit 3. The pseudo horizontal sync signal from the horizontal sync signal generating circuit 4 is received and counted, and the counter 41 is reset (its reset terminal (R)) by the vertical sync signal from the input terminal 8 instead of the horizontal sync signal. Then, the data latch circuit 47 latches the Q output of the flip-flop (F / F) 46 by the vertical synchronizing signal.

The lower limit setting register 42 is the lower limit setting register 3
2 is the same register, and the lower limit value detection circuit 43 is a detection circuit similar to the lower limit value detection circuit 33. The upper limit value setting register 44 is a register similar to the upper limit value setting register 34, and the upper limit value detecting circuit 45 is the upper limit value detecting circuit 3.
The detection circuit is the same as that of 5.

Therefore, the lower limit value register 42 stores the data of the lower limit timing position of the vertical synchronizing signal, and the upper limit value register 44 stores the data of the upper limit timing position of the vertical synchronizing signal. For example, in the lower limit value register 42 c csec
When data for setting dμsec is set in the upper limit register 44, a Q output is generated in the flip-flop 46 when the width of the vertical synchronizing signal is between c and dμsec.
The data is latched, and an output with a vertical signal is generated at the output terminal 9 from the data latch circuit 47.

The overall operation is almost the same as in the horizontal case except for the difference between horizontal and vertical, and the counter 41 uses the falling edge (or rising edge) of the vertical synchronizing signal as a reference to raise the next vertical synchronizing signal. The pseudo horizontal synchronizing signal received from the switch circuit 5 is counted until it falls (or rises), and when the count value is between the lower limit value and the upper limit value, the Q output (“H”) is output to the flip-flop 46. It is generated and latched by the data latch circuit 47 at the falling edge (or rising edge) of the vertical synchronizing signal which is delayed,
It is determined that the vertical synchronizing signal has arrived at regular timing within the range of c to dμsec pulse width, and the presence or absence of the vertical synchronizing signal is determined. This determination signal is output as a detection signal of the output terminal 8 with a vertical synchronizing signal. Therefore, when the output of the output terminal 8 is at the opposite level ("L") at the arrival timing of the vertical synchronizing signal (although it is delayed a little), there is no vertical synchronizing signal. This is because when it is determined that there is no horizontal sync signal and there are no pseudo horizontal sync pulses in the range set by the pseudo horizontal sync signal generation circuit 4, or when the pulse width of the vertical sync signal is a regular width. This is done when there is no vertical sync signal.

In this way, when the output terminal 8 remains "L" in response to the arrival of the vertical synchronizing signal, it is assumed that there is no vertical synchronizing signal, and this detection signal is sent to the circuit which internally generates the horizontal synchronizing signal and the vertical synchronizing signal. A horizontal synchronizing signal and a vertical synchronizing signal can be internally generated by adding as a start signal.

Therefore, in the superimpose operation and the like, it is possible to make a judgment that the horizontal sync signal is not easily affected by noise even when the situation is such as a weak electric field, and for the vertical sync signal, depending on the judgment result of the horizontal sync signal. The presence / absence of the pseudo horizontal sync signal can be determined more accurately on the basis of the pseudo horizontal sync signal generated at an accurate timing that is not affected by the electric field. Since the horizontal synchronizing signal is also time-measured by the reference clock from the clock generating circuit 3 in the embodiment, its pulse width can be accurately determined.

As a result, when there is no vertical sync signal, it is possible to reliably and automatically display an internal image such as a superimpose with the internal sync signal without external sync.
On the contrary, when there is a vertical synchronizing signal even in a weak electric field, the image display can be performed by external synchronization, and the switching can be performed accurately.

By the way, the data a, c, b, and d set in the lower limit value registers 32 and 42 and the upper limit value registers 34 and 44 are registers, so that the set values can be easily changed. Therefore, it is possible to change the setting according to the reception state even afterwards, and it is possible to detect the presence or absence of the vertical synchronization signal with higher accuracy according to the reception state.

By doing so, it is possible to add a superimpose image without synchronization to the external video signal and to accurately switch and display the composite image without being affected by the electric field strength in a weak electric field. Therefore, even if there is a weak electric field or electric field fluctuation, the switching operation is surely performed when necessary, and a clear image can be reproduced.

As described above, the determination circuit for the presence / absence of the horizontal synchronization signal and the vertical synchronization signal of the embodiment is configured by using the counter and the coincidence detection circuit, but this is an example, and it is one shot or various types. Of course, it can be configured by a combination of logic circuits.

Further, the pseudo horizontal synchronizing signal generating circuit does not have to have the same frequency of 15.73426 kHz as the horizontal synchronizing signal, and may be a pulse having a corresponding frequency such as an integral multiple or a fraction thereof.

[Effects of the Invention] As described above, according to the present invention, the horizontal sync signal presence / absence determination circuit and the vertical sync signal for determining the presence / absence of the horizontal sync signal depending on whether the horizontal sync signal is within a predetermined pulse width range A vertical synchronization signal presence / absence determination circuit for determining the presence / absence of a vertical synchronization signal depending on whether or not it is within a predetermined pulse width range is provided to perform two-stage determination, and the vertical synchronization signal presence / absence determination circuit generates a pseudo horizontal synchronization signal. Since the pulse width of the vertical sync signal is determined based on the pulse from the circuit, the horizontal sync signal can be determined less likely to be affected by noise even in a weak electric field, and the vertical sync signal can be determined. With respect to, the presence / absence of the pseudo horizontal sync signal can be determined more accurately based on the pseudo horizontal sync signal generated at an accurate timing that is not influenced by the electric field according to the determination result of the horizontal sync signal.

As a result, it is possible to detect the presence or absence of the vertical synchronization signal with high accuracy even in a weak electric field without affecting noise.

[Brief description of drawings]

FIG. 1 is a block diagram of a vertical sync signal presence / absence detection circuit to which the present invention is applied. 1 ... Vertical sync signal presence / absence detection circuit, 2 ... Horizontal sync signal presence / absence determination circuit, 3 ... Clock generation circuit, 4 ... Pseudo horizontal sync signal generation circuit, 5 ... Switch circuit, 6 ... Vertical sync signal presence / absence Judgment circuit, 7, 8 ... Input terminal, 9 ... Output terminal.

Claims (1)

[Claims] 1. A horizontal sync signal presence / absence determining circuit for determining the presence / absence of a horizontal sync signal depending on whether or not the horizontal sync signal extracted from the composite signal is within a predetermined pulse width range, and receiving the horizontal sync signal. In synchronization with this, a pseudo horizontal synchronizing signal generating circuit that generates a pulse signal of the same frequency as or a frequency corresponding to this, and a vertical synchronizing signal extracted from the composite signal are received, and in the determination of the horizontal synchronizing signal determination circuit. A vertical synchronization signal presence / absence determination circuit that counts the pulse signals when it is determined that there is a horizontal synchronization signal, and determines the presence / absence of a vertical synchronization signal based on whether the vertical synchronization signal is within a predetermined pulse width range. A vertical sync signal presence / absence detection circuit comprising: