JPH06204338A - Wiring method of semiconductor integrated circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] To adapt to the automatic wiring processing method for large-scale semiconductor integrated circuits, shorten the processing time, and minimize the memory used by the computer. A wiring processing method for a semiconductor integrated circuit, comprising: a rough wiring method for deciding an outline of a passage path of wiring; and a detailed wiring method for deciding an actual wiring laying position according to the result, which is a rough wiring processing. A method is to provide a general wiring 103 for the entire wiring area on a semiconductor integrated circuit chip,
According to the result, the partial area schematic wiring 106 and the like are formed for the partial area on the semiconductor integrated circuit chip.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring method for a semiconductor integrated circuit, and more particularly to a wiring processing method effective for automatic wiring processing using a computer.

[0002]

2. Description of the Related Art Various wiring processing methods such as a maze search method and a line search method have been announced as a wiring processing method for a semiconductor integrated circuit of this type. However, it is difficult to collectively process the entire wiring area on the semiconductor integrated circuit chip by the above method, because it increases the processing time and the memory used by the computer. Is becoming.

Conventionally, in order to solve this kind of problem, there is a method in which a wiring region on a semiconductor integrated circuit chip is divided into a plurality of partial regions, and the partial regions are set as a batch processing target region of the above method. According to this processing method, as shown in the flowchart in FIG. 8, before actually performing the wiring processing,
Rectangle generation 81 for rough wiring of input data 80, rough wiring 8
After the processing procedure called 2 is provided and the approximate wiring passage area is determined, the processing procedure such as the above-mentioned maze wiring method or line search method is performed based on the result of the processing procedure 83, 84, 85 called the detailed wiring processing. A method has been developed in which the wiring in the entire wiring area is processed by repeatedly performing the above for each partial area.

Hereinafter, such a schematic wiring method and a detailed wiring method will be described with reference to the drawings. FIG. 9 is a plan view symbolically showing a wiring region on a semiconductor integrated circuit chip, and each of the rectangles separated by a dotted line in the drawing is a region for allocating a wiring route at the time of rough wiring. Hereinafter, as shown in the drawing, a, b, c, ... In the column direction and 1, 2, 3 ,.
(B, 2), ..., And so on.

That is, in the rough wiring process 82,
For all the wiring areas on the semiconductor integrated circuit chip, which rectangular area is used to lay each wiring is determined. When deciding this wiring route, several preset conditions such as making the wiring density of each rectangular area as uniform as possible and minimizing the number of rectangular areas through which each wiring passes are satisfied as much as possible. The decision is made for the purpose of doing.

Regarding the result of this processing, the hatched portion in the figure is illustrated for the wiring between the terminals A and B, and these wirings are (a, 1), (b, 1), (c, 1), (c,
2) shows that it is determined to be wired using. Such route determination is performed for all wirings.

Next, detailed wiring processing will be described. In the detailed wiring processing, the wiring area on the semiconductor integrated circuit chip is divided, and the actual wiring is laid in the partial area using the maze search method or the like. At the time of this area division, in each partial area, a rectangular area for rough wiring located at the boundary is divided so as to be shared with an adjacent partial area. An example of this division method is h, i, j and 8, 9, 10 in the figure. In the detailed wiring below, this division (h, i, j) is performed.
8), (i, 4), ... Is repeatedly executed for each partial area.

In the detailed wiring 84 in each partial area, the laying position of the wiring assigned to the rectangle in the partial area by the general wiring 82 is determined only within the partial area, and the adjacent partial areas are determined. If the wiring is completed, the wiring that exits to that partial area is connected within the shared rectangular area for general wiring, and if it is not completed, each wiring is assigned in the wiring processing of this partial area. The shared rectangular area is drawn out to an arbitrary position, and the wiring is processed in the adjacent partial wiring area so that the same wiring is connected.

[0009]

According to this conventional wiring method, if each rectangular area for wiring path allocation at the time of rough wiring is finely set, the wiring path can be determined in detail over the entire wiring area. Therefore, a more optimized rough wiring result can be obtained, and the burden of the detailed wiring processing is reduced.

However, this means that the number of rectangular areas that must be considered at the time of the rough wiring increases, so that the processing time at the rough wiring and the memory space used by the program increase.

On the contrary, if each rectangular area is set to be large, the burden on the rough wiring is reduced, but this means that the partial area in which the route search must be performed in the detailed wiring becomes wider. Processing time, memory space used by programs, etc. increase.

That is, in this conventional wiring method, it is important to set the size of the rectangle for the rough wiring and the size of the divided area for the fine wiring in order to improve the processing efficiency. With the increase in scale, even this conventional method faces an increase in processing time and memory used.

The object of the present invention is to solve the above problems,
It is an object of the present invention to provide a wiring method for a semiconductor integrated circuit that can reduce the processing time and increase the memory used.

[0014]

The structure of the present invention is, in a wiring method of a semiconductor integrated circuit for connecting wiring between functional blocks arranged on a chip of the semiconductor integrated circuit, roughly determining a passage route of the wiring. In order to do so, a general wiring processing method for performing processing over the entire wiring area on the chip of the semiconductor integrated circuit, and a partial area of the wiring area on the chip of the semiconductor integrated circuit based on the result of the general wiring processing method And a wiring processing method for determining the wiring laying position in more detail than the general wiring processing method.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a flow chart showing a wiring method of a semiconductor integrated circuit of an embodiment of the present invention.

In FIG. 1, in this embodiment, the input data 101 of this processing system includes all information required by the processing system, such as circuit connection information, layout position information, and design rules. A wiring 103, a partial area schematic wiring 106, a detailed wiring 108 and the like are shown.

In the present processing system, the partial schematic global wiring area division 104 and the rectangular generation 105 are performed for the entire wiring area on the semiconductor integrated circuit chip by the general schematic wiring 103 following the general schematic wiring rectangle generation 102. The rough rough wiring is completed, and then the rough rough wiring, which is more detailed than the general rough wiring 103, is repeatedly executed by the partial area rough wiring 106 for each appropriately divided partial area on the chip (process 107). The actual wiring installation position is determined, and the process ends.

Next, with respect to this processing, the work division and processing procedure of each processing step will be specifically described with reference to FIG. 2 which symbolically shows the wiring region on the chip of the semiconductor integrated circuit. The whole of FIG. 2 shows the entire wiring region on the semiconductor integrated circuit chip, and as an example, a wiring for connecting the terminals A and B will be specifically described.

In this processing system, first, a rectangular area for overall schematic wiring is created by dividing the entire wiring area into a mesh shape by the processing of the overall schematic wiring rectangular creation 102 of FIG. The concrete example of this mesh is
2 is a dotted line in FIG. 2 and is a, b, and
c, ..., 1, 2, 3, ... In the row direction, and the divided areas are referred to as (a, 1), (b, 2) ,.

Next, the overall schematic wiring 103 of FIG. 1 determines which rectangular area of the semiconductor integrated circuit the wiring passes through. An example of this processing result is shown for the wiring that connects the terminals A and B, and it is shown in FIG. 3 that the rectangular region with hatching in the drawing is selected.

Next, the partial area rough wiring area division 104
By this processing, area division for partial processing rough wiring is performed.
This processing is illustrated in FIG. 4, where h, i, j in the column direction and 8, 9, 10 in the row direction are divided into (h, 8), (h,
9), ..., (j, 10) are divided into nine partial areas. In this processing, in order to ensure consistency among the divided areas, adjacent partial areas are divided so that the rectangular area for overall schematic wiring is shared.

Next, a rectangle for partial area general wiring is generated by the processing of the rectangle for partial area general wiring 105 in FIG. In this processing, a rectangle smaller than the rectangle for the overall schematic wiring is generated, so that the next partial area schematic wiring enables more detailed wiring allocation than the overall schematic wiring. This processing is illustrated in FIG. 5, which is an enlarged view of the divided area (h, 8), and the same subscripts as in FIGS. 2 to 4 represent the same things. The one-dot chain line in the figure indicates the divided area in this processing, and a in the column direction
, A2, ..., 11, 12, ... In the row direction.

Next, for each divided area, the partial area schematic wiring 1
06 is repeated to execute the divided area rough wiring. Here, this processing will be specifically described using the (h, 8) divided area. In this process, the overall schematic wiring 103 of FIG.
All wirings assigned to the area (h, 8) are divided by the processing 105, and (a1, 11), (a
2, 11), ..., And so on, through wirings are assigned to rectangles. This allocation processing is executed so as to be allocated to the partial area general wiring rectangles included in the general general wiring rectangles (a, 1), (b, 2), ... In the case of the wiring that should be connected across each divided area, such as the wiring between the terminals A and B, for the general rough wiring that is shared unless the rough wiring of the adjacent partial rough wiring divided areas is completed. Allocation of an arbitrary partial area general wiring rectangle within the rectangular area is performed, and if the general wiring is completed, the allocation is performed so as to be connected to the allocated partial general wiring rectangle.

This processing is illustrated for the wiring between the terminals A and B. In FIG. 6, the downward-sloping diagonally shaded portion shows a rectangle allocated by the overall schematic wiring, and the downward-sloping diagonally shaded portion is a partial area. The rectangle allocated by the schematic wiring is shown. Thus, the wiring starting from the point of terminal A is (a
2, 12), (a3, 12), (a3, 13), ... Are assigned, and since the schematic wiring of the adjacent partial areas is not performed, the assignment up to (c4, 33) is completed. .

In this way, when the partial area general wiring is completed for the entire wiring area, based on the result of the partial area general wiring, the detailed wiring 108 of FIG. By determining the laying position, the wiring process of the semiconductor integrated circuit is completed.

As described above, according to the wiring processing method of the present embodiment, the rough wiring is executed for all the wiring areas on the semiconductor integrated circuit chip, and based on the processing result, each of the appropriately divided partial areas is processed. In addition, by implementing more detailed rough wiring, there is provided means for hierarchical rough wiring.

Next, a wiring method according to another embodiment of the present invention will be described with reference to FIG. In FIG. 7, another embodiment of the present invention performs partial parallel wiring processing in parallel by utilizing the feature that the partial rough wiring processing is performed for each partial area.

Here, a first computer 70 and a second computer 90 are prepared. In the first computer 70, first, the same processing as that in FIG. 1 is sequentially performed with the overall schematic wiring rectangle generation 72, the overall schematic wiring 73, the partial area general wiring area division 74, and the partial area general wiring rectangle generation 75.

The next partial area rough wiring processing request 76
To the second computer 90, and in the second computer 90, the partial area schematic wiring 91 and the end report 92 are transmitted to the first computer 70. In the first computer 70, the partial area general wiring 77 is performed, and the processing is repeated until the entire area is completed (process 78). Finally, the detailed wiring 79 is performed, and the process ends.

As described above, in the present embodiment, a plurality of computers are used to parallelize the partial rough wiring processing, whereby a further high speed processing can be achieved.

[0031]

As described above, according to the present invention, the rough wiring is executed for the entire wiring area on the semiconductor integrated circuit chip, and based on the result of the processing, it is possible to further divide each of the appropriately divided partial areas. Since there is a means for performing hierarchical rough wiring by performing detailed rough wiring, the processing time can be shortened and the memory used by the program can be minimized as described below.

In the case of the processing method of determining the wiring route by the maze search method, when the wiring is executed collectively by the maze search method in the entire wiring area, the rough wiring is performed by the conventional method and the detailed wiring is performed by the maze search method. And the general outline wiring and the partial region outline wiring according to the present invention,
Regarding the case of performing detailed wiring by the maze search method,
See an overview of processing time and memory usage.

In the maze search method, grids for wiring (wiring grids) are set in the horizontal and vertical directions in the wiring area of the semiconductor integrated circuit, and the intersections (lattice points) of the vertical and horizontal grids are set. On the other hand, it is determined whether or not each wiring can pass, and the wiring is allocated on the wiring grid to determine the wiring route. Therefore, the processing time is mainly the square of the number of line grid points r and the total number of wiring lines P, except for the input processing and the output processing.
, And has an order of P × (r squared). In addition, the amount of memory being processed depends on the square of r because each grid point has or does not allow wiring passage.

Further, here, for simplification, in the rough wiring, the wiring route is assigned to the rough wiring rectangular area by the same method as the maze search method. The difference is that one rough wiring rectangular area is used. Considering that it is possible to allocate a plurality of wires to P, and the number of wires is P and the number of rectangles is the square of n, the processing time is P × (n square) and the memory usage is the square of n. I think it depends on.

First, in the case where all the wiring regions are collectively processed by the maze search method, the total number of wirings of the semiconductor integrated circuit is P, the horizontal wiring grid r, the vertical wiring grid r, and the total number of grid points. Assuming that the time required to search one grid is t and the memory usage amount per grid point is a, assuming that r is the second power, the processing time Tm and the maximum memory usage Mm are as follows.

Tm = P × t × (r squared) Mm = a × (r squared) In the conventional rough wiring processing, the wiring area of the semiconductor integrated circuit is defined as m as a partial area for detailed wiring. Divide by × m,
For simplification, consider a case in which the partial area and the general wiring rectangle are made the same.

In the rough wiring process, since there are m square power wiring rectangles, assuming that the memory usage amount per rough wiring rectangle is b, the processing time Tu1 and the used memory Mu1 are as follows.

Tu1 = P × t × (m squared) Mu1 = b × (m squared) In the detailed wiring process, the number of grids included in the partial area for the detailed wiring is r / m, The number of points is (square of r) / (square of m), and the average number of wirings assigned to a certain partial area by the rough wiring is P / (m
Squared), so processing time Tu2, used memory M
u2 is given by the following equation.

[0039]

Since there are (m squared) partial wiring areas for detailed wiring, the total processing time is given by the following equation.

[0041]

Here, this equation becomes the minimum when the square root of m = r, and becomes the following equation.

Tu = 2Ptr At this time, the maximum used memory Mu is as follows.

Mu = max (Mu1, Mu2) = max
(Br, ar) In the case of the wiring method according to the embodiment of the present invention, the same calculation is performed by dividing the region for partial schematic wiring into n × n and further dividing into m × m to form a detailed wiring partial region. According to the method, if the memory usage amount per rectangle for the overall schematic wiring is C, the processing time Tp1 for the overall schematic wiring and the memory amount Mp1
Becomes the following equation.

[0045]

Assuming that the memory usage amount per rectangle for partial schematic wiring is d, the processing time Tp2 and the memory usage amount Mp2 at the time of partial schematic wiring are given by the following equation.

[0047]

As described above, the processing time and the maximum memory used are determined according to “r squared” in the case of the collective maze search method, “r” in the conventional method, and 2/3 of r in the embodiment of the present invention. You can see that it will increase. Since r represents the number of wiring grids on the semiconductor integrated circuit, the effect of the present invention is
It is shown that the adaptation effect is more remarkable when the number of wiring grids is large, that is, the larger the semiconductor integrated circuit is.

[Brief description of drawings]

FIG. 1 is a flowchart showing a wiring method of a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is a symbolic plan view of a semiconductor integrated circuit showing a rectangular area for overall schematic wiring according to an embodiment of the present invention.

FIG. 3 is a plan view which symbolically shows a semiconductor integrated circuit showing a processing example of overall schematic wiring according to an embodiment of the present invention.

FIG. 4 is a symbolic plan view of a semiconductor integrated circuit showing a divided region for performing partial schematic wiring according to an embodiment of the present invention.

FIG. 5 is a plan view showing an enlarged rectangular area for partial schematic wiring of one embodiment of the present invention in a symbolic manner.

FIG. 6 is a plan view showing an enlarged schematic symbolically a processing example of partial schematic wiring according to an embodiment of the present invention.

FIG. 7 is a flowchart showing another embodiment of the present invention.

FIG. 8 is a flowchart showing a conventional wiring method for a semiconductor integrated circuit.

9 is a plan view of a semiconductor integrated circuit showing the conventional wiring method of FIG.

[Explanation of symbols]

 80,101 Input data 72,81,102 Rectangle generation 73,82,103 Overall schematic wiring 74,83,104 Area division 75,105 Partial rectangle generation 77,91,106 Partial schematic wiring 78,85,107 Process 79,84 , 108 Detailed wiring A, B terminals 70, 90 Computer 76 Processing request 92 Finish report

Claims (2)

[Claims] 1. In a wiring method of a semiconductor integrated circuit for connecting wiring between functional blocks arranged on a chip of the semiconductor integrated circuit, in order to roughly determine a passage route of the wiring, the wiring of the semiconductor integrated circuit is on the chip. Wiring processing method for performing processing over the entire wiring area, and laying wiring in more detail than the rough wiring processing method on a partial area of the wiring area on the chip of the semiconductor integrated circuit based on the result of the rough wiring processing method. And a wiring processing method for determining a position, the wiring method for a semiconductor integrated circuit. 2. The wiring method for a semiconductor integrated circuit according to claim 1, wherein the detailed wiring processing method is performed by parallel processing of a plurality of computers.