JPH06204411A - Composite semiconductor device and manufacture thereof - Google Patents

Abstract

(57) [Abstract] [Purpose] To improve the breakdown voltage of the parasitic bipolar transistor. [Structure] n-channel MOS field effect transistor T
_An n-type buried layer 35 is formed immediately below the p well layer 2 of ₁ , and the impurity concentration thereof is lower than the impurity concentration of the n ⁺ buried layer 31 used in the bipolar transistor T ₃ , and p
The well layer 2 is surrounded by a collector compensating n ⁺ diffusion layer 33 used in the bipolar transistor T ₃ except for a region in contact with the n well layer 3 in which the p-channel type MOS field effect transistor T ₂ is formed. Channel type MOS
The field effect transistor T ₁ and the p channel type MOS field effect transistor T ₂ are electrically separated from the bipolar transistor T ₃ .

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS field effect transistor in which an n-channel type MOS field effect transistor and a p-channel type MOS field effect transistor which are complementary to each other and a bipolar transistor are formed on the same semiconductor substrate. The present invention relates to a composite semiconductor device which is electrically separated from a bipolar transistor and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, a CMOS transistor and a bipolar transistor are formed on the same semiconductor substrate, and
As shown in FIG. 22, the composite semiconductor device in which the S field effect transistor and the bipolar transistor are electrically separated is shown in FIG. ”Higashidani
IEICE Technical Report VOL.ICD-89, No.139, PP.
9-14, 1989.) and IEEE literature [Journal of Soli
d-State Circuits (Douseki et al. "Fast-Acces BiCMOM
SRAM Architecture with a Vss Generator, IEEE SSC-
26, 4, pp. 513-517, 1991)], and a bipolar layer is formed directly under both well layers 2 and 3 of the n-channel MOS field effect transistor T ₁ and the p-channel MOS field effect transistor T _2. The n ⁺ buried layer 32 used in the transistor T ₃ is shared, and the p well layer 2 is surrounded by the n well layer 3 or the n ⁺ collector compensation layers 33 and 34.
By enclosing the MOS field effect transistor T ₁ ,
In this structure, T ₂ and the bipolar transistor T ₃ are electrically separated.

[0003]

However, in the composite semiconductor device having such a structure, in order to improve the performance of the bipolar transistor T ₃ , it is essential to make the epitaxial layer thinner.
In the MOS transistor T ₁ , the n ⁺ source / drain diffusion layers 21, 22 and the high-concentration n ⁺ buried layer 32 are close to each other, so that the n ⁺ source / drain diffusion layers 21,
22 is an emitter, high concentration n ⁺ buried layer 32 is a collector, p
There is a problem that the punch-through breakdown voltage of the parasitic vertical npn bipolar transistor based on the well layer 2 is lowered, and the punch-through current resulting from this becomes a latch-up trigger current, resulting in a drop in latch-up resistance.

Therefore, the present invention has been made to solve the above-mentioned conventional problems, and an object thereof is to provide a composite semiconductor device capable of improving the breakdown voltage of a parasitic bipolar transistor and a method for manufacturing the same. It is in.

[0005]

In order to achieve such an object, the present invention provides a MOS field effect transistor on a well layer of the first conductivity type and a MOS field effect transistor on the well layer of the second conductivity type which are complementary to each other. A composite semiconductor device in which a MOS field effect transistor and a bipolar transistor having a buried layer of the second conductivity type immediately below are formed on the same semiconductor substrate of the first conductivity type and electrically isolated from each other, A second conductivity type first buried layer is formed immediately below the first conductivity type well layer of the MOS field effect transistor, and the impurity concentration of the second conductivity type first buried layer is the same as that used in the bipolar transistor. A second conductivity type second buried layer having a lower impurity concentration and at least a first conductivity type well layer MOS field effect transistor is formed.
The periphery excluding the region in contact with the conductivity type well layer is surrounded by the second conductivity type high-concentration diffusion layer for collector compensation, and the second conductivity type of the second conductivity type used in the bipolar transistor is provided immediately below the second conductivity type well layer. A third buried layer of the second conductivity type having substantially the same impurity concentration as that of the second buried layer is formed to form a MOS field effect transistor on the well layer of the first conductivity type and a well layer of the second conductivity type. The MOS field effect transistor and the bipolar transistor are electrically separated.

[0006]

In the present invention, the second conductive type second buried layer (3 × 10 ¹⁹ cm 2) used in the bipolar transistor is used.
^-3 ), the first buried layer of the second conductivity type (1 × 10 ^{17 to} 3 × 10 ¹⁸ cm ⁻³ ) having an impurity concentration lower than that of the first conductivity type is directly below the well layer of the first conductivity type of the MOS field effect transistor. Therefore, the gate of the CMOS transistor and the substrate of the bipolar transistor are electrically separated.

[0007]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a cross-sectional view showing the structure of an embodiment of the composite semiconductor device according to the present invention. In the figure, 1
a is a p substrate, 1b is a p layer for separating bipolar transistors, 2 is a p well layer, 3 is an n well layer, 4 is an n collector layer, 11 is ap ⁺ diffusion layer for p base electrode, and 12 is an n ⁺ emitter. A diffusion layer, 13 a p base layer, 14 an element isolation layer,
Reference numerals 21 and 22 are n ⁺ source / drain diffusion layers, 23 is a p well contact diffusion layer, 24 and 25 are p ⁺ source / drain diffusion layers, 26 is an n well contact diffusion layer, 2
Reference numerals 7 and 28 are polysilicon gate electrodes.

Further, 31 and 32 are n ⁺ buried layers of the bipolar transistor, and the impurity concentration is 3 × 10 ¹⁹ cm ^-3.
Is. 33 and 34 are n ⁺ collector compensation layers, and 35 is n ⁺
The n-type buried layer has an impurity concentration lower than that of the buried layer 31 by one digit or more, and is about 1 × 10 ^{17 to} 3 × 10 ¹⁸ cm ⁻³ .

In the figure, n just below the p well layer 2 of the n-channel MOS field effect transistor, the impurity concentration is one digit lower than that of the n ⁺ buried layer 31 (3 × 10 ¹⁹ cm ^-3 ) used in the bipolar transistor. Mold burying layer 35 (1 × 10 ¹⁷
˜3 × 10 ¹⁸ cm ⁻³ ), and forming a bipolar transistor in the periphery except the region where the p well layer 2 and the n well layer 3 in which the p channel type MOS field effect transistor is formed are in contact with each other. The structure is surrounded by an n ⁺ diffusion layer 34 for collector compensation used in the p well layer 2
And the p substrate 1a of the bipolar transistor can be electrically separated.

FIG. 2 shows a plan view of an example of wrapping with the collector compensation layer described in FIG. The shaded region in the drawing is the n ⁺ collector compensation layer 34 that electrically separates at least the p-well layer 2 from the p-substrate 1a, and even if the periphery of the n-well layer 3 surrounded by the dotted line is added, the present invention can be realized. It is self-evident.

FIG. 3 shows an n-type epitaxial film thickness of 1.3 μm.
n ⁺ source / drain diffusion layer at m is an emitter, p
In a parasitic vertical npn bipolar transistor having a well layer as a base and an n-type buried layer as a collector, the experimental results of the withstand voltage BVceo between the collector and the emitter when the base is opened with respect to the peak impurity concentration of the n-type buried layer are shown. is there. The n-type buried layer peak impurity concentration uses the calculation result of the process simulator SUPREM. n-type embedding concentration of 10 ¹⁸ , 2.4 × 10 ¹⁷ , 1.2 × 10 ¹⁷ cm
By setting the concentration to ^-3 , the junction width of the p-well layer becomes deep and the base width is expanded, and the p-well layer / n-type buried interlayer depletion layer extends to the n-type buried layer side.

As a result, the conventional high-concentration n ⁺ buried layer (3
In comparison with the withstand voltage result of 3.5 V of the parasitic bipolar transistor in the isolation by (× 10 ¹⁹ cm ⁻³ ), the withstand voltage in this embodiment has an n-type buried concentration of 10 ¹⁸ , 2.4 × 10 ¹⁷ ,
5.1 V and 6.V for 1.2 × 10 ¹⁷ cm ⁻³ , respectively.
The breakdown voltage has been significantly improved by reducing the concentration to 2V and 13V.

4 to 9 are sectional views of steps for explaining an embodiment of the method for manufacturing the composite semiconductor device according to the present invention. First, as shown in FIG. 4, a thin silicon oxide film 101 having a film thickness of about 10 nm is formed on the surface of a p-type (100) silicon substrate 100 by thermal oxidation, and then an n-channel MO film is formed.
A resist pattern 102 that defines the p-well region of the S field effect transistor is formed by a normal photolithography method, and arsenic is accelerated at an acceleration voltage of 70 KeV and an implantation amount of 5 × 10 ¹² cm.
Ions are implanted under the condition of about ² to 5 × 10 ¹³ cm ² to form an arsenic ion implantation layer 103 in the silicon substrate 100.

Next, the resist pattern 102 is dissolved and removed with a mixed solution of sulfuric acid and hydrogen peroxide solution, and then annealed in a dry nitrogen atmosphere at a heat treatment condition of 800 ° C. for about 30 minutes,
As shown in FIG. 5, a normal pressure CV is formed on the silicon oxide film 101.
A silicon oxide film 104 having a film thickness of about 500 nm is deposited by the D (chemical vapor deposition) method. After that, p-channel MO
N well region in which the S field effect transistor is formed and n
A resist pattern 105 that defines the n-type buried region of the pn bipolar transistor is formed.

Next, using the resist pattern 105 as a mask, the silicon oxide film 101 formed by thermal oxidation and the atmospheric pressure CV are used.
After wet etching the silicon oxide film 104 formed by the D method with a buffered hydrofluoric acid solution or the like to open the silicon substrate 100 as shown in FIG. 6, the resist pattern 105 is dissolved with a mixed solution of sulfuric acid and hydrogen peroxide solution. And remove.

Next, as shown in FIG. 7, the silicon substrate 100 in the opening is oxidized in an oxygen atmosphere to form a silicon oxide film 106 having a film thickness of 75 nm, and then arsenic is applied to an accelerating voltage 70.
Ion implantation is performed under the conditions of KeV and an implantation amount of about 1.5 × 10 ¹⁶ cm ² .

After arsenic ion implantation, heat treatment is performed at 1100 ° C. for about 180 minutes in a mixed atmosphere of nitrogen and oxygen to diffuse arsenic into the silicon substrate 100 as shown in FIG. The embedded layer 107 is formed. By this heat treatment, the arsenic ion-implanted layer 103 becomes the high-concentration n-type buried layer 10
A low-concentration n-type buried layer 108 having a lower concentration than 7.

Thereafter, the silicon oxide film 101 and the silicon oxide film 104 are removed by wet etching with a buffered hydrofluoric acid solution or the like, and the n-type epitaxial layer 1 is formed as shown in FIG.
After forming 09, the formation of the n-type buried layer and the n-type epitaxial layer of the BiCMOS composite semiconductor device is completed.

When the n-type buried layer is formed by such a method, the p-type of the n-channel type MOS field effect transistor T ₁ is formed.
The concentration of the n-type buried layer immediately below the well layer is set to the p-channel type MOS.
It can be formed by lowering the concentration of the n-type buried layer formed immediately below the n-well layer of the field effect transistor T ₂ or the n-type buried layer of the npn bipolar transistor T ₃ by one digit or more.

10 to 17 are sectional views of steps for explaining another embodiment of the method for manufacturing a composite semiconductor device according to the present invention. First, as shown in FIG. 10, a silicon oxide film 114 with a thickness of about 500 nm is formed on the surface of a p-type (100) silicon substrate 100 by thermal oxidation, and then a p-channel MOS field effect transistor is formed. A resist pattern 115 that defines the n-well region and the n-type buried region of the npn bipolar transistor is formed by a normal photolithography method.

Next, using the resist pattern 115 as a mask, the silicon oxide film 114 is wet-etched with buffered hydrofluoric acid or the like as shown in FIG. 11 to open the silicon substrate 100, and then the resist pattern 115 is oxidized with sulfuric acid and peroxide. It is dissolved in a mixed solution of hydrogen water and removed.

Then, as shown in FIG. 12, the silicon substrate 100 in the opening is oxidized in an oxygen atmosphere to form a silicon oxide film 116 having a film thickness of 75 nm, and arsenic is accelerated to an acceleration voltage of 70K.
Ion implantation is performed under the conditions of eV and an implantation amount of about 1.5 × 10 ¹⁶ cm ² .

Next, as shown in FIG. 13, after annealing in a mixed atmosphere of nitrogen and oxygen under a heat treatment condition of 900 ° C. for about 30 minutes, a region to be a p well of the n-channel type MOS field effect transistor is determined. Resist pattern 11
Form 2.

Next, the silicon oxide film 114 implanted with arsenic ions is etched by using the resist pattern 112 as a mask, reactive ion etching, wet etching with buffered hydrofluoric acid, or a combination thereof, as shown in FIG.
The silicon substrate 100 is opened as shown in FIG.

Next, as shown in FIG. 15, the silicon substrate 100 in the opening is oxidized in an oxygen atmosphere to form a thin silicon oxide film 111 having a film thickness of about 10 nm, and then arsenic is accelerated at an acceleration voltage of 70 KeV and an implantation amount of 1. 5 × 10 ¹² cm ² to 5
Ions are implanted under the condition of about 10 ¹³ cm ² to form an arsenic ion implantation layer 113 in the silicon substrate 100 directly below the silicon oxide film 111.

Next, after arsenic ion implantation, heat treatment is performed at 1100 ° C. for about 180 minutes in a mixed atmosphere of nitrogen and oxygen to diffuse arsenic into the silicon substrate 100 to form a silicon oxide film 116 as shown in FIG. Silicon substrate 1 underneath
A high concentration n-type buried layer 117 is formed in 00. By this heat treatment, the arsenic ion-implanted layer 113 becomes the high-concentration n-type buried layer 1
A low-concentration n-type buried layer 118 having a lower concentration than 17.

After that, the silicon oxide films 111, 114,
116 is removed by wet etching with a buffered hydrofluoric acid solution or the like, and an n-type epitaxial layer 109 is formed as shown in FIG. 17 to form an n-type buried layer and an n-type buried layer of the BiCMOS composite semiconductor device.
The formation of the epitaxial layer is completed.

18 to 21 are sectional views of steps for explaining still another embodiment of the method for manufacturing the composite semiconductor device according to the present invention. First, as shown in FIG. 18, p-type (10
0) A film thickness of 10 is formed on the surface of the silicon substrate 100 by thermal oxidation.
After forming a thin silicon oxide film 121 of about nm,
A resist pattern 122 for defining the p-well region of the channel-type MOS field effect transistor is formed by a normal photolithography method, and arsenic is accelerated at an acceleration voltage of 70 KeV and an implantation amount of 1.5 × 10 ¹² cm ² to 5 × 10 ¹³ Ions are implanted under the condition of about cm ² to form an arsenic ion implantation layer 123 in the silicon substrate 100.

Next, the resist pattern 122 is dissolved and removed with a mixed solution of sulfuric acid and hydrogen peroxide, and then annealed under a heat treatment condition of 800 ° C. for about 30 minutes in a dry nitrogen atmosphere.
Next, as shown in FIG. 19, after forming a resist pattern 125 that defines the n-well region where the p-channel MOS field effect transistor is formed and the n-type buried layer region of the npn bipolar transistor, arsenic is used as an acceleration voltage. 70 Ke
Ion implantation is performed under the conditions of V and an implantation amount of about 1 × 10 ¹⁵ cm ² to form an arsenic ion implantation layer 130 in the silicon substrate 100.

Next, the resist pattern 125 is dissolved and removed with a mixed solution of sulfuric acid and hydrogen peroxide solution, and heat treatment is performed at 1100 ° C. for about 180 minutes in a mixed atmosphere of nitrogen and oxygen to remove arsenic from the silicon substrate. 20 diffused in 100
As shown in, the low concentration n-type buried layer 128 and the high concentration n-type buried layer 131 having a higher concentration than this are formed.

After that, the silicon oxide film 122 is removed by wet etching with a buffered hydrofluoric acid solution or the like to form an n-type epitaxial layer 109 as shown in FIG.
The formation of the n-type buried layer and the n-type epitaxial layer of the OS composite semiconductor device is completed.

The resist pattern 1 described with reference to FIG.
The step of forming 25 and the step of implanting arsenic ions may be performed before the step of forming the resist pattern 122 and the step of implanting arsenic ions described with reference to FIG.

[0033]

As described above, according to the present invention,
At least a second conductivity type first buried second layer of the second conductivity type surrounding the MOS field effect transistor and having a lower impurity concentration than the second buried layer
Since the CMOS gate and the substrate of the bipolar transistor can be electrically separated by the buried layer and the second conductivity type high-concentration diffusion layer for collector compensation, a thin epitaxial layer film for manufacturing a high-performance bipolar transistor. With respect to the thickness, the breakdown voltage between the second-conductivity-type high-concentration diffusion layer of the MOS field effect transistor and the second-conductivity-type first buried layer is significantly improved as compared with the conventional case. This makes it possible to realize a BiCMOS substrate structure that electrically separates the first conductivity type well layer having the ECL / TTL mixed circuit having the high-speed bipolar transistor and the first conductivity type semiconductor substrate. The effect is obtained.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a configuration according to an embodiment of a composite semiconductor device of the present invention.

FIG. 2 is a plan view showing an example of the surroundings of FIG. 1 and a collector compensation layer.

FIG. 3 is a diagram showing an experimental result of improving the breakdown voltage of a parasitic bipolar transistor.

FIG. 4 is a sectional view of a step illustrating an embodiment of the method for manufacturing the composite semiconductor device according to the present invention.

FIG. 5 is a sectional view of a step following the step of FIG. 4;

FIG. 6 is a sectional view of a step following the step of FIG. 5;

FIG. 7 is a sectional view of a step following the step of FIG. 6;

8 is a sectional view of a step following the step of FIG. 7. FIG.

FIG. 9 is a sectional view of a step following the step of FIG.

FIG. 10 is a sectional view of a step illustrating another embodiment of the method for manufacturing the composite semiconductor device according to the present invention.

FIG. 11 is a sectional view of a step following the step of FIG. 10;

FIG. 12 is a sectional view of a step following the step of FIG. 11;

FIG. 13 is a sectional view of a step following the step of FIG. 12;

FIG. 14 is a sectional view of a step following the step of FIG. 13;

FIG. 15 is a sectional view of a step following the step of FIG. 14;

FIG. 16 is a sectional view of a step following the step of FIG. 15;

FIG. 17 is a sectional view of a step following the step of FIG. 16;

FIG. 18 is a cross-sectional view of a step illustrating yet another embodiment of the method for manufacturing the composite semiconductor device according to the present invention.

FIG. 19 is a sectional view of a step following the step of FIG. 18;

FIG. 20 is a sectional view of a step following FIG. 19;

21 is a sectional view of a step following FIG. 20. FIG.

FIG. 22 is a cross-sectional view showing a configuration of a conventional composite semiconductor device.

[Explanation of symbols]

1a p substrate 1b p layer for separating bipolar transistors 2 p well layer 3 n well layer 4 n collector 11 base electrode p ⁺ diffusion layer 12 n ⁺ emitter diffusion layer 13 p base layer 14 element isolation layer 21 n ⁺ source Drain diffusion layer 22 n ⁺ source / drain diffusion layer 23 P well contact 24 p ⁺ source / drain diffusion layer 25 p ⁺ source / drain diffusion layer 26 n well contact 27 polysilicon gate 28 polysilicon gate 31 n ⁺ buried of bipolar transistor Buried layer 32 same as in the bipolar transistor process n ⁺ buried layer 33 n ⁺ collector compensation layer 34 n ⁺ collector compensation layer 35 n buried layer 100 p-type silicon substrate 101 silicon oxide film 102 resist pattern 103 arsenic ion implantation region 104 arsenic oxide Film 105 Resist pattern 1 06 silicon oxide film 107 high-concentration n-type buried layer 108 low-concentration n-type buried layer 109 n-type epitaxial layer 111 silicon oxide film 112 resist pattern 113 arsenic ion implantation region 114 silicon oxide film 115 resist pattern 116 silicon oxide film 117 high Concentration n type buried layer 118 Low concentration n type buried layer 121 Silicon oxide film 122 Resist pattern 123 Arsenic ion implantation region 125 Resist pattern 128 Low concentration n type buried layer 130 Arsenic ion implantation region 131 High concentration n type buried layer

Claims (3)

[Claims] 1. A MOS field effect transistor on a well layer of a first conductivity type and a MOS field effect transistor on a well layer of a second conductivity type which are complementary to each other, and a buried layer of a second conductivity type immediately below. A composite semiconductor device in which a bipolar transistor included therein is formed on the same semiconductor substrate of the first conductivity type and electrically isolated from each other, wherein a second semiconductor layer is provided at least directly under a well layer of the first conductivity type of the MOS field effect transistor. A conductive type first buried layer is formed, and an impurity concentration of the second conductive type first buried layer is a second conductive type second buried layer used in the bipolar transistor.
Lower than the impurity concentration of the buried layer, and at least the periphery of the first conductivity type well layer except for the region in contact with the second conductivity type well layer in which the MOS field effect transistor is formed is for collector compensation. A second conductivity type surrounded by a second conductivity type high-concentration diffusion layer and having an impurity concentration substantially the same as the second conductivity type second buried layer used in the bipolar transistor immediately below the second conductivity type well layer. 3. A composite semiconductor device having a third buried layer formed therein. 2. A second conductive film is formed on the main surface of the semiconductor substrate of the first conductivity type.
A step of selectively forming a conductive type first buried layer, and a second conductive type buried layer having a higher impurity concentration than the peak concentration of the second conductive type first buried layer on the main surface of the semiconductor substrate. A step of selectively forming a second buried layer and a third buried layer of a second conductivity type, and forming the first buried layer, the second buried layer and the third buried layer Forming an epitaxial layer on the first conductive type semiconductor substrate, a step of forming a first conductive type well layer on the epitaxial layer on the first buried layer, and the third buried layer. Forming a second conductive type well layer in the epitaxial layer on the buried layer; forming a second conductive type collector layer in the epitaxial layer on the second buried layer; The second conductive type high-concentration diffusion layer is formed around the well layer except for the region in contact with the second conductive type well layer. A step of forming a first MOS field effect transistor in the first conductive type well layer; a step of forming a second MOS field effect transistor in the second conductive type well layer; And a step of forming a bipolar transistor on the collector layer of two conductivity type. 3. A second surface is formed on the main surface of the semiconductor substrate of the first conductivity type.
A step of selectively forming a conductive type second buried layer and a third buried layer; and a second conductive type second buried layer and a third buried layer on the main surface of the semiconductor substrate. Selectively forming a first conductivity type first buried layer having an impurity concentration lower than the peak concentration of the buried layer; and the first buried layer, the second buried layer, and the third buried layer. Forming an epitaxial layer on the first-conductivity-type semiconductor substrate on which the layer is formed; forming a first-conductivity-type well layer on the epitaxial layer on the first buried layer; Forming a second conductivity type well layer in the epitaxial layer on the third buried layer; forming a second conductivity type collector layer in the epitaxial layer on the second buried layer; A high concentration of the second conductivity type is formed around the periphery of the first conductivity type well layer except for a region in contact with the second conductivity type well layer. Surrounding with a diffusion layer, forming a first MOS field effect transistor in the first conductivity type well layer, and forming a second MOS field effect transistor in the second conductivity type well layer. And a step of forming a bipolar transistor in the second-conductivity-type collector layer.