JPH0621026Y2 - Signal waveform display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a signal waveform display device for displaying a waveform of an input signal, and more particularly to a signal waveform display device having a simple structure and free of jitter. .

<Prior Art> In recent years, as a signal waveform display device for observing a waveform, a device has been used in which a signal is once converted into a digital signal and stored, and the waveform is displayed based on the stored data. The configuration of such a signal waveform display device is shown in FIG.
In FIG. 4, the input signal is input to the AD converter 1, converted into a digital signal in synchronization with the output of the free-run pulse generator 8, and stored in the memory 2. The input signal is also input to the trigger circuit 4. The trigger circuit 4 generates a trigger signal when the input signal reaches a preset trigger level. The change-over switch 28 selects either the trigger source of the trigger circuit 4 or the external trigger signal. This trigger signal is input to the sawtooth wave generator 5 for the time axis. The time axis sawtooth wave generator 5 generates a time axis sawtooth wave in synchronization with the trigger signal. This sawtooth wave is synchronized with the output of the free-run pulse generator 8
The digital signal is converted by the D converter 6 and stored in the memory 7. The data stored in the memories 2 and 7 is input to the Y-axis and X-axis of the display 3 and the waveform of the input signal is displayed.
The unblanking circuit 9 is for masking unnecessary display.

In such a signal waveform display device, since the input signal and the output of the free-run pulse generator 8 are generally asynchronous, the memory 2
If a few cycles of the input signal are held and displayed overlaid on each other, the starting point of the display portion will be shifted by a width of less than half the output cycle of the free-run pulse generator 8 and jitter will occur, making the waveform double and difficult to see. Become. Therefore, the time difference from the trigger point to the sampling point of the AD converter 1 is measured, and the display is corrected by the measurement result.

Such a time difference measuring circuit is shown in FIG. In this figure, the free-run pulse output from the free-run pulse generator 8 is input to the clock terminal of the flip-flop 10,
The output Q is input to the enable terminal EN of the counter 11. Further, the data terminal D is set to the low level. A clock for clock is input to the clock terminal of the counter 11. A trigger signal is input from the changeover switch 28 to the set terminal SET of the flip-flop 10 and the clear terminal CLR of the counter 11. The operation of this time difference measuring circuit will be described with reference to the time chart of FIG. When the trigger signal of (A) becomes low level at time, the flip-flop 10 is set, its output becomes high level as shown in (C), and the counter 11 is cleared. The enable input of the counter 11 becomes high level by the output of the flip-flop 10, and the counting of the clock for clock is started as shown in (E). When the free-run pulse rises at time, the output of the flip-flop 10 becomes low level, and the counter 11 stops counting. Therefore, the count value of the counter 11 is equal to the time difference between the rising edge of the trigger signal and the free-run pulse with the resolution of the clock cycle, and this time difference can be measured.

<Problems to be Solved by the Invention> However, in such a signal waveform display device, the resolution of the time difference signal for correcting the jitter is defined by the period of the clock for clocking. In a waveform display device such as a digital oscilloscope, the time axis is usually magnified hundreds of times for observation, but in order to prevent jitter from occurring even at such a high magnification, a timekeeping is used. The period of the clock for use must be sufficiently short. For example, the cycle of the free-run pulse is 1 MHz, and if the input signal is sampled at this cycle, the clock for clocking must be set to several hundred MHz, and expensive high-speed parts are required. .

In addition, correction is performed using both the trigger value at which the trigger signal is generated and the AD converter value at the rising edge of the freelance pulse that follows the trigger point at which the next trigger signal is generated, and the known trigger level value. There is also a method of improving the occurrence of jitter by carrying out the method (Japanese Patent Application No. Sho 62-12452 filed by the present applicant).
This device has a drawback that the value of the trigger is not always known and cannot be corrected when observing using a trigger signal input from the outside.

<Object of Invention> An object of the present invention is to provide a signal waveform display device capable of correcting jitter without using high-speed parts even when a trigger signal is input from the outside.

<Means for Solving Problems> The present invention relates to a signal waveform display device for sampling an input signal at a predetermined cycle, AD-converting it into a digital signal, and displaying the waveform of the input signal based on the digital signal. , A trigger signal generator that generates a trigger signal when the input signal reaches a predetermined level, and a free-run pulse that outputs a free-run pulse that is a rectangular wave with a fixed period while the input signal is being measured. A pulse generator, a first AD converter that converts the analog value of the input signal generated every time the free-run pulse is output from the free-run pulse generator into digital data, and immediately before the trigger signal is generated. A first register that holds the output of the first AD converter when a free-run pulse is generated; and a free-run pulse immediately after the trigger signal is generated. Second for holding an output of the first AD converter in the time of occurrence
Register, a second AD converter for converting an input signal into a digital signal at the time when the trigger signal generation unit or an external trigger signal is generated, and a value output from the second AD converter is held. And a computing unit that computes the time interval between the trigger signal and the sampling time point from the difference between the respective data using the buffer and the values held in the first and second registers, The signal waveform display device is characterized in that the display of the input signal is corrected by the output of the arithmetic unit.

<Embodiment> FIG. 1 shows an embodiment of a signal waveform display device according to the present invention. The same elements as those in FIG. 4 are designated by the same reference numerals and the description thereof will be omitted. In FIG. 1, reference numerals 20 and 21 are registers to which the output of the AD converter 1 is input. The outputs of the registers 20 and 21 are controlled by the control signal S. 22
Is a flip-flop, and the output of the trigger circuit 4 or an external trigger signal is input to the data terminal D thereof. 23
Is a flip-flop, and the output Q of the flip-flop 22 is input to the data terminal D thereof. 24 and 25 are A
It is an ND gate, and the outputs Q of the flip-flops 22 and 23 are input to its inverting inputs. Clock terminals of flip-flops 22 and 23 and AND gate 2
The output of the free-run pulse generator 8 is input to the non-inverting inputs of 4 and 25. The outputs of the AND gates 24 and 25 are input to the clock terminals of the registers 20 and 21. Two
Reference numeral 6 denotes an arithmetic unit, to which outputs of the registers 20 and 21 are input. Reference numeral 27 denotes a corrector, which is a memory 2 and a calculator 26.
The output of is input. The output of the compensator 27 is Y of the display unit 3.
Input to the axis. 29 is a sample for inputting the input signal
Hold circuit, 30 is this sample and hold circuit 29
AD converter for inputting the output of
It is a buffer that inputs the output of 0 and outputs it to the arithmetic unit 26. Sample and hold circuit 29 and AD converter 30
Is controlled by a trigger signal from the changeover switch 28. The output of the buffer 31 is controlled by the control signal S '.

Next, the operation of this embodiment will be described based on the time chart of FIG. In FIG. 2, (A) is a changeover switch 2
8 is a trigger signal, (B) is an output of the AD converter 30, (C) is a free-run pulse which is the output of the free-run pulse generator 8, and (D) and (E) are flip-flops 22 and 23. Output, (F) is the output of the AD converter 1,
(G) and (H) are outputs of the registers 20 and 21. A
The D converter 1 converts the input signal into a digital signal and outputs it in synchronization with the rising edge of the free-run pulse. D of (F)
_{n-1 to} D _{n + 2} represent the converted data. When the trigger signal becomes high level at time, the output of the flip-flop 22 becomes high level at a time slightly delayed from the rise of the next free-run pulse, and further at a time slightly delayed from the rise of the next free-run pulse. The output of group 23 goes high. Before the time when the output of the flip-flop 22 becomes high level, AND
The output of gate 24 changes in the same way as a free run pulse. Therefore, the same data as the output of the AD converter 1 is stored in the register 20. Flip-flop 22 at time
Since the output of the AND gate 24 is fixed to the low level when the output of the AD signal becomes high, the register 20 holds the output D _n of the AD converter 1 immediately before the time when the trigger signal becomes the high level. Similarly, since the output of the flip-flop 23 becomes high level at time, the AD converter 1 immediately after the time when the trigger signal becomes high level is stored in the register 21.
The output of D _{n + 1} is held. This register 2
The data held in 0 and 21 are input to the calculator 26 by the control signal S. The input signal is also held at the analog value in the sample and hold circuit 29 at the rising edge of the trigger signal and digitized by the AD converter 30. The signal S obtained as a result is a trigger level and is taken into the arithmetic unit 26 at an appropriate timing via the buffer 31.

The operation of the calculator 26 will be described with reference to FIG. As shown in FIG. 3, the rising times of the free-run pulse immediately before and after the rising of the trigger signal are T ₁ and T ₃ , the magnitudes of the input signals at these times, that is, the registers 20 and 21.
D _n, D _n + ₁ of the data stored _in, T ₂ the rise time of the trigger _signal, S ₁ size i.e. the trigger level input signal at that _time, when the period of free run pulse is T, the time T ₃ The time difference Δt between T ₂ and T ₂ can be calculated by Δt = T × | D _{n + 1} −S ₁ | / | D _{n + 1} −D _n |. However, it is assumed that the input signal changes linearly between adjacent sample points. Trigger level S ₁
Is obtained from the buffer 31 and the arithmetic unit 26 executes the above calculation. The calculation result is input to the corrector 27. The corrector 27 delays the data read from the memory 2 by this Δt and outputs it to the display 3. By doing so, even if the input signals are displayed multiple times, the trigger point always comes to the same point on the display unit, so that jitter does not occur. Since a circuit for detecting the level of the input signal at the trigger point is added, the above function can be realized regardless of the trigger source.

Although the arithmetic unit 26 is separately configured in this embodiment, it may be executed by a processor that controls the entire apparatus.

Further, when the changeover switch 28 is set to the internal trigger mode position, the known trigger level S ₁ used in the trigger circuit 4 can be used as it is for calculation without using the AD converter 30 or the like.

<Effect of Device> As specifically described above based on the embodiment, in this device, the magnitude of the input signal before and after the trigger point and the trigger level are detected to calculate the time difference between the trigger point and the sampling point. The display is corrected based on this calculation result. Therefore, even when the trigger signal is input from the outside, the jitter can be reduced with a simple and inexpensive configuration without using high-speed parts.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a signal waveform display device according to the present invention, FIG. 2 is a time chart showing the operation, FIG. 3 is a diagram for explaining a calculation method, and FIG. 5 is a block diagram showing the configuration of the signal waveform display device of FIG. 5, FIG. 5 is a configuration diagram of a conventional circuit for measuring a time difference, and FIG. 6 is a time chart showing its operation. 20, 21 ... Register, 22, 23 ... Flip-flop, 24, 25 ... AND gate, 26 ... Arithmetic unit,
27 ... Corrector, 30 ... AD converter.

Claims (1)

[Scope of utility model registration request] 1. A signal waveform display device for sampling an input signal at a predetermined cycle, AD-converting the input signal into a digital signal, and displaying the waveform of the input signal based on the digital signal, wherein the input signal has a predetermined level. A trigger signal generator that generates a trigger signal when the input signal is reached, a free-run pulse generator that outputs a free-run pulse that is a rectangular wave with a fixed period while the input signal is being measured, and the free-run pulse described above. A first AD converter that converts an analog value of an input signal every time a free-run pulse output from a generator is generated into digital data; and the first AD converter when the free-run pulse is generated immediately before the trigger signal is generated. A first register for holding the output of the A / D converter No. 1, and the first A when the free-run pulse is generated immediately after the trigger signal is generated. Second for holding the output of the converter
Register, a second AD converter for converting an input signal into a digital signal at the time when the trigger signal generation unit or an external trigger signal is generated, and a value output from the second AD converter is held. And a computing unit that computes the time interval between the trigger signal and the sampling time point from the difference between the respective data using the buffer and the values held in the first and second registers, A signal waveform display device characterized in that the display of the input signal is corrected by the output of the arithmetic unit.