JPH0621047A - Semiconductor device and manufacture thereof - Google Patents

Abstract

(57) [Summary] [Object] To provide a semiconductor device capable of suppressing the occurrence of a narrow channel effect and maintaining a PN junction breakdown voltage, and a manufacturing method thereof. [Structure] A step of forming a Si ₃ N ₄ film 3 on a Si substrate 1, a step of forming an opening in the Si ₃ N ₄ film 3 to expose the substrate 1, and a sidewall spacer 8 in the opening.
, A step of forming an etching region 9 by etching the Si substrate 1 using the sidewall spacers 8 as a mask, and a step of forming an element isolation film 7 of SiO ₂ by thermal oxidation in the etching region 9. And a step of forming the p ⁺ diffusion region 10 under the element isolation film 7 by ion implantation, and removing the sidewall spacers 8.
A step of forming an n ⁻ diffusion region 11 as an electrolytic relaxation region at a boundary portion between the n ⁺ diffusion region 12 and the p ⁺ diffusion region 10 in the element formation region is performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a technique for forming a fine element isolation film by a local oxidation method.

[0002]

2. Description of the Related Art A conventional method for forming an element isolation region is
For example, the best known local oxidation method (LOCO) today
S: Local Oxidation of Silicon), or an improved COSMOS method (Controlled Sidewall Masking Ox)
idation of Silicon) (Takuo Kanno, Ultra High Speed MOS Device, P135-146, see Baifukan).

FIG. 1 is a schematic sectional view showing a step of forming an element isolation region by the LOCOS method. First, Fig. 1
As shown in (a), a SiO ₂ film 2 is formed on a p-type Si substrate 1 by thermal oxidation, and Si ₃ N 2 is formed on the SiO ₂ film 2 by a CVD method.
₄ Deposit the film 3.

Next, as shown in FIG. 1B, a photoresist 4 is formed in the element formation region, and boron ions are ion-implanted into the element isolation region using this as a mask. This region serves as a channel stopper region for preventing an inter-element parasitic channel from being generated in the element isolation region.

Using the photoresist 4 as a mask, Si ₃ N ₄
After etching the film 3 and removing the photoresist 4,
Oxidize at 1000 ° C. in an O ₂ / H ₂ O atmosphere. At this time S
Since the i ₃ N ₄ film 3 has strong oxidation resistance, as shown in FIG. 1C, the SiO ₂ film 2 is formed only in the device isolation region without being oxidized in the device forming region.

Then, as shown in FIG. 1 (c), Si ₃
The N ₄ film 3 and the thin SiO ₂ film 2 thereunder are removed to expose the Si substrate in the element formation region. In this way, the element isolation region can be formed.

FIG. 2 is a schematic sectional view showing a step of forming an element isolation region by the COSMOS method. Figure 2
As shown in (a), the SiO ₂ film 2 and Si ₃ N are formed on the Si substrate.
_{4 The} film 3 is deposited in this order, the opening 5 is formed in the element isolation region by using the photoresist 4 as a mask, and the Si substrate 1 is exposed. Then, as shown in FIG. 2B, the photoresist 4 is again used as a mask to perform isotropic plasma etching of the Si substrate 1 to form an opening 6 having a U-shaped bottom. Due to the undercut action of the opening 6, Si
The lower part of the O ₂ film 2 is partially etched so that it is formed wider than the opening 5. At this time, the Si ₃ N ₄ film 3 is Si
Since the etching rate is close to that of the substrate 1, the Si ₃ N ₄ film 3
Although the end portion also recedes, the etching conditions are set so that the opening width of the Si ₃ N ₄ film 3 is narrower than the width of the opening portion 6.

After removing the photoresist 4, FIG.
As shown in (c), the portion of the SiO ₂ film 2 protruding above the opening 6 is removed, and the SiO ₂ film 2 is formed again in the opening 6 by thermal oxidation. Furthermore, by the LPCVD method, S
The i ₃ N ₄ film 3 is formed. Si ₃ N ₄ by this LPCVD
Since the film 3 has good step coverage, the opening 6
Is deposited on the entire surface of the SiO ₂ film 2 formed on the U-shaped bottom.

As shown in FIG. 2D, the opening 6 is anisotropically etched to leave the Si ₃ N ₄ film 3 only on the side wall of the U-shaped bottom of the opening 6. Then, as shown in FIG. 2E, the SiO ₂ film 2 is formed on the bottom of the opening 6 by thermal oxidation.
To form SiO ₂ in the opening 6 as an element isolation oxide film.
Form 7. The SiO ₂ 7 pushes up the Si ₃ N ₄ film 3 left on the side wall of the U-shaped bottom of the opening 6 and grows until the surface of the Si substrate 1 is at the same height. In this way
A flat element isolation region having no step is formed.

[0010]

In the LOCOS method, when the SiO ₂ film (thermal oxide film) 2 is formed in the element isolation region, a wedge shape is formed near the boundary between the element formation region and the element isolation region. Grow to. Since the wedge region called bird's beak is formed, there is a problem that the element isolation region width is expanded.

Further, the SiO ₂ film 2 in the element isolation region is made of Si.
Since it swells and grows on the substrate, a step is formed with the Si substrate in the element formation region. There is a problem that this step becomes an obstacle in the process in the element forming process or the device forming process.

Further, in the above-mentioned COSMOS method, Si
Since the thermal oxide film is formed after etching the substrate, no step is formed between the element formation region and the element isolation region. However, since the opening 6 formed in the Si substrate 1 is formed wider than the opening 5 formed at the lithography limit,
There is a problem that the width of the element isolation region is expanded.

It is also known that in the process of forming the element isolation region, channel stop ions are ion-implanted in order to prevent the formation of an inter-element parasitic channel in the element isolation region. The ion implantation, as shown in step 1, there are a method to be performed before the formation of the thermal oxide film such as SiO _2, a method performed after formation of the thermal oxide film of SiO ₂ or the like.

In the former method, since the heat treatment is carried out after the ion implantation, the implanted ions are diffused by heat to increase the narrow channel effect of the transistor, which raises the voltage threshold of the transistor. was there.

Further, in the latter method, a PN junction having a steep concentration gradient is formed between the diffusion region of the element formation region and the diffusion region formed by ion implantation, so that the breakdown voltage of this portion is increased. There is a problem that the deterioration becomes worse and the generated leak current becomes large.

The present invention relates to a semiconductor device and a method of manufacturing the same, and solves such a problem.

[0017]

A semiconductor device according to the present invention has an oxide film for separating an element formation region on a semiconductor substrate, and a diffusion region of the element formation region is provided below the oxide film. A diffusion region having a conductivity type opposite to that of the diffusion region of the element formation region and a diffusion region of the opposite conductivity type are formed at a boundary portion between the diffusion region of the element formation region and the diffusion region of the element formation region. A low electron relaxation region is formed.

In the above semiconductor device, the oxide film, the diffusion region of the element isolation region, and the diffusion region of the opposite conductivity type are not particularly limited. For example, the oxide film is formed after the diffusion region of the element isolation region is formed. You may form.

Further, according to the present invention, in a method of manufacturing a semiconductor device having an oxide film for separating an element forming region on a semiconductor substrate, a step of forming an oxidation resistant mask film on the semiconductor substrate, and the oxidation resistant mask film. A step of forming an opening in the substrate to expose the substrate, a step of forming a sidewall spacer in the opening, and a step of etching the semiconductor substrate with the sidewall spacer as a mask to form an etching region. A step of forming a thermal oxide film in the etching region, a step of forming a diffusion region of a conductivity type opposite to that of the diffusion region of the element forming region by ion implantation under the thermal oxide film, and the sidewalls The spacer is removed, and an electrolytic relaxation region is formed by ion implantation at the boundary between the diffusion region of the element formation region and the diffusion region of the opposite conductivity type. It is performed and the degree.

[0020]

That is, the electron relaxation region is formed at the boundary between the diffusion region of the element formation region and the diffusion region of the opposite conductivity type, so that the electrons of the diffusion region of the opposite conductivity type are formed in the element formation region at the boundary portion. In this way, the narrow channel effect is suppressed by preventing the advance in the direction.

Further, in the method of manufacturing a semiconductor device according to the second aspect, since the sidewall spacer is formed in the opening formed within the limit of the lithographic technique and the thermal oxide film is formed using this as a mask, the thermal oxide film is formed. The width of the oxide film, that is, the width of the element isolation region can be made smaller than the limit of the lithography technique.

Further, since the electrolytic relaxation region is formed,
It is possible to suppress a decrease in PN junction breakdown voltage caused by implanting ions for a channel stopper after forming the thermal oxide film. Further, since the thermal process is not performed after the ion implantation, the occurrence of the narrow channel effect is suppressed.

[0023]

Embodiments of the present invention will be described below with reference to the drawings.

3 and 4 are schematic sectional views at the stage of forming the element isolation region. As shown in FIG. 3A, the Si ₃ N ₄ film 3, the SiO ₂ film 2 and the Si ₃ N ₄ film 3 are sequentially formed on the p-type Si substrate 1 by the CVD method.

Next, after forming an opening in the element isolation region with a size limit of the lithography technique by the lithography technique, Si ₃ N ₄ is deposited on the entire surface, and this is anisotropically etched back by the RIE method. As shown in FIG. 3B, Si ₃ N ₄ sidewall spacers 8 are formed on the sidewalls of the opening.

Next, as shown in FIG. 3C, the exposed portions of the Si substrate 1 are isotropically etched using the sidewall spacers 8 as masks to form etching regions 9. Then, as shown in FIG. 3D, thermal oxidation is performed to form an element isolation film 7 of SiO _{2 in} the etching region 9. In this thermal oxidation process, the SiO ₂ film 2 becomes the Si ₃ N ₄ film 3
Due to the difference in the coefficient of thermal expansion between and, it is a stress relaxation layer.

As shown in FIG. 4E, p-type impurities (
⁽¹¹ B ⁺ ion) as a channel stop ion, ion implantation is performed by an ion implantation method under the conditions of an acceleration voltage of 200 KeV and a dose amount of 3 × 10 ¹² cm ⁻² , and a p ⁺ diffusion region 1 is formed.
Form 0.

As described above, since the ion implantation is performed after the thermal process for forming the element isolation film 7, the thermal process is not performed after the ion implantation and the occurrence of the narrow channel effect can be suppressed.

Next, the sidewall spacers 8 and 8 are heated.
Phosphoric acid (Hot H₃PO_Four) Is used to remove. At this time the top layer
Si₃N_FourThe film 3 is also removed, SiO₂Etching with membrane 2
Will stop. Then, as shown in FIG.^-Expansion
The dispersed areas 11 and 11⁺Formed above diffusion region 10
Conditions (for example, acceleration voltage 200 KeV, dose amount 3 × 10
¹²cm^-2) Is an n-type impurity (³¹p⁺Ion) ion
inject.

Since the n ⁻ diffusion regions 11 and 11 are formed using the SiO ₂ film 2 as a mask, they are wider on both sides than the p ⁺ diffusion region 10 of the channel stop ions.

Next, as shown in FIG. 4 (g), SiO ₂
The film 2 and the Si ₃ N ₄ film 3 are removed. n-type impurities ( ⁷⁵ A
s ⁺ ion) acceleration voltage 40 KeV, dose 5 × 10
Ion implantation is performed under the condition of ¹⁵ cm ^-2 to n ⁺
The diffusion regions 12 and 12 are formed. Thus, the n ⁻ diffusion regions 11 and 11 are the same as the n ⁺ diffusion regions 12 and 12 and the p ⁺ diffusion region 1, respectively.
It is located at the boundary with 0 and serves as an electrolytic relaxation region. By forming this electrolytic relaxation region, the concentration of the p ⁺ diffusion region 10 can be increased, so that it is possible to suppress the decrease in the PN junction breakdown voltage caused by the ion implantation for the channel stop after the thermal process.

Further, this electrolytic relaxation region can be formed in a self-aligned manner by removing the sidewall spacers 8 by etching and implanting ions.

[0033]

According to the semiconductor device of the first aspect of the present invention, the electron relaxation region is formed at the boundary portion between the diffusion region of the element formation region and the diffusion region of the opposite conductivity type. In the above, since electrons in the diffusion region of the opposite conductivity type are prevented from advancing toward the element formation region, the narrow channel effect of the transistor can be suppressed.

In the method of manufacturing a semiconductor device according to a second aspect of the present invention, since the side wall is provided in the opening formed at the limit of the lithographic technique and the element isolation region is etched using this as a mask, the element isolation region is etched. The width of the region can be reduced, and further, the element isolation region can be formed with good flatness.

Ion implantation is performed after the oxide film is formed,
Further, since the electrolytic relaxation region is formed, the element isolation region can be formed while suppressing the narrow channel effect and maintaining the PN junction breakdown voltage.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view showing a step of forming an element isolation region by a conventional LOCOS method.

FIG. 2 is a schematic sectional view showing a process of forming an element isolation region by a conventional COSMOS method.

FIG. 3 is a schematic cross-sectional view at a stage of forming an element isolation region according to an example of the present invention.

FIG. 4 is a schematic cross-sectional view at a stage of forming an element isolation region according to an embodiment of the present invention.

[Explanation of symbols]

1 Si substrate (semiconductor substrate) 2 SiO ₂ film 3 Si ₃ N ₄ film 4 photoresist 5, 6 opening 7 element isolation region 8 sidewall spacer 9 etching region 10 diffusion region (reverse conductivity type diffusion region) 11 diffusion region (Electron relaxation region) 12 Diffusion region (Diffusion region of element formation region)

Claims (2)

[Claims] 1. A semiconductor substrate having an oxide film for separating an element formation region, wherein a diffusion region having a conductivity type opposite to that of the diffusion region of the element formation region is formed below the oxide film. An electron relaxation region of the same conductivity type as the diffusion region of the element formation region and having a low concentration is formed at a boundary portion between the diffusion region of the device formation region and the diffusion region of the opposite conductivity type. Semiconductor device. 2. A method of manufacturing a semiconductor device having an oxide film for separating an element formation region on a semiconductor substrate, the method comprising: forming an oxidation resistant mask film on the semiconductor substrate; and forming an opening in the oxidation resistant mask film. Forming and exposing the substrate, forming a sidewall spacer in the opening, etching the semiconductor substrate using the sidewall spacer as a mask to form an etching region, and etching the region A step of forming a thermal oxide film on the substrate, a step of forming a diffusion region of a conductivity type opposite to that of the element formation region by ion implantation below the thermal oxide film, and removing the sidewall spacers. A step of forming an electrolytic relaxation region by ion implantation at the boundary between the diffusion region of the element forming region and the diffusion region of the opposite conductivity type. And a method for manufacturing a semiconductor device.