JPH0621076A - Semiconductor device - Google Patents

Abstract

(57) [Summary] [Object] The present invention relates to a protection device for protecting a semiconductor circuit from static electricity, and an object thereof is to realize a self-aligned bipolar transistor as an emitter-base short-circuit protection device. The structure is such that the area of an emitter layer 19 of a self-aligned bipolar transistor used as an emitter-base short-circuit protection element is made larger than that of the self-aligned bipolar transistor of an internal circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to improvement of the quality of a protection element for protecting a semiconductor circuit from static electricity against electrostatic breakdown (EDS resistance).

[0002]

2. Description of the Related Art In order to protect a semiconductor circuit from static electricity entering a semiconductor device, a protection element 32 is connected to input / output terminals T ₁ and T ₂ of an internal circuit 31, as shown in FIG. Protective element 3 protects static electricity from the outside
It is discharged to the ground wire GND through 2 and static electricity is generated in the internal circuit 31.
I try not to break into.

In such a semiconductor device, while a normal data signal is input to and output from the internal circuit 31, several hundred to
Since it is necessary to flow only a static electricity of several thousand V to the protection element 32, the protection element 32 is generally used that utilizes the breakdown phenomenon of a pn junction of a diode or a bipolar transistor.

When a bipolar transistor is used, one having the same structure as the transistor formed in the internal circuit 31 is used, and the emitter E and the base B are short-circuited as shown in FIG. 3 (b), for example. There is a protective element 32.

By the way, in the bipolar transistor,
As shown in FIG. 4D, the p-type impurities contained in the base extraction electrode 41 and the emitter electrode 42 made of polycrystalline silicon are solid-phase diffused into the n-type silicon layer 43 to form the external base layer 44 and the emitter layer 45. And a side wall 46 on the side of the emitter electrode 42 is used to reduce the area S ₁ of the emitter layer 45 and reduce the junction capacitance.

Next, a process of forming this bipolar transistor will be briefly described. First, as shown in FIG. 4A, after a selective oxide film 47 for surrounding the base region and the collector extraction region is formed on the surface of the silicon layer 43, a polycrystalline silicon film 48 containing boron and a SiO ₂ film are formed. By laminating 49 and patterning these, a base extraction electrode 41 having an opening 50 in the internal base region is formed. The silicon layer 43 in this case is applied as a collector.

After that, boron is ion-implanted through the opening 50, and then the boron is activated by annealing to form the internal base layer 51 in the silicon layer 43, and the boron in the base extraction electrode 41 is converted into the silicon layer. Solid-phase diffusion is performed on 43 to form an external base layer 44.

Next, as shown in FIG. 4 (b), the surface of the internal base layer 51 and the side portion of the base extraction electrode 41 are thermally oxidized.
The SiO ₂ film 52 is grown. Subsequently, as shown in FIG. 4 (c), polycrystalline silicon 53 containing phosphorus is entirely grown and then anisotropically etched vertically to form a base extraction electrode around the internal base layer 51. The polycrystalline silicon 53 is left on the sidewall of 41 to form a sidewall 46, and an opening 54 is formed on the internal base layer 44 surrounded by the sidewall 46.

Next, after the polycrystalline silicon film 55 containing phosphorus is formed on the entire surface, phosphorus is solid-phase diffused from the polycrystalline silicon film 55 in the opening 54 defined by the sidewalls 46 to form the internal base layer 51. N ⁺ type emitter layer 4 on the upper layer
5 is formed (FIG. 4 (d)).

After this, an aluminum film 56 is deposited,
This and the polycrystalline silicon film 55 are patterned to form the emitter electrode 42 on the emitter layer 45. In addition, as shown in the drawing, the emitter electrode 4 is passed through the contact hole 56.
By connecting 2 and the base extraction electrode 41, the emitter-base short-circuit type protection element 32 as shown in FIG. 3B is formed.

In the figure, reference numeral 57 indicates an n ⁺ -type collector extraction layer formed on the side of the external base layer 44 via the selective oxide film 47, and reference numeral 58 indicates a collector electrode formed thereon. .

[0012]

However, if the bipolar transistor having such a structure is used as it is as the emitter-base short-circuit protection element 32, the area S ₁ of the emitter layer 45 is used for the internal circuit 31. Since it has the same structure as the self-aligned transistor and is small in size, electrostatic stress is applied to the interface between the emitter layer 45 and the base layer 44, cracking is likely to occur, and the protective element leaks.

Therefore, an emitter-base short-circuit type transistor which employs a self-aligned bipolar transistor has not been employed. The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device capable of realizing a self-aligned bipolar transistor as an emitter-base short-circuit protection element.

[0014]

[Means for Solving the Problems]
2 and 4, a first inner base layer 51 surrounded by a first outer base layer 44 and the first inner base layer
The first emitter layer 45 is formed on the upper layer of 51, and the first collector layer 43 is formed below the first outer base layer 44 and the first inner base layer 51. A second internal base layer 9 surrounded by a second external base layer 10 while forming a bipolar transistor in the internal circuit.
A second emitter layer 19 formed on the upper part of the second internal base layer 9 and having a larger area than the first internal emitter layer 45, the second external base layer 10 and the second internal base layer 10. Second collector layer 1 formed below the internal base layer 9 of
An emitter-base comprising a base extraction electrode 7 formed on the second external base layer 10, an emitter electrode 21 connected to the second emitter layer 19 and the base extraction electrode 7. This is achieved by a semiconductor device having a short-circuit type protection element.

[0015]

[Operation] According to the present invention, when the emitter layer 19 and the base layer 10 of a self-aligned bipolar transistor are short-circuited and used as a protective element, the area of the emitter layer 19 is the self-aligned bipolar transistor of the internal circuit. Wider than the emitter layer 45 of.

For this reason, the electrostatic stress applied to the interface between the emitter layer 19 and the internal base layer 9 of the protective element is reduced, cracking is less likely to occur, and the protective element can be applied.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. 1 and 2 are cross-sectional views showing a manufacturing process of an embodiment of the present invention.

First, a process of forming a bipolar transistor up to the state shown in FIG. 1A will be described. First, the base region X and the collector region Y of the n-type silicon layer 1
A selective oxide film 2 is formed on the surface of the portion surrounding the, and then phosphorus is ion-implanted into the collector extraction region Y to form a collector extraction layer 3. The n-type silicon layer 1 in the base region X becomes a collector layer.

Next, a polycrystalline silicon film 4 containing boron and a SiO ₂ film 5 are entirely laminated by a CVD method, and then these are patterned by a photolithography method to form an opening 6 at the center of the base region X. Is formed in the region from the base region X to the selective oxide film 2, and the collector electrode 8 is formed on the collector extraction layer 3.

After that, the silicon layer 1 is passed through the opening 6.
Ion implantation of boron into the inner base region of. Following this, annealing is performed to activate the implanted boron and p
To form the inner base layer 9 of the mold, the boron in the base lead-out electrode 7 by solid phase diffusion in the silicon layer 1 to form the external base layer 10 of p ⁺ -type.

Thereafter, as shown in FIG. 1B, the polycrystalline silicon film 4 forming the base electrode 7 and the collector electrode 8 is formed.
Oxidizing the side surfaces and the upper surface of the internal base layer 9 heat, there SiO ₂
The film 12 is grown.

Next, the polycrystalline silicon 13 containing arsenic is converted into C
After stacking by the VD method, as shown in FIG. 1 (c), the polycrystalline silicon 13 is anisotropically etched in the vertical direction so as to be left only on the side portions of the base extraction electrode 7 and the collector electrode 8 and the side wall. To form. At the same time, the second opening 14 surrounded by the polycrystalline silicon 13 is formed on the internal base layer 9.

The steps up to this point are the same as those of the bipolar transistor formed in the internal circuit of the semiconductor device. The manufacturing process of the bipolar transistor formed in the internal circuit is the same as the conventional process shown in FIG.

Following this, Si on the base extraction electrode 7
The O ₂ film 5 is patterned to form a contact hole 15. Further, as shown in FIG. 2 (d), a photoresist 16 is applied, and this is exposed and developed to form a window 17 for exposing the polycrystalline silicon 13 of the sidewall, and then the polycrystalline silicon is passed through this window 17. 13 and below
The SiO ₂ film 12 is removed by dry etching.

Next, as shown in FIG. 2 (e), after the polycrystalline silicon film 18 containing phosphorus is formed on the entire surface, the SiO ₂ film 5 on the base extraction electrode 7 and the SiO remaining on the side portion thereof. ₂ membranes 12
Is used as a mask to solid-phase diffuse the phosphorus to form an n ⁺ -type emitter layer 19 on the upper portion of the internal base layer 9.

After this, an aluminum film 20 is deposited,
This and the polycrystalline silicon film 18 are successively patterned to form an emitter electrode 21 that short-circuits the emitter layer 19 and the base extraction electrode 7. At the same time, the collector electrode 22 is formed on the collector extraction layer 3.

Reference numeral 23 indicates an n ⁺ type buried layer formed under the n type silicon layer 1. The bipolar transistor formed by the above process,
The emitter electrode 21 and the base extraction electrode 7 are short-circuited to be used as an emitter / base short-circuit type protection element.

According to such a protection device, the emitter layer 19 has a width almost equal to that of the internal base layer 9, and the area S _{2 of the} emitter layer is equal to the emitter layer of the bipolar transistor of the internal circuit shown in FIG. The area is larger than the area S _{1 of} 45, and the breakdown voltage increases, and the emitter layer 19 and the internal base layer 9
The electrostatic stress applied to the interface with and becomes smaller, making crack fracture less likely to occur.

As a result, the self-aligned bipolar transistor can be used as a protection element.

[0030]

As described above, according to the present invention, when the emitter layer and the base layer of a self-aligned bipolar transistor are short-circuited and used as a protection element, the area of the emitter layer is determined by the self-alignment of the internal circuit. Since it is made wider than the emitter layer of the bipolar transistor, the electrostatic stress applied to the interface between the emitter layer and the internal base layer of the protective element is reduced, cracking is less likely to occur, and the protective element can be applied.

[Brief description of drawings]

FIG. 1 is a cross-sectional view (1) showing a manufacturing process of a device according to an embodiment of the present invention.

FIG. 2 is a sectional view (No. 2) showing the manufacturing process of the device according to the embodiment of the present invention.

FIG. 3 is a block diagram showing a connection state of a protection element in a semiconductor device and an equivalent circuit diagram of the protection element.

FIG. 4 is a cross-sectional view showing an example of a manufacturing process of a bipolar transistor.

[Explanation of symbols]

1 Silicon Layer (Collector Layer) 2 Selective Oxide Film 3 Collector Extraction Layer 5 SiO ₂ Film 7 Base Extraction Electrode 8 Collector Electrode 9 Internal Base Layer 10 External Base Layer 12 SiO ₂ Film 18 Polycrystalline Silicon Film 19 Emitter Layer 20 Aluminum Film 21 Emitter electrode 22 Collector electrode 41 Base extraction electrode 42 Emitter electrode 43 Silicon layer (collector layer) 44 External base layer 45 Emitter layer 46 Sidewall

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 23/522 23/556 23/60 23/62

Claims (1)

[Claims] 1. A first inner base layer (51) surrounded by a first outer base layer (44) and the first inner base layer (5).
1) a first emitter layer (45) formed on the upper layer portion,
A bipolar transistor composed of the first external base layer (44) and the first collector layer (43) formed under the first internal base layer (51) is formed in an internal circuit, A second inner base layer (9) surrounded by a second outer base layer (10), and the first inner emitter layer (45) formed on the upper layer of the second inner base layer (9). ), And a second collector layer (1) formed under the second outer base layer (10) and the second inner base layer (9). ) And a base extraction electrode (7) formed on the second external base layer (10).
A semiconductor device having an emitter-base short-circuit type protection element composed of an emitter electrode (21) connected to the second emitter layer (19) and the base extraction electrode (7). .