JPH06214620A - Input/output data switching system - Google Patents

Abstract

(57) [Summary] (Correction) [Purpose] To realize an input / output data exchange method in which the OS can effectively use resources and can input / output data without being restricted by the maximum number of data to be transmitted. [Structure] The OS 105 outputs the output data to the I / O memory 10
2 to the I / O image area 103-C. If the flag 106 is off, the transmission buffer 103-S is not updated, and if it is on, it is updated. The transfer pointer 107 is the start address of the reception buffer to be read this time, the write pointer 1
Reference numeral 08 stores the start address of the receive buffer to be written this time, and edit pointer 109 stores the start address of the receive buffer for editing data in the event of an abnormality. The data exchange table 110 stores the relative address for data corresponding to the I / O device number. Input / output data is input / output at an address obtained by adding a relative address to the selected start address. If all the transmission result parts at this time are normal, the start addresses of the transfer pointer 107 and the write pointer 108 are exchanged.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable controller constructed by connecting a central control unit and an I / O unit via a serial transmission bus, and has a capacity exceeding the maximum number of data that a serial transmission interface circuit can send at one time. And an input / output data exchange method between the central control unit and the I / O device having the above.

[0002]

2. Description of the Related Art Generally, a programmable controller (hereinafter referred to as a PC) has a configuration as shown in FIG.
A central control unit 501 that performs calculation and control, and an I / O unit 5 that inputs and outputs input / output data to and from a plurality of controlled devices based on the calculation result and control of the central control unit 501.
It is divided into 20. The I / O unit 520 and the central control unit 501 are connected via a serial transmission bus 510.

The central control unit 501 includes an arithmetic unit 504 operated by a user program, and the arithmetic unit 504 and I.
I / O for storing data input / output between the I / O units 520
A memory 502, an I / O buffer 503 that temporarily stores data input and output by the I / O memory 502, and a connection of the I / O buffer 503 to the I / O unit 520 via the serial transmission bus 510. It comprises a serial transmission interface circuit 540.

The I / O unit 520 inputs / outputs data to / from a plurality of controlled devices, I / O devices (interfaces) 520-1, 520-2, ... 520.
-N. Those I / O devices 520-i (i =
1, 2, ... N, and so on) are station number setting devices 53, respectively.
0-i, and these I / O numbers for the station number setting unit 530-i
The device number given to the O device is set. Furthermore, I
The I / O devices 520-i each include a serial transmission interface circuit 540-i.

The serial transmission bus interface 540 of the central control unit 501 and the serial transmission bus interfaces 540-1, 540-2, ... 54 of the I / O unit 520
0-n are connected via a serial transmission bus 510.

The central control unit 501 includes a serial transmission bus 510 and a serial transmission interface circuit 54.
Data input from each I / O device 520-i of the I / O unit 520 via the I / O buffer 503 and the I / O buffer 503.
It is input to the arithmetic unit 504 via the O memory 502, arithmetic is performed using the input data, and the arithmetic result is calculated by the I / O memory 502, the I / O buffer 503, the serial transmission interface circuit 540, and the serial transmission bus 510.
By outputting to the I / O device 520-i of the I / O unit 520 via the I / O unit 520, the controlled device connected to the I / O device 520-i is controlled.

By the way, various I / O devices 520-i are prepared so that they can be used for various controlled devices.
The input / output data capacity of the I / O device 520-i is determined in advance. Therefore, the central control unit 5
01 inquires the input / output data capacity of the I / O device 520-i to know the input / output data capacity of the I / O device 520-i. It is designed to perform fixed length input / output data transmission.

FIG. 6 is a schematic diagram showing the concept of input / output data of the I / O buffer 503 and transmission data on the serial transmission bus 510. In the example shown in the figure, the station number setting device 5
The device number “X” is set in 30-1, the device number “Y” is set in the station number setting device 530-2, and the device number “Z” is set in the station number setting device 530-n.

Further, the I / O buffer 503 mediates between the I / O memory 502, the transmission buffer 503-S and the reception buffer 503-R, and an I / O image area 503-.
C, a transmission buffer 503-S for sending output data to the I / O device 520-i, and an I / O device 520-i
Receive buffer 5 that stores the input data sent from
It is composed of three parts 03-R.

The above-mentioned transmission buffer 503-S is provided for each I / O.
The O-device 520-i has areas corresponding to the respective areas, and each of these areas includes a command section, a transmission data number section,
It is composed of a device number part and an output data part. In the device number portion of each area, device numbers “X”, “Y” ... “Z” are stored corresponding to the I / O devices 520-i.

On the other hand, the reception buffer 503-R also receives each I / O.
The O-device 520-i has areas corresponding to the respective areas, and each of these areas includes a transmission result portion, a received data number portion,
It is composed of a device number part and an input data part. The I / O device 520-i is also included in the device number part of the device number part of each of these areas.
Corresponding to the device numbers "X", "Y" ...
“Z” is stored.

When the operating system (hereinafter referred to as OS) 505 of the central controller 501 issues a transmission command to the serial transmission interface circuit 540, the serial transmission interface circuit 540 causes the transmission buffer 503-.
When the command part of S is "execution", serial transmission is executed, transmission is continuously performed until the command part of the transmission buffer 503-S becomes "stop", and the above "stop" is fetched. Is notified to the end of transmission.

To further explain, if the command portion of the head address of the transmission buffer 503-S is "execute", the serial transmission interface circuit 540 will generate the number of transmission data portions indicated by the next address, and The transmission data (device number and output data) stored from the address is sent to the serial transmission bus 510 as a set of transmission data (hereinafter referred to as a transmission frame).

That is, first, the first transmission data (device number "X" and output data) of the transmission buffer 503-S is transmitted to the I / O device 520-1 as the transmission frame 601-1. The I / O device 520-1 has a transmission frame 601.
When -1 is received, the transmission frame 6 of the transmission data (device number "X" and input data) to the central control unit 501 is immediately transmitted.
11-1 is transmitted. This transmission data exchange system is generally known as a polling and safety system.

Serial transmission interface circuit 540
Is the transmission frame 61 transmitted by the I / O device 520-1.
When 1-1 is received, the received data is written in the corresponding area of the receive buffer 503-R, and the number of received data and the transmission result are stored in a predetermined place.

Next, the serial transmission interface circuit 5
40 fetches the next command part of the transmission buffer 503-S, and based on this, the transmission frame 601-2
(Device number “Y” and output data) to I / O device 520-
2 and the I / O device 520-2 immediately transmits the transmission frame 61 of the transmission data (device number “Y” and input data).
1-2, and the serial transmission interface circuit 54
When receiving the transmission frame 611-2, 0 stores the reception data, the number of reception data, and the transmission result in the corresponding predetermined area of the reception buffer 503-R.

These processes are sequentially performed by the I / O device 520-
It is similarly executed up to n. In this way, the transmission is repeated until the command section becomes "stop". The OS 505 does not participate in the serial transmission information processing device at all after the transmission command is given to the serial transmission interface circuit 540 until the end of the transmission is notified. Further, the maximum number of data that can be transmitted at one time is predetermined for the serial transmission interface circuits 540 and 540-i.

The timing at which the OS 505 issues a transmission command to the serial transmission interface circuit 540 and the operation unit 5
The timing at which 04 performs the calculation is asynchronous. Therefore, the input timing of the input data used by the arithmetic unit 504 during the arithmetic operation and the output timing of transmitting the output data of the arithmetic result to the I / O device 520-i are both synchronized with the serial transmission interface circuit 540. Is required.

Therefore, the OS 505 synchronizes with the arithmetic operation of the arithmetic unit 504 and the serial transmission interface circuit 54.
Immediately before sending the output data transmission command to 0, the output data is sent from the I / O image area 503-C to the transmission buffer 5
03-S, and at the end of transmission, the input data of the reception buffer 503-R is transferred to the I / O image area 503.
-Transfer to C.

The I / O image area 503-C is also provided.
The input / output data of is exchanged with the I / O memory 502.
The OS 505 transfers the data in the transmission buffer 503-S and the reception buffer 503-R to the I / O image area 503-.
When transferring between C, I / O memory 502 and I / O memory 502
Data exchange of the O image area 503-C is not performed. In this way, the synchronization of the input / output data is guaranteed.

Further, conventionally, in such an input / output data exchange system, the serial transmission interface circuit 5 is used.
The maximum number of data that 40 and 540-i can send at one time was predetermined.

[0022]

However, in the above-mentioned conventional input / output data exchange system, P of the arithmetic unit 504 is used.
Even if the calculation cycle by the user program in C, that is, the cycle in which the OS 505 exchanges input / output data between the I / O memory 502 and the I / O image area 503-C is longer than the cycle of serial transmission, the OS 50
5 is an I / O image area 503-at each start of serial transmission.
The output data of C is transferred to the transmission buffer 503-S, and the input data is transferred from the reception buffer 503-R to the I / O image area 503-C each time the transmission is completed, which is a wasteful data transfer process. Therefore, there is a problem that it becomes an overhead of the OS 505.

Further, the serial transmission interface circuit 5
Since the maximum number of data that can be transmitted by 40 and 540-i at a time is determined, it is impossible to design an I / O device having an input / output data capacity exceeding this maximum number of data.
There was also a problem that the scale of the design system was restricted.

An object of the present invention is to realize an input / output data exchange system in which an OS can effectively use resources and can input / output data without being restricted by a predetermined maximum transmission data number.

[0025]

SUMMARY OF THE INVENTION According to the present invention, there is provided a programmable controller including a central control unit for calculating input / output data and a plurality of I / O units each having a device number connected by a serial transmission bus. The output data exchange method is assumed.

The input / output data exchange system according to the present invention includes an I / O memory for storing input / output data to be operated, and this I / O memory.
A serial transmission interface circuit that mediates the transmission of input / output data between the O memory and the plurality of I / O units via a serial transmission bus, and a serial transmission interface circuit connected between the serial transmission interface circuit and the I / O memory. Stores the overall transmission result indicating whether the transmission / reception results of the input / output data between the I / O memory and the plurality of I / O units via the I / O unit are normal and the input data from the plurality of I / O units The input data from the plurality of I / O units and the first pointer that indicates the start address of the reception buffer in which the input data from the plurality of I / O units are read by the I / O memory. When the second pointer indicating the start address of the reception buffer written by the serial transmission interface circuit and the general transmission result are abnormal A third pointer indicating the start address of the receiving buffer for editing the input data of the number I / O units, the relative address of the receiving buffer corresponding to the plurality of I / O units, the relative address of the I / O memory, and the input / output. The I / O data exchange table for storing the data capacity, the transmission buffer connected to the serial transmission interface circuit and outputting the output data of the I / O memory to the serial transmission interface circuit, and the output data to be output by the transmission buffer are shown. An output image area for temporary storage and a flag area indicating whether or not the output data stored in the output image area is output to the transmission buffer are provided.

[0027]

According to the input / output data exchange method of the present invention, the serial transmission interface circuit transfers the input / output data between the I / O memory for storing the calculated input / output data and the plurality of I / O units by the serial transmission bus. Mediate through.
The three reception buffers include a general transmission result indicating whether or not the transmission results of the input / output data are all normal and a plurality of I's.
Stores input data from the / O section.

The first pointer indicates the start address of the reception buffer from which the input data is read, the second pointer indicates the start address of the reception buffer to which the input data is written, and the third pointer indicates the above summary. When the transmission result is abnormal, the head address of the reception buffer for editing the input data of the plurality of I / O units is shown.

The I / O data exchange table includes a plurality of I / O data.
Relative address and I / O of receive buffer corresponding to section O
It stores the relative address of the memory and the input / output data capacity. The transmission buffer outputs the output data of the I / O memory to the serial transmission interface circuit, the output image area temporarily stores the output data to be output by the transmission buffer, and the flag area stores it in the output image area. It indicates whether the output data that has been output is output to the transmission buffer.

The above-mentioned input / output data exchange method is, for example, for transmission / reception data of input / output data of a plurality of I / O units having a capacity exceeding the maximum number of data that can be transmitted at one time by the serial transmission interface circuit. Is provided with a relative address table of three reception buffers that assigns a sequential number indicating the transmission order of the data and a page number indicating the division order of the transmission data, and stores the data of the sequential number and the page number. In turn, transmission of output data from the transmission buffer mediated by the serial transmission interface circuit and a plurality of I's.
The input data from the / O section is transmitted alternately.

[0031]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the overall configuration of a central control unit according to an embodiment of the present invention. In the figure, the central control unit, via a serial transmission interface circuit 140 and a serial transmission bus 110 (not shown),
This is also connected to an I / O unit 120 that inputs / outputs input / output data to / from a plurality of controlled devices (not shown).

The I / O unit 120, like the conventional I / O unit (see FIG. 5), inputs / outputs I / O data to / from a plurality of controlled devices. = 1, 2
... n, and so on), and these I / O devices 12
0-i includes a station number setter 130-i and a serial transmission interface circuit 140-i, respectively, and the station number setter 130-i is set with a device number assigned to each I / O device 120-i. It

In the central control unit shown in FIG. 1, first, an arithmetic unit 104 operated by a user program and its arithmetic unit 10 are operated.
4 and the I / O unit 120, the I / O memory 102 for storing the data input / output, and the I / O image area 1 for temporarily storing the transmission data stored in the I / O memory 102.
03-C, a transmission buffer 103-S for outputting the transmission data of the I / O image area 103-C to the serial transmission interface circuit 140, and output data between the I / O memory 102 and the I / O image area 103-C. The flag area 106 for storing the transfer condition of

Next, the central control unit controls the plurality of I / O devices 12 via the serial transmission interface circuit 140.
Three receive buffers 103-R-X, 103-R-Y and 103-R for storing received data input from 0-i
-Z, receive buffer 103-R for transferring input data received from I / O device 120-i to I / O memory 102
-X (103-R-X, 103-R-Y or 103-R
-Z) transfer pointer area 10 for storing the start address
7, a write pointer area 108 for storing the start address of the reception buffer 103-R in which the data received from the I / O device 120-i is written, and a reception buffer 103-R for editing the input data when the reception data is abnormal An edit pointer area 109 for storing the start address of

Further, the central control unit further comprises an I / O device 1
The reception buffers 103-R-X and 103-R corresponding to the transmission order (device number) of the transmission / reception data of 20-i, respectively
I / O data exchange table 1 for storing the relative addresses of -Y and 103-R-Z, the relative address of I / O memory 102, and the input / output data capacity of each I / O device 120-i.
Equipped with 10.

Then, the arithmetic unit 104 of the central control unit
A calculation is performed using the input data input to the I / O memory 102, and the calculation result is used as the I / O memory 102 and I / O memory.
By outputting to the I / O device 120-i of the I / O unit 120 via the image area 103-C, the transmission buffer 103-S, the serial transmission interface circuit 140, and the serial transmission bus 110, those I / O devices 120-i are output. The controlled device connected to the O device 120-i is controlled.

Next, FIG. 2 shows the transmission buffer 103-
The structure of the output data of S and the structure of the input data of the receiving buffer 103-R are shown. As shown in the figure, the transmission buffer 103-S and the reception buffer 103-R have I / O devices 120- in order of device numbers "j", "k", and "m".
Input / output data of i is stored.

In this example, the I / O device 1 with the device number "k"
The data capacity of 20-i exceeds the maximum number of data that the serial transmission interface circuit 140 can send at one time. In this example, the maximum number of data that the serial transmission interface circuit 140 can send at one time is 255 bytes. Then, the I / O device 120 of the device number “k”
The data capacity of -i is such that the output data amount is 500 bytes and the input data amount is 400 bytes. Further, the division standard of the output data and the input data in this case is 220 bytes.

Also, I of other device numbers "j" and "m"
The data capacity of the / O device 120-i and the like is smaller than the maximum data number of 255 bytes that the serial transmission interface circuit 140 can send at one time. Therefore, the structure of the input / output data in the transmission / reception buffer corresponding to these I / O devices 120-i is the same as the structure of the input / output data in the normal transmission / reception buffer shown in FIG.

The structure of input / output data corresponding to the device number "k" in the transmission buffer 103-S and the reception buffer 103-R will be described below. As shown in FIG. 2, the transmission buffer 103 created by the OS 105
Output data S1, S2 to device number "k" in -S
And S3 are configured by inserting a sequential number part and a page number part between the device number part and the output data part.
In the sequential number portion, a value indicating the transmission order, that is, a value incremented by "1" for each transmission command to the serial transmission interface circuit 140 by the OS 105 is written. The page number and the total number of pages are written in the page number section.

FIG. 3 shows the structure of the page number section.
As shown in the figure, the page number part 30 has 1 byte (8
The upper digit 4 bits represent the page number, and the lower digit 4 bits represent the total number of pages.

For the total number of pages, the quotient obtained by dividing the number of bytes of the output data or the input data, whichever has the larger capacity, by 220 bytes, or if there is a remainder, add "1" to the quotient and write it. Be done. In this example, since the output data (500 bytes) is larger than the input data (400 bytes), the number of output data bytes divided by 220 bytes,
That is, since there is a remainder in the quotient “2” of 500 bytes ÷ 220 bytes, “3” obtained by adding “1” is written as the total number of pages. Page numbers include fractions 2
Delimiter ranks "1", "2", and "3" for each 20 bytes are written. In the page number portion shown in FIG. 2, the page number and the total number of pages are represented by "1/3", "2/3", and "3/3".

Then, as shown in the figure, the input data R from the device number "k" in the reception buffer 103-R.
Similarly, 1, R2 and R3 are also configured by inserting a sequential number part and a page number part between the device number part and the output data part. In this example, since the input data is 400 bytes, the input data ends at the second page,
There is no input data part in the structure of the input data of the last page “3/3” page.

Next, the control operation by the central control unit having the above configuration will be described again with reference to FIG. In the figure, the OS
Reference numeral 105 denotes an I / O in synchronization with a calculation cycle of the calculation unit 104.
Output data to be sent to the device 120-i is I / O memory 1
02 to the I / O image area 103-C. At this time, the OS 105 uses the I / O data exchange table 11
The output data relative address stored in 0 is read, and the read relative address is read out from the I / O memory 10
I / O memory 10
The address of the output data of 2 is calculated.

Further, the OS 105 sends a command to the serial transmission interface circuit 140 at regular intervals. Immediately before executing this transmission command, the OS 105
Starts preparation for creating output data to be output to the transmission buffer 103-S.

At this time, I / O from the I / O memory 102 is changed.
When the flag area 106 indicating that the output data has been transferred to the image area 103-C is off (“0”), the transmission buffer 103-S is not updated,
It transmits a command to the serial transmission interface circuit 140. Therefore, the serial transmission interface circuit 14
0 sends the contents of the transmission buffer 103-S already created in the previous cycle to the I / O device 120-i of the I / O unit 120 via the serial transmission bus 110.

On the other hand, when the flag area 106 is on ("1"), the data of the I / O image area 103-C is transferred to the output data area of the transmission buffer 103-S, It transmits a command to the serial transmission interface circuit 140. Therefore, in this case, the serial transmission interface circuit 140 sends out the updated new output data of the transmission buffer 103-S.

On the one hand, the OS 105 sends out the above-mentioned output data, and on the other hand, the OS 105 transmits the output data in the previous processing cycle (hereinafter, simply referred to as the previous cycle) and has already received the reception buffer. The input data stored in 103-R-X is transferred to the I / O memory 102.

At this time, the OS 105 stores the start address (eg, “X”) of the reception buffer stored in the transfer pointer area 107 and the I / O data exchange table 110.
Each of the input data relative addresses (for example, “i”) stored in is read, and the relative address “i” is added to the read start address “X” to obtain I /
The address "X + i" of the reception buffer 103-R-X storing the input data to be transferred to the O memory 102 is calculated.

The OS 105 also executes I / O at this cycle.
The input data transmitted from the device 120-i is stored in the reception buffer 103-RY. At this time, OS1
05 reads the start address (for example, “Y”) of the reception buffer stored in the write pointer area 108 and the input data relative address “i” stored in the I / O data exchange table 110. , The relative address “i” is added to the read head address “Y”, and the input buffer is to receive the input buffer 103.
The address "Y + i" of -RY is calculated.

Thus, on the one hand, the input data of the previous cycle is stored in the I / O memory 102, and on the other hand, the output data of the current cycle is sent out and the input data of the current cycle is received.

When the transmission completion is notified from the serial transmission interface circuit 140, the OS 105 checks the transmission state of this cycle. Then, if the integrated transmission result portion in the reception buffer 103-R shown in FIG. 2 is normal, the input data of the device number "k" having a larger data capacity is checked. This check processing is based on the device number “k” of the device number part in the reception buffer 103-R and the output data of the device number “k” by the relative address of the sequential number part in the I / O data exchange table 110. Corresponding input data, receiving buffer 103-
R input data pages R1, R2, and R3 sequential number output data pages S1 and S2 at the time of transmission
And S3 are the same as the sequential numbers, and whether the page number portion of each page S1, S2 and S3 is written in the page order.

If there is no abnormality in the check result, the contents stored in the transfer pointer area 107 and the contents stored in the write pointer area 108 are exchanged.
That is, as a result, the start address “Y” is stored in the transfer pointer area 107, and the start address “X” is stored in the write pointer area 108.

Therefore, in the next cycle, the reception buffer 103-RY becomes the reception buffer for transfer by being designated by the start address "Y" of the transfer pointer area 107, and the reception buffer 103-RY
The latest input data written in this cycle is I /
It is transferred to the O memory 102. As a result, the latest input data can be obtained in the I / O memory 102.

On the other hand, in the reception buffer 103-R-X,
The transfer of the input data is completed in the current cycle, and the reception buffer 103-R-X is designated by the start address “X” of the write pointer area 107 in the next cycle, so that the reception buffer for writing in the next cycle. Then, new input data input from the I / O device 120-i is written in the reception buffer 103-R-X.

As described above, with respect to the input data, the I / O can be performed by simply exchanging the start address stored in the transfer pointer area 107 and the start address stored in the write pointer area 108 for each processing cycle. Memory 102
Without passing through the I / O image area 103-C,
Input data can be read directly from the receive buffer.

Reception buffer 103 in the above processing
The configuration of the input data of -R is a configuration example when each I / O device 120-i normally responds to the transmission from the transmission buffer 103-S.

Next, FIG. 4 shows an example of input data when the transmission result is abnormal. In the example of the figure, in the current cycle, the input data of the device number “j” received in the reception buffer 103-R-X is abnormal, and the page number part of the input data of the device number “k” is originally "1 /
Where input data that is "3", "2/3" and "3/3" should be received, "1/3", "1/3" and "3 /"
3 ”is received.

The reception buffer 103-R-X has been a reception buffer for writing in this cycle, and "X" is currently stored in the write pointer area 108. Therefore, “Y” is stored in the transfer pointer area 107. That is, the reception buffer 103
-RY is designated by "Y" in the transfer pointer area 107 in this cycle, and serves as a reception buffer for transfer. That is, the reception buffer 10
In 3-RY, since the input data written in the previous cycle was all normal as determined by the check, the start address of the pointer was exchanged and the write buffer in the previous cycle transferred this cycle. It is a receive buffer for

Next, the processing when there is an abnormality in the input data will be described. First, regarding the input data having the abnormal device numbers “j” and “k” shown in the figure, the reception buffer for transfer 103-of the current cycle designated by the start address “Y” of the transfer pointer area 107
The data of the input data portion of RY, that is, the normal input data of the previous cycle, is set to the edit receiving buffer 103-R (103 in this example) designated by the start address (for example, “Z”) of the edit pointer area 109. -R-Z) based on the relative address in the I / O data exchange table 110.

Next, for the input data of the device number "m" which has been normally transmitted, the write pointer area 10
7, the data of the input data portion of the write reception buffer 103-R-X for the current cycle designated by the start address “X” of 7;
That is, the normal input data of the current cycle is transferred to the edit receive buffer 103-R-Z, which is also designated by the start address “Z” of the edit pointer area 109, and to the relative address in the I / O data exchange table 110. Copy based.

As a result, the edit receiving buffer 103-
Regarding the input data of the device numbers “j” and “k”, which have been transmitted abnormally, the latest input data immediately before the abnormality is written in the RZ, and the device number “m” which was transmitted normally. For the input data of, the latest input data is written.

Thereafter, the start address "Y" of the transfer pointer area 107 and the start address "Z" of the edit pointer area 109 are exchanged, and the start address "Z" is set in the transfer pointer area 107. For the input data of the device numbers “j” and “k”, the latest input data immediately before the abnormality occurs, and for the input data of the device number “m” that was normally transmitted, the latest input data is the arithmetic unit 104. Can be obtained.

[0064]

As described in detail above, according to the present invention,
It is possible to divide and transmit the data of the I / O device whose input / output capacity exceeds the maximum data number range that can be sent at one time of the serial transmission interface circuit. Only by checking the page number and sequential number, the divided input data can be divided. Since the simultaneity of the output data and the output data is surely guaranteed, various I / O devices ranging from small capacity to large capacity corresponding to the controlled device can be used within the range of the I / O memory capacity of the central control unit. It can be easily incorporated into the design without any restrictions, and thus the operational efficiency of the PC is improved.

In addition, input data from the reception buffer is I / O
Since it is not necessary to transfer to the O image area and only the output data needs to be temporarily transferred to the I / O image area, the overhead of the central control unit can be greatly reduced, and therefore, other OS processing, for example, central control can be performed. The man-machine interface such as reading out the sequence program in the department can be performed at high speed, and the operation efficiency of the PC is further improved.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating an input / output data exchange system of the present invention.

FIG. 2 is a diagram showing a structure of input / output data in the input / output data exchange system of the present invention.

FIG. 3 is a diagram showing a configuration of a page number section provided for transmission data that exceeds the maximum number of data that can be transmitted at one time.

FIG. 4 is a diagram illustrating a process when the received data is abnormal according to the present invention.

FIG. 5 is a diagram showing a configuration of a conventional programmable controller.

FIG. 6 is a diagram illustrating a conventional input / output data exchange method of a programmable controller.

[Explanation of symbols]

104 arithmetic unit 102 I / O memory 103-C I / O image memory 103-S transmission buffer 103-R-X, 103-RY, 103-RZ reception buffer 105 OS 106 flag area 107 transfer pointer area 108 Write pointer area 109 Edit pointer area 110 I / O data conversion table 30 Page number section S1, S2, S3 Page of divided output data R1, R2, R3 Page of divided input data

Claims (2)

[Claims] 1. An input / output data exchange system of a programmable controller configured by connecting a central control unit for calculating input / output data and a plurality of I / O units each having a device number by a serial transmission bus. An I / O memory for storing the input / output data, and a serial transmission interface circuit that mediates the transmission of the input / output data between the I / O memory and the plurality of I / O units via the serial transmission bus, The result of transmission of input / output data connected between the serial transmission interface circuit and the I / O memory and between the I / O memory and the plurality of I / O units via the serial transmission interface circuit is all normal. And three reception buffers storing the overall transmission result indicating whether or not the input data from the plurality of I / O units, A first pointer indicating the start address of the reception buffer for reading the input data from the plurality of I / O units by the I / O memory, and the input data from the plurality of I / O units by the serial transmission interface. A second pointer indicating the start address of the reception buffer written by a circuit, and the plurality of I / Os when the general transmission result is abnormal.
A third pointer indicating the start address of the reception buffer for editing the input data of the copy, the relative address of the reception buffer and the relative address of the I / O memory, and the input / output data corresponding to the plurality of I / O parts An I / O data exchange table for storing the capacity, a transmission buffer connected to the serial transmission interface circuit and outputting the output data of the I / O memory to the serial transmission interface circuit, and the data should be output by the transmission buffer. Input / output data, comprising: an output image area for temporarily storing output data; and a flag area indicating whether or not the output data stored in the output image area is output to the transmission buffer. Exchange method. 2. A sequential number indicating the transmission order of transmission data and transmission for input / output data of the plurality of I / O units having a capacity exceeding the maximum number of data that can be transmitted at one time by the serial transmission interface circuit. The relative address table of the three receiving buffers, which gives the data of the page number indicating the division order of the data and stores the data of the sequential number and the page number, is provided by the serial transmission interface circuit in the order of the pages. 2. The input / output data exchange system according to claim 1, wherein the transmission of output data from the transmission buffer and the transmission of input data from the plurality of I / O units are alternately performed via the mediation.