JPH0621504A - Junction field-effect photoelectric conversion element and driving method therefor - Google Patents

Abstract

PURPOSE:To provide a junction field-effect photoelectric conversion element capable of simultaneously realizing accumulation mode actuation, non-breakdown mode actuation and high amplification factor. CONSTITUTION:An insular P-type rear surface gate 202 is formed in an N<+>-type substrate 201 to be a drain and then an N<+> source 203 reaching the substrate surface is provided in the central part of the gate 202. An N-type channel 204 is formed on a surface gate around the source 203; a P-type surface gate 205 is formed on the channel 204; an N<+>-type pin gate 206 connecting to the source 203 is provided on the substrate surface; next, the side surfaces of the pin gate 206 and the surface gate 205 are separated from the substrate 201 by insulating films 207. As for the actuations, the rear surface gate 202 is firstly impressed with high negative voltage so as to deplete the surface gate 205 successively impressed with lower negative voltage for a specific time so as to accumulate the holes generated by incident light in the surface gate 205. Next, the rear surface gate 202 is impressed with a lower negative potential so that the signal current proportional to the charge accumulated in the bias current and the surface gate 205 may be fed to the parts between the source 203 and the drain 201.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a junction field effect photoelectric conversion element and a driving method thereof.

[0002]

2. Description of the Related Art A phototransistor is known as an amplification type photoelectric conversion element. FIG. 2 is a configuration diagram of a phototransistor. The phototransistor is an N ⁺ (or P ⁺ ) emitter, P
A type (or N type) base and an N type (or P type) collector. 0 voltage is applied to the emitter and + (or-) voltage is applied to the connector, and the base operates in a floating state. An electron-hole pair is generated when light enters the base, which will be described below for the N ⁺ -P-N phototransistor. Electrons are emitters
Or, it is absorbed by the collector and the holes enter the base. At this time, the potential of the base rises, and a current flows from the collector to the source in proportion to the light incident intensity.

As can be seen from this description, the holes entering the base of the phototransistor are lost when a current is passed between the collector and the source, and so-called nondestructive reading cannot be performed. In addition, since holes cannot be stored in the base, it cannot be operated in a so-called storage mode.

[0004]

As described above, the drawback of the phototransistor is that it cannot perform nondestructive reading or operation in the accumulation mode.

An object of the present invention is to provide a junction field effect photoelectric conversion element capable of non-destructive reading and operation in a storage mode and a driving method thereof.

[0006]

A junction field effect type photoelectric conversion element according to the present invention is provided with an island-shaped second conductivity type region (back surface gate) inside a first conductivity type high concentration semiconductor substrate, and the second conductivity type A first-conductivity-type high-concentration region is provided substantially in the center of the upper surface of the type region, a first-conductivity-type region is provided at the peripheral edge of the high-concentration region, and a second-conductivity-type region ( A front surface gate), a first conductivity type high-concentration region connected to the first conductivity type high-concentration region is provided on the upper surface of the front surface gate, and insulation is provided between the first conductivity type high-concentration region and the substrate. It is provided with a film.

Further, the driving method of the junction field effect photoelectric conversion element according to the present invention is such that the back gate is negative when it is p-type,
In the case of the n-type, a large positive voltage is applied to deplete the front gate, and then the absolute value is smaller than this and the same polarity voltage is applied for a certain period to accumulate carriers generated by light in the surface gate. The back gate is made to have the same polarity as the above-mentioned large potential and a small absolute value, and a bias current and a signal current proportional to the charges accumulated in the front gate are made to flow between the source and the drain.

[0008]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1A is a plan view showing the structure of a junction field effect type (hereinafter referred to as JFET type) photoelectric conversion element according to the present invention, and FIGS. 1B and 1C are each a view of FIG. A-
It is an A'line sectional view and a BB 'line sectional view.

First, the structure of the JFET type photoelectric conversion element will be described. An island-shaped P-type region 202 is formed inside the N ⁺ -type silicon substrate 201. The N ⁺ type silicon substrate 201 acts as the drain of this device. In addition, P
The mold region 202 functions as one gate of this device, and is a regular hexagon in plan view. Hereinafter, this region 202 will be referred to as a back gate.

At the center of the upper surface of the backside gate 202, an N ⁺ region 203 serving as the source of this element is provided in contact with the backside gate 202, and an N region 204 serving as a channel is in contact with the backside gate 202 at the periphery thereof. Is formed. A P-type layer 205 is provided in contact with the upper surface of the N region 204. N region 204 and P-type layer 205 as seen in a plane
The outer edge of is similar to that of the back gate 202. This P-type layer 205 acts as the other gate of this device. This area will be called the surface gate from now on. An N ⁺ region 206 connected to the source 203 is provided in contact with the upper surface of the surface gate 205. In this region, the electric potential on the surface side of the surface gate 205 is fixed (PINed) near the source electric potential.
We call it pin gate from now on. A narrow and deep insulating film layer 207 is provided on the drain side of the pin gate 206 and the surface gate 205. The depth of the insulating film layer 207 does not necessarily have to reach the lower end of the surface gate. The depth of the insulating film layer may be up to the lower end of the pin gate, and the portion below it may be the N ⁺ region.

An example of the size and density of each part of this device will be described. The donor concentration of the substrate 201 is 1 × 10 ¹⁷ /
cm ³ , the acceptor concentration of the back gate 202 is 1 × 10
¹⁶ / cm ³ , the source 203 and the pin gate 206 have a donor concentration of 1 × 10 ¹⁷ / cm ³ , the surface gate 205 has an acceptor concentration of 1.3 × 10 ¹⁵ / cm ³ , and the channel has a donor concentration of 5 × 10 5. ^{It is 14} / cm ³ . The back gate 202 has a thickness of about 1 μm, the channel 204 has a thickness of 3 μm, the front gate 205 has a thickness of 1 μm, and the pin gate 206 has a thickness of about 0.5 μm.
The width of 7 is about 0.1 to 1 μm.

Next, the operation of this element will be described. First, 0 volt is applied to the source 203 and the pin gate 206. Further, 0.5 V is applied to the substrate (drain) 201. Then, a large negative potential (about -5 V) is applied to the back gate 202. At this time, holes in the front surface gate 205 are absorbed by the back surface gate 202, and electrons in the channel 204 are absorbed by the substrate (drain) 201.

Next, the back gate 202 is supplied with a negative potential slightly smaller than the large negative potential. This potential will be referred to as an intermediate potential hereinafter. The intermediate potential is about -4 volts. When light is incident from the surface of this element in the state where this intermediate potential is applied, all the generated holes are stored in the surface gate 205 on the pin gate 206, the surface gate 205, and the surface gate side of the channel 204. Further, all holes generated on the back side gate side of the channel 204 and on the back side gate 202 are absorbed by the back side gate 202. In addition, all electrons generated in the pin gate, the front gate, the channel, and the back gate are absorbed by the substrate (source) and the drain. When light is incident for a certain period, the surface gate 205 is filled with holes and becomes neutral. The intermediate potential applied to the back gate 202 is a potential capable of keeping the channel region negative in this state. After performing photoelectric conversion for a certain period in this way, the voltage of the surface gate 202 is set to a small negative potential (about -2.5 V). The potential of the channel locally becomes positive regardless of whether light is incident or not, and a current flows from the drain to the source. This current is divided into a current that flows regardless of whether light is incident and a current that flows when light is incident. In the future, the former will be called the bias current, and the latter will be called the signal current.
The bias current can be set to 0 by adjusting the voltage applied to the back gate 202. Further, since the signal current is proportional to the number of holes accumulated in the surface gate 205, it is proportional to the total amount of light incident during the photoelectric conversion for the fixed period.

From the above description, the signal current flowing between the source and the drain is a current in the accumulation mode, and the holes accumulated in the surface gate are not affected by the passage of this current. It is clear that this is a breakdown mode current.

Now, let us consider the degree of amplification of signal charges by the signal current. Now, if n holes are accumulated in the surface gate and the aforementioned small negative potential is applied to the surface gate, the number of electrons generated in the channel by this is approximately n / 2.

When the channel length of this device is L, the electron mobility is μ, and the source-drain voltage is V _D , the transit time Tr is Tr = L / μE, where E = V _D / L . L = 1.5 μm μ = 600 cm
² / volt · sec, V _D = 0.5 volt
The ^{1 1 sec - Tr = 7.5 ×} 10. When the period during which the signal current is being read is T _READ , the amplification degree of the signal charge is T _READ / 2Tr. Now, assuming that T _READ is 50 μsec, the amplification degree is 3.33 × 10 ⁵ . Therefore, when n holes are accumulated in the surface gate, the number of electrons flowing between the source and the drain during the read period is (n / 2) × (T _READ / Tr) =
It becomes n × 3.33 × 10 ⁵ .

As described above, the device of the present invention can realize the storage mode, the non-destructive readout, and the large charge amplification at the same time.

[0019]

As described above, the junction field effect type having the source, the drain, the back gate, the front gate, the channel, the pin gate, and the insulating film for insulating between the pin gate and the drain and between the front gate and the drain according to the present invention. The photoelectric conversion element can realize storage mode operation, non-destructive mode operation, and high amplification degree at the same time.

[Brief description of drawings]

FIG. 1 is a plan view and a cross-sectional view showing a structure of a junction field effect photoelectric conversion element of the present invention.

FIG. 2 is a diagram showing a conventional example.

[Explanation of symbols]

201 N ⁺ Substrate 202 Back Gate 203 Source 204 Channel 205 Front Gate 206 Pin Gate 207 Insulating Film

Claims (2)

[Claims] 1. An island-shaped second conductivity type region (back surface gate) is provided inside a first conductivity type high-concentration semiconductor substrate, and the first conductivity type high-concentration region is provided substantially at the center of the upper surface of the second conductivity type region. Is provided, a first conductive region is provided at a peripheral portion of the high concentration region, a second conductive type region (surface gate) is provided on an upper surface of the first conductive type region, and the first conductive region is further provided on an upper surface of the surface gate. 1
A junction field effect photoelectric conversion element, comprising: a first conductivity type high concentration region connected to the conductivity type high concentration region; and an insulating film provided between the first conductivity type high concentration region and a substrate. 2. The back gate is negative when it is p-type, n
In the case of the mold, a large positive voltage is applied to deplete the surface gate, and then a voltage with a smaller absolute value and the same polarity is applied for a certain period of time to accumulate carriers generated by incident light in the surface gate, Next, the back gate is set to a potential having the same polarity as that of the large voltage and a small absolute value, and a bias current and a signal current proportional to the charges accumulated in the front gate are passed between the source and the drain. For driving a junction field effect type photoelectric conversion element of.