JPH06217201A - Solid state image pickup device - Google Patents

Abstract

PURPOSE:To provide the solid state image pickup device which can employ an optional signal read system and can greatly be improved in the degree of freedom of design and uses a lateral electrostatic induction transistor(TR). CONSTITUTION:On the top surface of a semiconductor layer formed on an insulator or high-resistance semiconductor substrate, a source area and a drain area are provided, and a gate area is provided between those source area and drain area to constitute the electrostatic induction TR whose source-drain current flows in parallel to the top surface of the semiconductor layer; and many solid state image pickup elements 250 equipped with electrostatic induction TRs are arrayed in matrix to constitute an array. This device is equipped with the array and scanning means 251, 252, 253, and 255 which are constituted by connecting two terminals among the gate, source, and drain terminals of the solid state image pickup elements of the array in common, line by line, and supply source-drain currents corresponding to photoelectric charges accumulated in the gate areas of the respective solid state image pickup elements to a video line 254 by controlling the potentials of respective lines by horizontal and vertical scanning circuits 257 and 256.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device using a lateral static induction transistor as a solid-state image pickup device.

[0002]

2. Description of the Related Art Conventionally, as a solid-state image pickup device used for a video camera, a facsimile or the like, there is a solid-state image pickup device using a charge transfer element such as a BBD or CCD or a MOS transistor. However, these solid-state imaging devices have various problems such as leakage of charges during signal charge transfer and low photodetection sensitivity.

As a solution to such problems at once, a static induction transistor (Static Induction Transistor) is used.
A solid-state imaging device using SIT (which is an acronym for stor) has already been proposed. The SIT is a kind of phototransistor having a photoelectric conversion function and a photocharge storage function, and has a higher input impedance, higher speed, and higher speed than a field effect transistor or a junction transistor.
It has features such as non-saturation, low noise, and low power consumption.

Therefore, if this SIT is used as a solid-state image pickup device, it is possible to obtain a solid-state image pickup device having high sensitivity, high-speed response and a wide dynamic range. Such a device is disclosed in Japanese Patent Application Laid-Open No. 55-15229. Is disclosed in.

FIG. 1 is a sectional view of an SIT which constitutes each pixel of this known solid-state image pickup device. This SIT
1 is a vertical structure, the drain region is composed of an n ^{+ -type} substrate 2, and the source region is an n ^{+ -type} region 4 formed on the surface of an n ⁻ -type epitaxial layer 3 which constitutes a channel region deposited on the substrate 2. Consists of. A p ^{+ type} signal storage gate region 5 is further formed on the surface of the epitaxial layer 3 so as to surround the source region 4, and an electrode 7 is provided on the gate region 5 with an insulating film 6 interposed therebetween. Thus, a so-called MIS structure gate electrode including an electrode / insulating film / gate region is formed. The impurity concentration of the n ⁻ -type epitaxial layer 3 forming the channel region is selected to be a low concentration such that the channel region is depleted even when the applied bias of the gate electrode 7 is 0 V and a high potential barrier is generated to cause pinch-off. There is.

The operating principle of the SIT 1 will be described below. In the state where no bias is applied between the drain and the source, light is emitted from the channel region 3 and the gate region 5.
Of the electron-hole pairs generated here, holes are accumulated in the gate region 5 and electrons flow off to the ground via the drain region 4. The holes accumulated in the gate region 5 in response to the light input raise the potential of the gate region 5 and lower the potential barrier of the channel region 3 in response to the light input. When a bias is applied between the drain and the source and a forward voltage is applied to the gate electrode 7, a current flows between the drain and the source according to the amount of holes accumulated in the gate region 5, and the output amplified for the optical input. Is obtained. The optical amplification factor S is

[Equation 1] The value is usually 10 ³ or more, which is more sensitive than the conventional bipolar transistor by one digit or more. In the above equation, 2a is the distance between the gate regions 5 and 5, l
₁ represents the depth of the gate region 5, and l ₂ represents the distance between the gate and drain regions. As is clear from the above equation, in order to obtain a higher optical amplification factor, it is necessary to reduce 2a while increasing the thickness of the epitaxial layer 3 and the depth of the gate region 5. For example, to obtain S of 10 ³ to 10 ⁴ ,
Usually, l ₁ = 2 to 3 μm and l ₂ = 5 to 6 μm are required.

[0007]

By the way, as shown in the figure, it is necessary to provide a separation region 8 between each SIT in the solid-state image pickup device having the above-described structure to separate the signal charges of each SIT. However, methods such as oxide film separation, diffusion separation, and V-shaped groove separation are generally used for this separation. In this case, the isolation region 8 is provided from the surface of the epitaxial layer 3 to the substrate 2, but the thicker the epitaxial layer 3, the more difficult it is to form the region. On the other hand, forming the gate region 5 deep in order to increase the optical amplification factor S has a limit in the diffusion method and the like. Further, when the gate region 5 is deepened, light is absorbed in the gate region 5 and the spectral sensitivity deteriorates. For these reasons, in the solid-state imaging device composed of the SIT having the vertical structure, there is a limit to the improvement of the sensitivity, which is an unavoidable drawback in the structure.

In order to eliminate such drawbacks, the present applicant has developed a solid-state image pickup device using a lateral SIT in Japanese Patent Application No. 58-245059. FIG. 2 shows an example of the structure of the lateral structure SIT. This horizontal structure SI
T (hereinafter abbreviated as LSIT) 11 is p ⁻ or p
An n ⁻ -type epitaxial layer 13 forming a channel region is grown on the shaped substrate 12 and the epitaxial layer 13 is formed.
To reach from the surface to the substrate 12 by a diffusion method or the like n ⁺
-Shaped source region 14 and drain region 15 are formed, and a gate insulating film 16 is formed on the surface of the epitaxial layer 13 between the source region 14 and the drain region 15.
An insulated gate is formed by providing a gate electrode 17 made of polysilicon or the like through. A source electrode 18 and a drain electrode 19 made of Al or the like are bonded to the source region 14 and the drain region 15, respectively, and are insulated from the adjacent LSIT by reaching the substrate 12 from the surface of the epitaxial layer 13. It is separated by the object 20. Hereinafter, an LSIT having such an insulated gate structure will be referred to as I
Abbreviated as GLT (Insulated Gate Lateral Transistor).

In the IGLT 11 shown in FIG. 2, the source (drain) electrode voltage V _S = 0 and the drain (source) electrode voltage V _D = in the dark current state in which no light is emitted.
0, gate electrode voltage V _G = V (V <0) substrate voltage V _SUB
= V ₁ (V ₁ <0), a depletion layer spreads over the entire channel from the boundary between the gate region 16 made of an insulating film and the channel region 13 depending on the state where the gate voltage V is applied to the gate electrode 17. At this point, however, there is no hole in the depletion layer because of non-steady-state operation. Next, when light is irradiated to enter the depletion layer, a positive photo-electron pair is generated and holes are accumulated at the interface between the gate insulating film 16 and the channel region 13. The height of the barrier potential between the source / drain regions is reduced by the amount of holes accumulated at the interface.

When a positive voltage is applied to the drain electrode 19 after a certain hole accumulation time, a source / drain current I _SD according to the interface accumulated holes flows. This current I _SD increases as compared with the case where no light is irradiated and no holes are present at the interface. That is, the amount of light can be extracted as a change in the source / drain current I _SD . The applicant of the present application has also proposed an LSIT having a junction gate structure in Japanese Patent Application No. 58-245059.

An object of the present invention is to provide a solid-state image pickup device having a lateral electrostatic induction transistor as a solid-state image pickup element, which can adopt an arbitrary signal readout method, and therefore can be designed appropriately so that the degree of freedom in designing can be greatly improved. To provide a device.

[0012]

In order to achieve the above object, according to the present invention, the surface of a semiconductor layer having a second conductivity type formed on an insulator or a high resistance semiconductor substrate having a first conductivity type is formed. Providing a source region and a drain region made of a low resistance diffusion layer having a second conductivity type,
A solid state comprising a static induction transistor configured such that a gate region for accumulating carriers generated by photoexcitation is provided between the source region and the drain region and a source / drain current flows in parallel with the surface of the semiconductor layer. An array having a large number of image pickup devices arranged in a matrix and a horizontal and vertical scanning circuit for sequentially scanning each solid-state image pickup device of the array are provided, and at least two terminals of gate, source and drain terminals of each solid-state image pickup device Each line is connected in common and the potential of each line is controlled by the horizontal and vertical scanning circuits to sequentially source / drain current according to the photocharge accumulated in the gate region of each solid-state image sensor. And scanning means flowing through the line.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a solid-state image pickup device composed of a lateral static induction transistor which can constitute a solid-state image pickup device of the present invention will be described. 3A and 3B show a first example of the solid-state image pickup device, FIG. 3A is a plan view, and FIG. 3B is X- of FIG. 3A.
A cross-sectional view taken along line X'is shown. The solid-state image sensor 21 of this example is an IG
An n ^{+ type} source region 24 and a drain region having an LT structure formed by growing an n ^{− type} epitaxial layer 23 forming a channel region on a p ⁻ substrate 22 and adding an n type impurity into the epitaxial layer. 25 are formed, and a source electrode 26 and a drain electrode 27 made of Al or the like are joined to these regions, respectively, and on the surface of the epitaxial layer 23 so as to completely surround each of the source region 24 and the drain region 25. A gate electrode 29 made of a transparent conductive material such as SnO ₂ or ITO is provided through the gate insulating film 28 to form an insulated gate. In this example, a plurality of IGLTs 21 are formed on the substrate 22 in a matrix form, and between adjacent pixels, a semiconductor oxide provided from the surface of the epitaxial layer 23 to the substrate 22 is provided.
Electrical isolation is provided by the isolation region 30 made of an insulator or the like.

In this example, since the insulated gate is provided so as to completely surround each of the source region 24 and the drain region 25, the gate area, that is, the aperture ratio can be increased and the channel region between the source and the drain can be obtained. Can be widely used. As a result, the stability of the gate potential at the time of light input is improved, and a good S / N can be obtained.

4A and 4B show a second example of the solid-state image pickup device. FIG. 4A is a plan view and FIG. 4B is a sectional view taken along line XX 'of FIG. 4A. The solid-state imaging device 31 has the IGLT structure as in the first example. In this example, the source region, the drain region and the insulated gate are formed concentrically and only the source region is completely surrounded by the insulated gate. It is the one. That is, the n ^{− type} epitaxial layer 33 forming the channel region on the p ⁻ substrate 32.
And an n ^{+ type} circular source region 34 formed by adding an n type impurity into the epitaxial layer and a drain region 35 formed concentrically so as to completely surround the source region 34. And a source electrode 36 and a drain electrode 37, which are made of Al or the like, are bonded to each other, and a gate insulating film 38 is formed on the surface of the epitaxial layer 33 between the source region 34 and the drain region 35 so as to completely surround the source region 34. Through SnO ₂ , ITO
A gate electrode 39 made of a transparent conductive material such as is provided to form a concentric insulated gate. In this example, the substrate 32
A plurality of IGLTs are formed so as to be positioned at the vertices of an equilateral triangle, and adjacent pixels are made of a semiconductor oxide, an insulator or the like provided from the surface of the epitaxial layer 33 to the substrate 32. Electrical isolation is provided by the isolation region 40.

According to this example, the source region 34, the drain region 35, and the insulated gate are formed concentrically in addition to the same effect as the first example, so that the variation in characteristics between pixels is small. In addition, the insulated gate does not directly contact the isolation region 40, so that the surface leakage current in the isolation region 40 can be ignored.

Incidentally, the source region 34 and the drain region 35.
Alternatively, the drain region 35 may be completely surrounded by the insulated gate by changing the formation positions of and, and in this case, the same effect can be obtained. Further, the planar shape of the pixel according to this example is not limited to a circular shape, and may be any shape that is topologically equivalent.

5A and 5B show a third example of the solid-state image pickup device. FIG. 5A is a plan view and FIG. 5B is a sectional view taken along line XX 'of FIG. 5A. This solid-state imaging device 41 is a junction gate structure LSIT (hereinafter referred to as Junction Gate Lath).
The abbreviation of JTLT is abbreviated as teral Transistor), and the junction gate completely surrounds each of the source region and the drain region as in the first example. That is, an n ^{− type} epitaxial layer 43 forming a channel region is grown on the p ⁻ substrate 42,
N formed by adding n-type impurities to this epitaxial layer
^{A + type} source region 44 and a drain region 45 are formed, and a source electrode 4 made of Al or the like is formed in each of these regions.
6 and the drain electrode 47 are joined together, and a p ^{+ -type} gate region 48 formed by adding a p-type impurity is formed so as to completely surround each of the source region 44 and the drain region 45. SnO ₂ , I in the region 48
A gate electrode 49 made of a transparent conductive material such as TO is provided so as to be joined to form a joined gate. It should be noted that adjacent pixels in a matrix are electrically isolated from each other by an isolation region 50 made of a semiconductor oxide, an insulator, or the like, which reaches the substrate 42 from the surface of the epitaxial layer 43. In this example,
Only the gate structure is different from the first example.
The effect is similar to that of the first example.

6A and 6B show a fourth example of the solid-state image pickup device, FIG. 6A is a plan view, and FIG. 6B is a sectional view taken along line XX ′ of FIG. 6A. This solid-state image sensor 51 is
Although it has the JGLT structure as in the third example, in this example, the source region, the drain region and the gate region are formed concentrically and only the source region is surrounded by the gate region as in the second example. It is the one. That is, p
^An n ^{+ type} circular source region 54 formed by growing an n ^{− type} epitaxial layer 53 forming a channel region on a substrate 52 and adding an n type impurity into the epitaxial layer, and the source region 54 completely. A drain region 55 is formed concentrically so as to surround it, and A is formed in each of these regions.
A source electrode 56 and a drain electrode 57 made of 1 or the like are provided so as to be bonded to each other, and a p ^{+ type} impurity is added between the source region 54 and the drain region 55 so as to completely surround the source region 54. Gate region 58 is formed, and a gate electrode 59 made of a transparent conductive material such as SnO ₂ or ITO is joined to the gate region 58 to form a concentric junction gate. Note that adjacent pixels are electrically separated from each other by a separation region 60 formed of a semiconductor oxide, an insulator, or the like, which is provided so as to reach the substrate 52 from the surface of the epitaxial layer 53.

This example is different from the second example only in the gate structure, and its operation and effect are similar to those of the second example. Further, the formation positions of the source region 54 and the drain region 55 may be replaced with each other so that the drain region 55 is completely surrounded by the gate region 58, and the same effect can be obtained in this case as well.

7A and 7B show a fifth example of the solid-state image pickup device. FIG. 7A is a plan view and FIG. 7B is a sectional view taken along line XX ′ of FIG. 7A. The solid-state image sensor 61 is
4A, only that the isolation region 62 reaches the substrate 32 from the surface of the n ⁻ -type epitaxial layer 33 forming the channel region and is formed in a hexagonal shape with a p ⁺ diffusion layer having a conductivity type opposite to that of the epitaxial layer 33. Different from the second example shown in FIG. 4B, the same reference numerals as those shown in FIGS. 4A and 4B represent those having the same function.

As described above, by forming the isolation region 62 with the diffusion layer, the leakage current at the interface of the isolation region, that is, between pixels, can be suppressed more stably as compared with the case where the isolation region 62 is made of a semiconductor oxide or an insulator. It can be manufactured easily.

In the example shown in FIGS. 7A and 7B, the isolation region 62 made of the p ⁺ diffusion layer is provided so as to reach the substrate 32 from the surface of the epitaxial layer 33, but the isolation region 62 does not necessarily have to reach the substrate 32. There is no. A solid-state image sensor in this case is shown in FIG. 8A as a sixth example.

The solid-state imaging device 65 shown in FIG. 8A differs from the fifth example only in that the isolation region 62 made of ap ⁺ diffusion layer is formed from the surface of the epitaxial layer 33 to a depth that does not reach the substrate 32. Is. In this case, the separation area 6
As the depletion layer in the second downward reaching the substrate 32 is formed, by applying an appropriate reverse bias V _R with respect to the epitaxial layer 33 through the electrode 66 in the isolation region 62, electrically between adjacent pixels To separate.

According to this example, the same effect as that of the fifth example can be obtained, and since the depth of the isolation region 62 does not reach the substrate 32, it is 3 times larger than the case where the area is formed until it reaches the substrate 32. It can be reduced by up to 5 times, so that the pixel size can be reduced, which is extremely advantageous for high density. Incidentally, such a structure in which the separation region is formed by diffusion can be similarly applied to the LSIT and the like described in Japanese Patent Application No. 58-245059.

When the source region or the drain region is formed on the outermost side as shown in the second and fourth examples, the isolation region can be formed by the outermost region. Solid-state imaging devices in this case are shown in FIGS. 8B and 8C as the seventh and eighth examples, respectively.

A solid-state image pickup device 67 shown in FIG. 8B deepens the central portion of the n ⁺ -type drain region 35, and a solid-state image pickup device 69 shown in FIG. 8C shows the entire depth of the n ⁺ -type drain region 35. It is different from the second example only in that it is deepened so that the drain region 35 also acts as an isolation region.

As described above, by making a part or the whole of the drain region 35 deep, the drain region 35 can also act as an isolation region between pixels, thereby increasing the density and manufacturability. Can be done easily.
In addition, the structure in which the drain region also acts as the isolation region can be effectively applied to the JGLT structure shown in the fourth example, and even when the outermost side is the source region, this is similarly performed. The source region can also act as the isolation region.

In the first, second, fifth to eighth examples and the IGLT structure as shown in FIG. 2, the gate of the conductivity type opposite to that of the epitaxial layer is formed on the surface of the epitaxial layer in contact with the gate insulating film. Regions can be formed.
The solid-state image pickup device in this case is shown in FIGS. 9A, 9B and 10 as the ninth and tenth examples, respectively.

9A and 9B are a plan view and its X-
The solid-state imaging device 71 shown in the cross-sectional view taken along the line X ′ is the same as that of the fifth example IGLT shown in FIGS. 7A and 7B, in which the n ^{+ -type} source region 34 is formed on the surface of the n ⁻ -type epitaxial layer 33 in contact with the gate insulating film 38. Further, a p-type gate region 73 is formed over the drain region 35 by an ion implantation method or the like. In addition, the solid-state imaging device 75 shown in FIG. 10 is similar to the solid-state imaging device 75 shown in FIGS.
The p-type channel region 73 is formed on a part of the surface of the n ⁻ -type epitaxial layer 33 which is in contact with the.

As described above, by providing the gate region having a conductivity type opposite to that of the outer semiconductor layer on the surface of the semiconductor layer immediately below the gate insulating film, the saturated exposure amount can be further increased, and particularly, the ninth example. When the gate region is formed over the source region and the drain region as described above, JGL
A so-called self-aligned structure process can be adopted in the source, gate and drain positions as compared with the T structure.

In the above-mentioned IGLT and JGLT, the first and third examples are shown as a structure in which each of the source region and the drain region is completely surrounded by the gate region, but these regions are formed concentrically. Each of the source region and the drain region can be completely surrounded by the gate region.

11A and 11B show an eleventh embodiment of the solid-state image pickup device.
FIG. 11A is a plan view, and FIG.
11A is a sectional view taken along line XX ′ of FIG. This solid-state image sensor
Reference numeral 81 denotes an IGLT structure, which includes a source region and a drain.
These so that each gate region is completely surrounded by the gate region.
Each area is formed concentrically. Ie p ^-
N forming a channel region on the substrate 82^-Shape epitaxy
Of the n-type layer is grown in the epitaxial layer.
N made by adding pure substances⁺Shaped circular source region 84 and
Concentric with the ring-shaped drain region 85 having a notch
It is formed in a circular shape, and each of these regions is made of Al or the like.
The source electrode 86 and the drain electrode 87 are provided by being joined
In addition, each of the source region 84 and the drain region 85
Through the notches in the drain region 85 so that they completely surround each other.
Gate connection to the surface of the epitaxial layer 83
SnO through the membrane 88₂・ From transparent conductive materials such as ITO
The gate electrode 89 is formed to form a concentric insulated gate.
To achieve. In this example, a plurality of IGLTs are provided on the substrate 82.
Formed so that each is located at the apex of the triangle,
The space between the adjacent pixels is from the surface of the epitaxial layer 83.
Consists of semiconductor oxides, insulators, etc. that reach the plate 82
Electrical isolation is provided by the isolation region 90.

According to this example, the same effect as that described in the first example can be obtained, and in particular, since each region is formed concentrically, the variation between pixels can be reduced. In this way, in order to completely surround each of the source region and the drain region with the gate region,
The configuration in which these regions are concentrically formed is not limited to the IGLT structure, but can be effectively applied to the JGLT structure.

12A and 12B show a solid-state image pickup device according to the twelfth embodiment.
12A is a plan view and FIG. 12B is a sectional view taken along line XX ′ in FIG. 12A. This solid-state image sensor 91 is the same as the IGLT 81 shown in the eleventh example, except that the gate region in the cutout portion of the drain region 85 is removed, and the first gate region surrounding the source region 84 and the first gate region surrounding the drain region 85. The two gate regions are provided separately. These first and second gate regions are formed on the surface of the epitaxial layer 83 by the gate insulating film 88-1,
Gate electrodes 89-1 and 89-2 are provided via 88-2.

By separating the gate region in this way, the optical signal charge accumulated in the outermost second gate region in the amplification stage is controlled to the inner side for controlling the current between the source region 84 and the drain region 85. Can be transferred to the first gate region of the first gate region, thereby obtaining a larger amplification factor as compared with the single gate configuration.

13A and 13B show a solid-state image pickup device according to a thirteenth embodiment.
13A is a plan view and FIG. 13B is a sectional view taken along line XX ′ in FIG. 13A. This solid-state imaging device 101 is the IGLT3 shown in the second example (FIGS. 4A and 4B).
1, the gate electrodes are the first gate electrode 39-1 and the second gate electrode 39-2 on the same gate insulating film 38.
Further, the first and second gate regions are formed by the respective gate electrodes separated into a double ring shape.

According to this structure, in addition to the effect of the twelfth example described above, the efficiency of transfer of the optical signal charge from the first or second gate region to the second or first gate region can be increased.

The configurations in the twelfth and thirteenth examples have the above-mentioned JGLT structure and other IGLTs.
It can be effectively applied to a structure.

In each of the examples of the solid-state image pickup device described above, the source electrode and the drain electrode were formed of a metal such as Al, but it was tested that the incident light was received even under the source region and the drain region in contact with the gate electrode. Found out. Therefore, the source electrode and the drain electrode can be formed of a transparent electrode or a semi-transparent electrode such as polysilicon similarly to the gate electrode, which can further increase the light receiving efficiency.

Further, in the above example, n ^- / p ^- or was epitaxial with two-layer structure of p, p ^- used only as a substrate, a IGLT and JQLT with good photoelectric conversion characteristics without the epitaxial layer Can be obtained, which makes the process easier and cheaper. Further, even if only p ⁻ is used as the substrate in this way, the back gate can be applied from the substrate as in the n ⁻ / p structure. With this configuration, the channel current can be controlled by both the gate on the surface and the substrate, so that the photoelectric conversion characteristics can be changed by the substrate bias even in a device having the same structure. Therefore, if the substrate bias is appropriately selected, desired photoelectric conversion characteristics can be freely set.

Further, in addition to the n ⁻ (channel) / p ⁻ or p substrate, a layer structure of n ⁻ (channel) / insulator or n ⁻ (channel) / insulator / Si can be used, and particularly the latter. In this case, there is an advantage that the back gate can be applied in a completely insulated form. Furthermore, in each of the above examples, when the charges flowing through the channel region are all electrons, that is,
Although the n-channel one is shown, the channel region may be formed by a p-channel. However, in this case, it is necessary to reverse the conductivity type of each region and reverse the polarity of the bias applied voltage. As a semiconductor material, IV of the periodic table is used.
In addition to the group C and V element simple elements and bulk crystals such as III-V group and II-VI group compound semiconductors, these amorphous bodies can also be used.

Next, the characteristics and driving method of the solid-state image pickup device composed of the lateral static induction transistor (LSIT) as described above will be explained. The solid-state imaging device described above is roughly classified into an insulated gate lateral static induction transistor (IGLT) and a junction gate lateral static induction transistor (JGLT) according to its gate structure, but the IGLT will be described below as an example. To do.

FIG. 14 shows an example of the IGLT structure, which corresponds to the above-mentioned second example shown in FIG. An n ⁻ -type epitaxial layer 11 is formed on the p-type substrate 111.
2 is grown, and a drain region 113 made of an n ⁺ diffusion layer and a source region 114 also made of an n ⁺ diffusion layer are concentrically formed in this epitaxial layer. A gate insulating film 115 is formed on the surface of the epitaxial layer 112 between the drain region 113 and the source region 114, and a gate electrode 116 made of a transparent conductive material is provided thereon to form an insulated gate structure. . Therefore, in this example, the source region 114 is completely surrounded by the gate region. A source terminal 117 connected to the source region 114, a drain terminal 118 connected to the drain region 113, a gate terminal 119 connected to the gate electrode 116, and a substrate terminal 120 connected to the substrate 111 have source voltages V _S , The drain V _D , the gate voltage V _G, and the substrate voltage V _SUB are applied.

FIG. 15 is an equivalent circuit diagram of the solid-state image pickup device shown in FIG. The specifications of the solid-state image sensor of this example are as follows. The substrate 111 is made of silicon and has a p-type impurity concentration of 1 × 10 ¹² atoms / cm ³ . The epitaxial layer 112 forming the channel is made of silicon and has an n-type impurity concentration of 7 × 10 ¹² atoms /
It is cm ³ . The channel thickness d ₂ + d ₃ is 4 to 10 μm
m, the diffusion depth d ₂ of the drain region 113 and the source region 114 is 0.5 μm, the thickness d ₁ of the gate insulating film 115 made of silicon oxide is 800 Å, and the circular source region 1 is formed.
The diameter l ₁ of 14 is 6 μm, and the length l of the ring-shaped gate region is
₂ is about 3 μm. It has been confirmed that in the IGLT thus configured, the area of the channel region can be made sufficiently large because the source region is surrounded by the gate region, and good photoelectric conversion characteristics can be obtained.

Next, the characteristics of the above-mentioned solid-state image sensor will be described. In FIG. 16, the horizontal axis represents the gate voltage V _G applied to the gate terminal 119 on a linear scale, and the vertical axis represents the current _ID flowing between the source terminal 117 and the drain terminal 118 on a logarithmic scale. The voltage V _D (> 0) applied to 118 is shown as a parameter, the source voltage V _S is V _S = 0, and the substrate voltage V _SUB is negative and p between the substrate 111 and the epitaxial layer 112 is set.
The n-junction is reverse biased. As can be seen from these graphs, the larger the drain voltage V _D , the larger the current I _D
It can also be seen that the larger the gate voltage V _G is, the larger the current I _D flows. In FIG. 16, the solid line shows the current I _D in a non-steady state in which almost no hole inversion layer exists directly below the gate insulating film 115, and the dotted line shows the thermal equilibrium state in which the hole inversion layer is completely present. The current I _D is shown. Here, V _S = 0 and V _SUB = V _SUB1 (<0) are the same conditions.

Next, an example of the light receiving operation of the above-mentioned solid-state image pickup device will be described with reference to FIG. First, in the dark state where light is not radiated, the source voltage V _S =
0, drain voltage V _D = V _D1 = 0, gate voltage V _G = V
_G1 (<0) and substrate voltage V _SUB = V _SUB1 (<0).
By applying the gate voltage V _G1 to the gate terminal 119, the depletion layer spreads from the boundary between the gate insulating film 115 and the epitaxial layer 112 to the entire channel region. At this point, there are no holes in the depletion layer because of the non-steady state. Next, when light is irradiated, hole-electron pairs are generated in the depletion layer, and the holes are accumulated in the gate region at the interface between the gate insulating film 115 and the epitaxial layer 112. Thus, when holes are accumulated at the interface, the height of the barrier potential between the source / drain regions correspondingly decreases.

When a positive voltage V _D2 is applied to the drain terminal 118 after a certain period of hole accumulation, a current I _D flows between the source and drain regions according to the holes accumulated at the interface. This current I _D is larger than the dark current V _D1 flowing between the source / drain regions when light is not irradiated and holes are not present at the interface. That is, the change in the amount of incident light can be extracted as the change in the current I _D flowing between the source / drain regions.

In this case, when the solid-state image pickup device is constructed so that at least one of the source region and the drain region is surrounded by the gate region, the area of the gate region, that is, the area of the channel region increases, and the aperture ratio increases, so that photoelectric conversion is performed. The efficiency is high, and it is possible to stably accumulate holes in the gate region in an amount corresponding to the amount of incident light.
Therefore, the S / N of the current I _D can be increased.

When a hole having a saturated exposure amount or more is incident during the light accumulation time, holes having a saturation amount or more are generated, but most of these holes flow to the substrate 111. Therefore, when a light amount more than the saturated exposure amount is incident, the source-drain current I
_D is fixed to the saturation current value I _D2 .

In FIG. 18, the horizontal axis represents the light accumulation time on a linear scale, the vertical axis represents the source-drain current I _D on a logarithmic scale, and the light intensity is shown as a parameter. The higher the strength, the faster the source-drain current _ID rises, and the weaker the strength, the slower the rise. It takes about 10 seconds to reach the saturation current I _D2 in the dark, and this time is determined by the thermal generation rate of holes.

When the above-mentioned solid-state image pickup device is actually incorporated in a solid-state image pickup device, a change in the current I _D is mainly converted into a change in voltage for signal processing. Main current-voltage conversion methods include a source follower and a source ground, which will be described below with reference to FIGS. 19 and 20.

FIG. 19 shows a source follower in which a load resistor R _L is connected to the source terminal 117 and an output voltage V _{OUT is} taken out from between the load resistors. FIG. 20 shows an example of source grounding. In this example, a load resistance R _L is connected to the drain terminal 118, and the output voltage V _OUT is taken out from between the load resistances. In FIGS. 19 and 20, light incident on the gate region is indicated by hν.

FIG. 21 is a timing chart of the photoelectric conversion operation, where the horizontal axis represents time t and the vertical axis represents the gate voltage V _G , drain voltage V _D , source voltage V _S and substrate voltage V _SUB . To show. Substrate voltage V _SUB
Is always the reverse bias voltage V _SUB1 (<0), and the source voltage V _S is always kept at the ground level V _S1 (= 0). The operation cycle T is composed of a storage time T ₁ , a read time T _2, and a reset time T ₃ .

During the accumulation time T ₁ , the gate voltage V _G is kept at the reverse bias voltage V _G1 (<0) and the drain voltage V _D is kept at the ground level V _D1 (= 0). In such a bias state, holes generated by incident light are accumulated in the gate region, but no signal output is generated. During the read time T ₂ , the gate voltage V _G is the read voltage V _G2 (V _G1 ≦
V _G2 <0) and the drain voltage V _D is high level V
_D2 (> 0) is set, and the signal can be read. V _G1 in FIG. 21 <has been a V _G2, it may be a V _G1 = V _G2. During the reset time T ₃ , the gate voltage V _{G is set} to the forward reset voltage V _G3 (> 0) while maintaining the drain voltage V _D high level V _D2 to release the holes accumulated in the gate region. Here, in the case where the output signal does not have to be output during the reset time T ₃ , the drain voltage V _D may be the ground level V _D1 (= 0). As a reset method, there is also a method in which one or both of the source voltage V _S and the drain voltage V _D are forward biased with respect to the gate.

After performing light accumulation as described above, the reading is performed.
FIG. 22 and FIG. 23 show the output signals obtained by performing the projection.
Shown in. In FIG. 22, the horizontal axis represents the incident light amount on a logarithmic scale.
Is the output voltage V when light is incident on the vertical axis._OUTAnd output in the dark
Voltage V_DARKDifference with V _OUT-V_DARKThe absolute value of
It is shown on a logarithmic scale. Clear from Figure 22
As you can see, the gradient is

[Equation 2] It was confirmed by an experiment that good characteristics of can be obtained.

In FIG. 23, the horizontal axis represents the drain voltage V _D2 at the time of reading on a linear scale, and the vertical axis represents the absolute value │V _OUT -V _DARK │ of the output voltage difference between the light incident state and the dark state. It is shown on a scale. As is apparent from FIG. 23, it was experimentally confirmed that the higher the drain voltage V _D2 at the time of reading, the larger the output voltage obtained, and the better linearity of this relationship. It was also confirmed by experiments that the saturation exposure amount, sensitivity, gradation degree γ, etc. can be changed by adjusting the gate voltage V _G , the source voltage V _S , the drain voltage V _D , and the substrate voltage V _SUB .

The operation method of the solid-state image pickup device described above is shown in FIG.
However, the method is not limited to the one shown in FIG. Since it suffices that no output signal be output during the accumulation time T ₁ , the source voltage V _S can be set to the high level V _S2 = V _D2 (> 0) during this accumulation time. An operation timing chart in this case will be described with reference to FIG.

In FIG. 24, the horizontal axis represents time t and the vertical axis represents time t.
The axis is the gate voltage V_G, Drain voltage V_D, Source voltage V
_SAre shown respectively. The substrate voltage V_SUBIs constant
And V _SUB<0. Accumulation time T₁Inside is the gate voltage V
_GIs the reverse bias voltage V_G1(<0), drain voltage V_D
And source voltage V_SIs high level V_S2= V_D2(> 0)
It becomes a state where it receives light but does not output a signal.
Has become. Read time T₂Inside is the gate voltage V_GIs
Read voltage V_G2(V_G1≤V_G2<0) and source voltage
V_SIs low level V_S1(= 0). By this
Signal is ready to be read. Also, reset time T₃Is
Voltage V_GForward reset voltage V_G3(> 0)
The holes accumulated by the incidence of light directly below the gate electrode.
It is in a state of being discharged from the gate region at.

In the example shown in FIG. 24, no signal is output as V _S1 = V _D1 (= 0) during the reset time T ₃ , but if a signal may be output during reset, The drain voltage V _D can also be set to the high level V _D2 .
Further, when V _G3 can be set large, the drain voltage V _D can be set to V _D2 and the source voltage V _S can be set to V _S2 . In the example shown in FIG. 24, since the source voltage V _{S is set} to the high level V _S2 during the accumulation time T ₁ , there is an effect that the light effect and the hole holding ability can be improved.

As described above, since the reset operation only needs to sweep the holes from directly under the gate, the substrate voltage V
It can be reset by changing _SUB . Next, such an example will be described with reference to FIG.

In FIG. 25, the horizontal axis represents time t, and the vertical axis represents the gate voltage V _G , the drain voltage V _D , the source voltage V _S , and the substrate voltage V _SUB in order from the top.
In this example, the substrate potential V _{SUB is set} to V during the reset time T _3.
By setting _SUB2 (<0), holes accumulated directly under the gate can be forcibly discharged to the substrate. In this method, since the gate voltage V _G may be binary, the driving circuit becomes simple. Furthermore, since resetting only needs to change the substrate voltage V _SUB , the effect is obtained that the entire chip can be reset collectively.

One of the factors that determine the optimum light receiving operation state for a certain incident light intensity is a method of changing the accumulation time T _1. The operation characteristic in this case is shown in FIG. 26 is a graph showing the incident light intensity on a logarithmic scale on the horizontal axis and the output | V _OUT −V _DARK | on the vertical axis on a logarithmic scale, and showing the accumulation time T ₁ as a parameter. As shown in FIG. 18, when the incident light intensity is weak, the output becomes small. However, for the same incident light intensity, the accumulation time T ₁
It can be seen from FIG. 26 that the output becomes smaller when becomes shorter. Therefore, the intensities of the incident light are detected, and the accumulation time T ₁ is determined according to them. When the incident light intensity is high, the accumulation time T ₁ is shortened, and when the incident light intensity is low, the accumulation time T ₁ is determined. By making the length longer, an optimum exposure state can be obtained.

To obtain the optimum exposure state as described above,
This can also be done by changing the gate voltage V _G2 . In FIG. 27, the horizontal axis represents the read gate voltage V _G2.
Is taken on a linear scale, and the vertical axis shows the output voltage │V _OUT −
V _DARK | is taken on a logarithmic scale, and the incident light intensity is shown as a parameter. It can be seen that when the gate voltage V _G2 is low and the incident light intensity is low, the output voltage is small, and when the gate voltage V _G2 is high and the incident light intensity is high, the output voltage is saturated quickly. Therefore, by detecting the incident light intensity and reading the signal by increasing the gate voltage V _G2 when the incident light intensity is low, and by reading the signal by lowering the gate voltage V _G2 when the incident light intensity is high, Optimal light receiving operation will be achieved.
Furthermore, it is also clear that by changing the gate voltage V _G1 or the substrate voltage V _SUB1 during the accumulation time T ₁ , a good exposure state can be obtained in a wider range.

In the above description of the operation of the solid-state image pickup device, the IGLT having the insulated gate structure is taken as an example, but it goes without saying that the same description can be applied to the JGLT in which the gate diffusion region is taken through the capacitor. .

Next, the solid-state image pickup device of the present invention will be described. In a solid-state image pickup device, solid-state image pickup elements are arranged in a matrix and raster-scanned to extract a video signal. This scanning method includes drain /
There are a gate selection method, a source / gate selection method, and a source / drain selection method, each of which will be described below.

In the first embodiment of the solid-state image pickup device,
As shown in FIG. 28, m × n LSIT 250-1
1,250-12,250-21,250-22, ...
.., 250-mn are arranged in a matrix and signals are sequentially read out by the XY address system. The LSIT constituting each pixel is not limited to the lateral static induction transistor having a structure in which at least one of the source and drain regions is surrounded by a gate region as shown in FIGS. A lateral static induction transistor having a structure in which a gate region is provided between the source and drain regions can also be used.

In this embodiment, the source terminal of each LSIT is grounded, and the gate terminals of the LSIT group of each row arranged in the X direction are row lines 251-1, 251-2, ..., 25.
1-m respectively. In addition, the drain terminals of the LSIT groups in each row arranged in the Y direction are column lines 252-1.
, 252-n, and these column lines are respectively connected to column selecting transistors 253-.
1, 253-2, ..., 253-n and 253-
Video line 254 and ground line 25 through 1 ', 253-2', ..., 253-n ', respectively.
4'is commonly connected. A video power supply V _DD is connected to the video line 254 via a load resistor 255. Row lines 251-1, 251-2, ..., 251-m are connected to a vertical scanning circuit 256, and signals φ _G1 , φ _G2 , ...
.., _.phi.Gm are configured to be applied sequentially. Also,
Column selection transistors 253-1, 253-2, ...
253-n and 253-1 ', 253-2', ...
, 253-n 'are connected to the horizontal scanning circuit 257 so that signals φ _D1 , φ _D2 , ..., φ _Dn and their inverted signals are respectively applied.

Next, referring to FIG. 29, the solid-state image pickup of this embodiment is performed.
The operation of the image device will be described. FIG. 29 shows the vertical scanning signal φ_GOh
And horizontal scanning signal φ_DIs shown. Line 25
Signals φ applied to 1-1, 251-2, ..._G1, Φ
_G2, ... Read gate voltage Vφ with small amplitude
_GAnd a reset gate voltage Vφ having an amplitude larger than that_R
And the scanning period t of one row line._HBetween
Is Vφ_G, The horizontal block before moving to the horizontal scanning of the next row line.
Ranking period t_BLVφ_RSet to the value of
Has been. In addition to the gate terminal of the column selection transistor
Horizontal scanning signal φ _D1, Φ_D2, ... are column lines 252
Signals for selecting -1, 252-2, ...
The low level is the column selection transistors 253-1 and 253-
3-2, ... OFF, anti-selection transistor 253-
1 ', 253-2', ... turned on, high level selects columns
Transistor for turning on, anti-selection transistor for turning off
The voltage value is set to

Next, the operation of the solid-state image pickup device shown in FIG. 28 will be described with reference to the signal waveforms shown in FIG. 29, based on the above-described operating principle of the LSIT. When the signal φ _G1 becomes Vφ _G due to the operation of the vertical scanning circuit 256, the row line 251
LSIT groups 250-11 and 250-1 connected to -1
2, ..., 250-1n are selected, and the horizontal scanning circuit 2 is selected.
The horizontal selection transistors 253-1, 253-2, ..., 2 according to the signals φ _D1 , φ _D2 , ...
When 53-n sequentially turn on, LSIT250-11,
The signals 50-12, ..., 250-1n are sequentially output from the video line 254.

Subsequently, the LSIT groups 250-11 and 250-11
50-12, ..., 250-1n are signals V_G1Has a high level
Le Vφ_RAre reset all at once, then the optical communication
No. can be accumulated. Then signal φ_G2Is Vφ_GWhen
Then, the LSIT group 25 connected to the row line 251-2
0-21,250-22, ..., 250-2n is selected
Horizontal scanning signal φ_D1, Φ_D2, ... by LSIT
250-21, 250-22, ..., 250-2n
Optical signals are read out sequentially, and then φ_G2Is Vφ _RBecomes
It is reset all at once. And so on
The optical signal of the LSIT of the
Signal is output.

In this first embodiment, the anti-select transistor groups 253-1 ', 153-2', ..., 253-
The reason why n'is provided is to fix the drain of the unselected LSIT to the ground potential via these transistors, but an optical signal is stored in the gate even if these anti-selection transistor groups are not provided. Therefore, the anti-selection transistor can be omitted from this embodiment. Further, in this embodiment, but were different from the voltage of the vertical scanning signal phi _G between the time accumulated during the reading, it is also possible to V.phi _G during both storage time and reading. In this case,
Since the gate pulse φφ _G may have two levels, the configuration of the vertical scanning circuit 256 becomes simple.

In the first embodiment described above, the LSIT25
The source terminals of 0-11, 250-12, ..., 250-mn are all at a constant potential, that is, the ground level, but the source terminals of the LSIT groups in each column are common and are parallel to the horizontal scanning circuit. It can also be connected to a horizontal reset circuit composed of a shift register provided in.

FIG. 30 shows a second embodiment provided with such a horizontal reset circuit. 30, the LSIT groups 250-11, 250-21, ...
..., 250-m1; 250-12, 250-22, ...
..., 250-m2; ...; 250-1n, 250-
Source terminals of 2n, ..., 250-mn are connected to source lines 259-1, 259-2 ,.
A horizontal reset circuit 258 connected in common to n and having these source lines arranged in parallel to the horizontal scanning circuit 257.
Connect to.

Next, the operation of this embodiment will be described with reference to FIG.
explain. A signal φ is generated by the operation of the vertical scanning circuit 256._G1But
Vφ_GThen the LS selected on the row line 251-1
IT group 250-11, 250-12, ..., 250-
1n is selected and sequentially output from the horizontal scanning circuit 257.
Signal φ_D1, Φ_D2, ... by horizontal selection transistor
253-1, 253-2, ..., 253-n are sequentially
Is turned on and the selected LSIT group 250-11, 250-11,
50-12, ..., 250-1n are sequentially turned on
The source drain corresponding to the photocharge accumulated in the gate region
The in-current flows to the video line 254 and the load resistance 255
An output signal is obtained in the meantime. Reset each LSIT is a signal
φ_D1, Φ_D2Right after the horizontal reset circuit 258
Signal φ _S1, Φ_S2, ..., φ_SnThe source line 259
-1,259-2, ..., 259-n
Do more. That is, in the source area of each LSIT,
Voltage Vφ_GApplying forward bias potential to
The holes accumulated in the gate area can be swept out by
Wear.

In the first embodiment, resetting is performed by LS of each row.
Although it is performed for each IT group, in the present embodiment, since it can be performed for each LSIT, there is an effect that the light accumulation times of all the LSITs can be made completely the same. Further, since the pulse level of the gate voltage becomes binary, there is also an effect that the design of the vertical scanning circuit 256 becomes easy.

FIG. 32 shows a third embodiment of the solid-state image pickup device of the present invention which adopts the source / gate selection system. As shown in FIG. 32, in the solid-state imaging device of the present embodiment, LSIT 260-11, 260-12, ..., 2
Similar to the previous example, 60-mns are arranged in a matrix and the signals are read out by the XY address method. That is, the drains of the LSITs forming each pixel are commonly connected to the video power supply V _DD, and the gate terminals of the LSIT groups in each row arranged in the X direction are connected to the row line 261-.
1, 261-2, ..., 261-m, respectively. Further, the source terminals of the LSIT groups in each column arranged in the Y direction are column lines 262-1, 262-2 ,.
62-n.

These column lines are respectively connected to column selecting transistors 263-1, 263-2, ..., 263-.
n and 263-1 ', 263-2', ..., 263
-N 'are commonly connected to the video line 264 and the ground line 264', and the video line is grounded via the load resistor 265. And row line 261
-1, 261-2, ..., 261-m are connected to the vertical scanning circuit 266, and signals φ _G1 , φ _G2 , ...
_Gm is applied. Also, the column selection transistors 263-1, 263-2, ..., 263-n
And 263-1 ', 263-2', ..., 263-
The gate terminal of n'is connected to the horizontal scanning circuit 267, and is configured to receive the signals φ _S1 , φ _S2 , ..., φ _Sn and their inverted signals, respectively.

Next, the vertical scanning signal φ _G and the horizontal scanning signal φ _S will be described with reference to the signal waveform diagram shown in FIG. Signals applied to the row lines φ _G1 , φ _G2 , ...
It is intended made smaller than the amplitude of the read gate voltage V.phi _G and large amplitude of the reset voltage V.phi _R than, during the scanning period t _H of a row line V.phi _G, before moving to the horizontal scanning of the next line line Vφ during the blanking period t _BL of
It is set to the value of _R. Horizontal scanning signals φ _S1 , φ _S2 , ... Applied to the gate terminals of the column selecting transistors 263-1, 263-2 ,.
Is a signal for selecting a column line, and the low level is a column selection transistor 263-1, 263-2, ..., 26.
Turn off 3-n, anti-selection transistors 263-1 ', 2
63-2 ', ..., 263-n' are turned on, and the high level is set to a voltage value for turning on the column selecting transistor and turning off the anti-selecting transistor.

Next, based on the operating principle of LSIT, FIG.
The operation of the solid-state imaging device shown in 2 will be described. By the operation of the vertical scanning circuit 266, the signal φ _G1 changes to the read level Vφ.
_When it becomes _G , the LSIT connected to the row line 261-1
Groups 260-11, 260-12, ..., 260-1n
Is selected and the signal φ output from the horizontal scanning circuit 267 is selected.
_When the horizontal selection transistors 263-1, 263-2, ..., 263-n are sequentially turned on by _S1 , φ _S2 , ..., φ _Sn , LSIT 260-11, 260-12,
The signals of 260-1n are output from the video line 264.

Subsequently, this LSIT group is reset all at once when the signal φ _G1 becomes the high level Vφ _R. Then, when the signal phi _G2 is Vφ _G, LSIT group 260-21,260-22 connected to row line 261-2, ·
· ·, 260-2N is selected, the horizontal scanning signal phi _S1, phi
_{By S2} , ..., φ _Sn , LSIT260-21,26
The optical signals of 0-22, ..., 260-2n are sequentially read and then reset all at once. In the same manner, the optical signal of each pixel is sequentially read out and a video signal of one field is obtained.

In this embodiment, the anti-select transistor groups 263-1 ', 263-2', ..., 263-n 'are provided to fix the source of the non-selected LSIT to the ground potential. However, even if there is no anti-selection transistor group, it is possible to store an optical signal in the gate. Therefore, as a modification of the present embodiment, there is a solid-state imaging device without an anti-selection transistor. Further, in this embodiment, the gate voltage Vφ _G at the time of reading can be set to the same level as the level at the time of accumulation.

The present embodiment is characterized in that the drain wiring is easier and the pixel separation can be simplified as compared with the first embodiment. Therefore, it was tested that it is advantageous for miniaturization of one pixel. I confirmed it. Further, since each pixel signal is read in the source follower format, the influence of the drain parasitic capacitance is small and the load capacitance of the column line can be reduced, which is advantageous for high-speed reading.

In the third embodiment shown in FIG. 32, each LSI
Although the drain terminal of T is commonly connected to the power source V _DD ,
As shown in FIG. 4, the drain terminal of each LSIT can be connected to the video line 264, and the video line 264 can also be connected to the power supply V _DD via the load resistor 265 (source ground type readout). In the fourth embodiment, the sources and drains of all the unselected LSITs are interconnected via the anti-selection transistors, so that signals (anti-selection signals) are output at all from the LSITs other than the selected LSITs. There is a feature that is not done.

FIG. 35 shows a fifth embodiment of the solid-state image pickup device of the present invention which adopts the source / drain selection system. As shown in FIG. 35, the solid-state imaging device according to the present embodiment includes LSITs 270-11, 270-12 ,.
70-mn are arranged in a matrix and are configured to read signals by the XY address system. That is, the gate terminal of the LSIT forming each pixel is grounded, and the source terminal of the LSIT group of each row arranged in the X direction is the row line 271-1, 271-2 ,.
271-m, respectively. The drain terminals of the LSIT groups in each row arranged in the Y direction are connected to the column lines 272-1, 272-2, ..., 272-n.

These column lines are respectively connected to column selection transistors 273-1, 273-2, ..., 273-.
n and 273-1 ', 273-2', ..., 273
Video line 274 and video power supply V _DD via -n '
Are commonly connected to each. Video line 274
Is connected to the video power supply V _DD via an ammeter 275. And the row lines 271-1, 271-2, ...
271-m is connected to the vertical scanning circuit 276, and signals φ _S1 , φ _S2 , ..., φ _Sm are applied thereto. Also, the column selection transistors 273-1 and 273-
2, ..., 273-n and 273-1 ', 273-
The gate terminals of 2 ′, ..., 273-n ′ are connected to the horizontal scanning circuit 277, and the signals φ _D1 , φ _D2 , ...
.., φ _Dn and its inverted signal are added.

The vertical scanning signal φ _S and the horizontal scanning signal φ _D will be described based on the waveform chart shown in FIG. The signals φ _S1 , φ _S2 , ... Applied to the row lines are composed of a read source voltage Vφ _S having a small amplitude and a reset voltage Vφ _R having a larger amplitude, and are used for the scanning period t _H of one row line. The interval is Vφ _S , and the blanking period t _BL before the horizontal scanning of the next row line is set to the value of Vφ _R. Column selection transistor 273
Horizontal scanning signals φ _D1 , φ _D2 , ... Applied to the gate terminals of -1, 273-2, ..., 273-n are signals for selecting column lines, and a low level is a column selecting transistor. 273-1, 273-2, ..., 273-n are turned off, and anti-selection transistors 273-1 ', 273-
2 ', ..., 273-n' are turned on, and a high level is set to a voltage value for turning on the column selecting transistor and turning off the anti-selecting transistor.

Next, the operation of the solid-state image pickup device shown in FIG. 35 will be described based on the operation principle of the LSIT. When the signal φ _S1 becomes Vφ _S due to the operation of the vertical scanning circuit 276,
LSIT group 270-1 connected to row line 271-1
1,270-12, ..., 270-1n are selected,
The signals φ _D1 , φ _D2 , ... Output from the horizontal scanning circuit 277
..., by φ _Dn, horizontal selection transistor 273-1,
273-2, ..., 273-n are sequentially turned on, the LSITs 270-11, 270-12 ,.
The 0-1n signal is output from the video line 274.
Subsequently, this LSIT group is reset all at once when the signal φ _S1 during the blanking period t _BL becomes the high level Vφ _R. Then, when the signal φ _S2 becomes Vφ _S , the row line 2
71-2 connected to 71-2
-22, ..., 270-2n are selected, and the LSIT270- is selected by the horizontal scanning signals φ _D1 , φ _D2 , ..., φ _Dn .
The optical signals of 21,270-22, ..., 270-2n are sequentially read, and subsequently reset all together. In the same manner, the optical signal of each pixel is sequentially read out and the video current signal of one field is obtained.

In this embodiment, the anti-selection transistor groups 273-1 ', 273-2', ..., 273-n 'are provided because the drain of the non-selected LSIT is fixed to the potential of the power supply V _DD. However, even if there is no anti-selection transistor group, an optical signal can be stored in the gate. Therefore, as a modified example of this embodiment, a solid-state imaging device without an anti-selection transistor can be considered. A feature of this embodiment is that an LSIT other than the selected LSIT is used.
Has the advantage that no signal (anti-selection signal) is output.

[0090]

As described in detail above, according to the solid-state image pickup device of the present invention, a gate / drain selection method, a source / gate selection method, or a source / drain selection method can be arbitrarily selected as a signal reading method. Therefore, the degree of freedom in design is significantly improved, and the optimum selection method according to each requirement can be adopted.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a configuration of a conventional vertical SIT.

FIG. 2 is a lateral SIT applicable to the solid-state imaging device of the present invention.
It is sectional drawing which shows the structure of an example.

FIG. 3 is a diagram showing a first example of a solid-state image sensor that can configure a solid-state image sensor according to the present invention.

FIG. 4 is a diagram similarly showing a second example.

FIG. 5 is a diagram similarly showing a third example.

FIG. 6 is a diagram similarly showing a fourth example.

FIG. 7 is a diagram similarly showing a fifth example.

FIG. 8 is a diagram showing the sixth, seventh, and eighth examples, respectively.

FIG. 9 is a diagram similarly showing a ninth example.

FIG. 10 is also a diagram showing a tenth example.

FIG. 11 is a diagram similarly showing an eleventh example.

FIG. 12 is a diagram similarly showing a twelfth example.

FIG. 13 is a diagram similarly showing a thirteenth example.

FIG. 14 is a diagram for explaining the operation of the solid-state imaging device that constitutes the solid-state imaging device according to the present invention.

FIG. 15 is an equivalent circuit diagram of FIG.

FIG. 16 is a graph showing gate voltage vs. source / drain current characteristics with drain voltage as a parameter.

FIG. 17 is a graph showing characteristics of gate voltage vs. source / drain current.

FIG. 18 is a graph showing characteristics of accumulation time vs. source / drain current with incident light intensity as a parameter.

FIG. 19 is a circuit diagram showing a source follower type current-voltage conversion method.

FIG. 20 is a circuit diagram showing a source-grounded current-voltage conversion method.

FIG. 21 is a signal waveform diagram showing changes in gate, drain, and source voltages during accumulation, reading, and reset.

FIG. 22 is a graph showing an incident light amount-output voltage characteristic.

FIG. 23 is a graph showing a drain voltage-output voltage characteristic.

FIG. 24 is a signal waveform diagram for explaining an operation when the drain voltage is controlled and reset is performed.

FIG. 25 is a signal waveform diagram for explaining an operation in which the substrate voltage is controlled and reset is performed.

FIG. 26 is a graph showing an incident light intensity-output voltage characteristic with an accumulation time as a parameter.

FIG. 27 is a graph showing a gate voltage vs. output voltage characteristic with incident light intensity as a parameter.

FIG. 28 is a circuit diagram showing the configuration of the first embodiment of the solid-state imaging device of the present invention.

FIG. 29 is also a signal waveform diagram for explaining the operation.

FIG. 30 is a circuit diagram showing a second embodiment of the solid-state imaging device of the present invention.

FIG. 31 is likewise a signal waveform diagram for explaining the operation thereof.

FIG. 32 is a circuit diagram showing a third embodiment of the solid-state imaging device of the present invention.

FIG. 33 is likewise a signal waveform chart for explaining the operation.

FIG. 34 is a circuit diagram showing a fourth embodiment of the solid-state imaging device of the present invention.

FIG. 35 is also a circuit showing a fifth embodiment.

FIG. 36 is a signal waveform diagram for explaining the operation of the solid-state imaging device shown in FIG.

[Explanation of symbols]

11, 21, 31, 41, 51, 61, 65, 67, 6
9, 71, 75, 81, 91, 101 Solid-state imaging device 12, 22, 32, 42, 52, 82 Substrate 13, 23, 33, 43, 53, 83 Epitaxial layer 12, 24, 34, 44, 54, 84 Source region 15, 25, 35, 45, 55, 85 Drain region 16, 28, 38, 88 Gate insulating film 17, 29, 39, 49, 59, 89 Gate electrode 18, 26, 36, 46, 56, 86 Source Electrode 19, 27, 37, 47, 57, 87 Drain electrode 20, 30, 40, 50, 60, 62, 90 Separation region 48, 58 Gate region 66 Electrode 73 Gate region 111 Semiconductor substrate 112 Epitaxial layer 113 Drain region 114 Gate Region 115 Gate insulating film 116 Gate electrode 117 Source terminal 118 Drain terminal 119 Gate terminal 120 substrate terminal V _S source voltage V _G gate voltage V _D drain voltage V _SUB substrate voltage 250-11, 250-12, ..., 250-mn
Solid-state image sensor 251-1, 251-2, ..., 251-m row line 252-1, 252-2, ..., 252-n column line 253-1, 253-2 ,. -N; 253
-1 ', 253-2', ..., 253-n 'Column selection transistor 254 Video line 254' Ground line 255 Load resistance V _DD Video power supply 256 Vertical scanning circuit 257 Horizontal scanning circuit 258 Horizontal reset circuit 260-11 , 260-12, ..., 260-mn
Solid-state imaging device 261-1, 261-2, ..., 261-m row line 262-1, 262-2, ..., 262-n column line 263-1, 263-2 ,. -N; 263
, 263-n 'Column selection transistor 264 Video line 265 Load resistance 266 Vertical scanning circuit 267 Horizontal scanning circuit 270-11, 270-12, ..., 270-mn
Solid-state image sensor 271-1, 271-2, ..., 271-m row line 272-1, 272-2, ..., 272-n column line 273-1, 273-2 ,. -N; 273
-1 ', 273-2', ..., 273-n 'Column selection transistor 274 Video line 275 Ammeter 276 Vertical scanning circuit 277 Horizontal scanning circuit

Claims (5)

[Claims] 1. A source region and a drain made of a low resistance diffusion layer having a second conductivity type on a surface of a semiconductor layer having a second conductivity type formed on an insulator or a high resistance semiconductor substrate having a first conductivity type. Electrostatic induction in which a gate region for accumulating carriers generated by photoexcitation is provided between the source region and the drain region so that a source / drain current flows in parallel with the surface of the semiconductor layer. It has an array in which a large number of solid-state image pickup devices including transistors are arranged in a matrix, and horizontal and vertical scanning circuits for sequentially scanning each solid-state image pickup device of the array. At least two terminals of each line are commonly connected to each line, and the potential of each line is controlled by the horizontal and vertical scanning circuits. Te, the solid-state imaging apparatus characterized by comprising a scanning means for sequentially supplying the video line source-drain current corresponding to the photoelectric charge stored in the gate area of the solid-state imaging devices. 2. The scanning means connects a source terminal of each solid-state image pickup device to a constant potential, connects a gate and a drain terminal commonly for each line, and sets the potential of the gate and the drain terminal to the vertical direction. 2. The solid-state image pickup device according to claim 1, wherein the solid-state image pickup device is configured to sequentially control the solid-state image pickup devices by controlling the horizontal scanning circuit and the horizontal scanning circuit. 3. The scanning means connects the drain terminal of each solid-state imaging device to a constant potential, commonly connects the gate and source terminals for each line, and connects the potentials of these gate and source terminals to the vertical direction. 2. The solid-state image pickup device according to claim 1, wherein the solid-state image pickup device is configured to sequentially control the solid-state image pickup devices by controlling the horizontal scanning circuit and the horizontal scanning circuit. 4. The scanning means has a horizontal reset circuit, the gate and drain terminals are connected in common for each line, and the potentials of these gate and drain terminals are controlled by the vertical and horizontal scanning circuits, respectively. At the same time, the source terminal of each solid-state image pickup device is commonly connected to each line, the potential of each line is controlled by the horizontal reset circuit, and each solid-state image pickup device is sequentially selected to read out signals. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is reset immediately after the signal reading operation. 5. The solid-state image pickup device according to claim 3, wherein the scanning means includes means for making a non-selected source line equal to a ground potential.