JPH0621799A - Level conversion circuit - Google Patents

Abstract

(57) [Summary] (Modified) [Purpose] High-integration and high-speed operation can be easily realized by configuring the level conversion circuit with the minimum number of elements, and low power consumption and stable operation are possible. A level conversion circuit capable of outputting an ECL level is provided. In a level conversion circuit 3 used in a semiconductor integrated circuit in which a CMOS circuit 1 and an ECL circuit 2 are mixed, a cathode is connected to an input terminal IN1 and an anode is an output terminal OU.
A first diode D1 connected to T1, a transistor Q8 provided between the anode of the first diode D1 and the power supply Vcc and having a collector connected to the power supply Vcc, and an emitter of the transistor Q8 have their anodes. Connected and whose cathode is the first diode D1
Of the second diode D2 connected to the anode of the transistor Q8, and the base of the transistor Q8 is connected to the cathode of the first diode D1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level conversion circuit, and more particularly, in a semiconductor integrated circuit in which a CMOS circuit and an ECL circuit are mixed, the output of the CMOS circuit is input to the ECL circuit. The present invention relates to a level conversion circuit for a signal level used for the operation.

[0002]

2. Description of the Related Art In recent years, with the increase in speed and integration of computer systems and the like, various logic circuits have been constructed by mixing ECL circuits capable of high-speed operation and CMOS circuits featuring high integration and low power consumption. The number of cases is increasing. In such a conventional semiconductor device, since the amplitude of the signal level in the CMOS circuit is too larger than the amplitude of the signal level in the ECL circuit, the signal is directly transmitted from the CMOS circuit 1 to the ECL circuit 2. When the ECL circuit 2 is sent to operate, the transistor of the input stage in the ECL circuit is saturated, the delay time becomes long, and the base of the transistor of the input stage is delayed.
There is a problem that the reverse withstand voltage is applied between the emitters and the reliability of the ECL circuit decreases.

Therefore, it is necessary to convert the CMOS level in the signal level into the ECL level, and in that case, it is necessary to reduce the amplitude of the signal level of the CMOS level to match the ECL level. Conventionally, for example, a level conversion circuit as shown in FIG. 2 or FIG. 3 has been adopted. That is, referring to the circuit example of FIG. 2, the level conversion circuit 3 provided between the CMOS circuit 1 and the ECL circuit 2 is, for example, between the high potential power supply Vcc (GND) and the low potential power supply Vee. P-channel type MOS transistor MP1, N-channel type MOS transistors MN1 and MN2, bipolar transistor Q
6, Q7, resistors R5, R4, and diode Q8 form a circuit configuration as shown in the drawing, and the circuit configuration itself constitutes a known level conversion circuit. Further, the output terminal OU of the level conversion circuit 3
A level conversion circuit having a structure in which a plurality of diodes Q8, Q9 and a threshold diode SD1 are connected in series between T and the high potential power supply Vcc (GND) to form a clamp circuit 4 is used. .

An example of the circuit configuration of the conventional ECL circuit 2 is shown in FIG. 2, in which a pair of transistors Q1 is used.
, Q2 and a constant current source 6 composed of a differential amplifier circuit 5 composed of a pair of resistors R1 and R2 and a transistor Q3 connected to the common emitter of the differential amplifier circuit 5,
The reference input VBB in the differential amplifier circuit 5 is connected to the collector of the transistor Q2, and the output O
The emitter follower transistor Q4 forming the UT, the diode Q5 arranged between the output OUT and the high potential power supply Vcc (GND) are wired as shown in the drawing, and the ECL circuit is concerned. Is an example of a known ECL circuit, and the ECL circuit is not limited to the circuit configuration shown in FIG.
Of course, the L circuit can also be used.

As described above, the transistor Q1 forming the input stage of the ECL circuit 2 causes saturation or increase in delay when the level conversion circuit is not suitable. . So, for example,
The maximum signal level amplitude in the CMOS circuit 1 is 0V.
~ -5.2V is set, and the ECL circuit 2
The amplitude of the signal level at -1.3V
When the CMOS circuit 1 is designed to vary in the range of −0.8 V to −2.0 V, the number of diodes constituting the clamp circuit 4 or the size of the diodes is adjusted to adjust the CMOS circuit 1. It is possible to keep the signal level at the output within the amplitude range of the signal level of the ECL circuit.

However, the level conversion circuit shown in FIG. 2 can certainly convert the ECL circuit 2 to an appropriate signal level. However, the N channel type MOS transistor in the level conversion circuit 3 is converted. Since a large amount of current flows through the clamp circuit 4, the resistor R5, and the transistor Q7 when the MN2 is turned ON, unnecessary current is consumed in the level conversion circuit. , There was a problem.

On the other hand, in order to improve the power consumption, FIG.
There has been proposed a level conversion circuit 3 having a circuit configuration as shown in FIG. As shown in the figure, the level conversion circuit 3 of FIG. 3 includes, for example, a P-channel MOS transistor MP between a high potential power source Vcc (GND) and a low potential power source Vee.
1, N-channel type MOS transistors MN1 and MN2,
The MN3, the bipolar transistors Q6 and Q7, and the diode Q8 form a circuit configuration as shown in the figure. The difference from the level conversion circuit of FIG. 2 is that the clamp circuit 4 is deleted, The bipolar transistor Q
A diode Q8 is inserted between the emitter of 6 and the output section out.

The circuit configuration of the ECL circuit 2 in FIG. 3 is the same as the circuit configuration of the ECL circuit in FIG. 2, but the amplitude of the signal level in the ECL circuit 2 is -2.
It shows a case where it is designed to be varied in the range of -1.6V to -4.6V with 9V as the center. Therefore, the maximum amplitude range of the signal level of the CMOS circuit 1 is shown as follows.
The size and the number of the diodes Q8 are adjusted and converted so as to be in the range of -1.6V to -4.6V.

2 and 3, the low-potential power source is set to -5.2 V, and the load applied to the output terminal of the ECL circuit 2 is, for example, 50 Ω. Is assumed. The level conversion circuit 3 shown in FIG. 3 has the effect of preventing an increase in power consumption as shown in FIG. 2, but has a large number of elements and the like that compose the level conversion circuit 3. Therefore, the manufacturing process is complicated, the manufacturing cost is high, and further, since the number of each element is large, a layout area is required, which is an obstacle to high speed and high integration. Has become.

[0010]

SUMMARY OF THE INVENTION The object of the present invention is to improve the drawbacks of the prior art described above, and to configure a level conversion circuit with a minimum number of elements to facilitate high integration and high speed. Achievable, low power consumption and stable ECL
A level conversion circuit capable of outputting a level is provided.

[0011]

In order to achieve the above-mentioned object, the present invention adopts the technical constitution as described below. That is, in a semiconductor integrated circuit in which a CMOS circuit and an ECL circuit are mixed, it is a level conversion circuit used when inputting the output of the CMOS circuit to the ECL circuit, and outputs the output of the CMOS circuit. An input terminal for receiving, an output terminal connected to an input section of the ECL circuit, provided between the input terminal and the output terminal, a cathode thereof is connected to the input terminal, and an anode thereof is connected to the output terminal. A first diode, a transistor provided between the anode of the first diode and the power supply, the collector of which is connected to the power supply, and the emitter of the transistor, the anode of which is connected to the cathode of the transistor. Is the first
A second diode connected to the anode of the diode or a resistor connected to the emitter of the transistor and the anode of the first diode, and the base of the transistor is the first diode. It is a level conversion circuit connected to the cathode of the diode.

[0012]

Since the level conversion circuit according to the present invention employs the technical configuration as described above, the circuit configuration of the level conversion circuit is greatly simplified, and therefore the number of elements and the like used is remarkably reduced. Therefore, the high integration of the level conversion circuit can be easily realized, and at the same time, the delay time of the conversion time in the level conversion circuit is reduced due to the small number of elements, so that the conversion in the level conversion circuit is reduced. The processing speed is improved and the speed can be increased.

On the other hand, by the circuit configuration of the level conversion circuit according to the present invention, the size of the diodes or the number thereof are changed and adjusted, whereby the conversion level at the time of signal level conversion can be easily changed. It is possible to set the level conversion of a more appropriate signal level easily and quickly.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Specific examples of the level conversion circuit according to the present invention will be described in detail below with reference to the drawings. That is, FIG.
1 is a block diagram illustrating the configuration of a specific example of a level conversion circuit according to the present invention. In FIG.
In the semiconductor integrated circuit in which the CMOS circuit 1 and the ECL circuit 2 are mixed, the level conversion circuit 3 used when the output of the CMOS circuit 1 is input to the ECL circuit 2, Input terminal IN1 for receiving the output of 1 and output terminal O connected to the input portion IN2 of the ECL circuit 2
UT1, a first diode D1 provided between the input terminal IN1 and the output terminal OUT1 and having a cathode connected to the input terminal IN1 and an anode connected to the output terminal OUT1; And a transistor Q8 provided between the anode of the diode D1 and the power supply Vcc and having a collector connected to the power supply and the transistor Q8.
Of the second diode D2 whose cathode is connected to the anode of the first diode D1 or the emitter of the transistor Q8 and the anode of the first diode D1. A level conversion circuit is shown in which the base of the transistor Q8 is connected to the cathode of the first diode D1.

That is, the level conversion circuit 3 according to the present invention.
In this case, since it is composed of only bipolar transistors and diodes, and its circuit configuration is also designed simply, the number of elements used in the level conversion circuit, that is, the number of bipolar transistors and diodes, is reduced to the conventional level. The level can be significantly reduced as compared with the conversion circuit, and therefore the size of the level conversion circuit 3 itself can be reduced, so that high integration and high speed can be realized at the same time.

Further, in the level conversion circuit according to the present invention, the steady-state current becomes almost 0, and it becomes possible to flow the required current only at the intermediate point when the signal level changes.
The transistor Q8 used in the level conversion circuit according to the present invention is preferably an NPN type bipolar transistor, the collector of which is the high potential power source and the emitter of which is the anode side of the second diode D2. It is arranged so as to be connected.

The base of the transistor Q8 is the first
The diode D1 is wired so as to be connected to the cathode side. Further, it is preferable that the first diode D1 and the second diode D2 in the level conversion circuit 3 according to the present invention have different characteristics from each other. The number of diodes is
It is arbitrary and can be appropriately selected and determined in consideration of the signal levels of the CMOS circuit 1 and the ECL circuit 2.

Further, in the level conversion circuit according to the present invention, the second diode D2 or the resistor R arranged between the anode of the first diode D1 and the emitter of the transistor Q8 has the conversion level. Is determined, and any one can be selected according to the degree. In the level conversion circuit 3 of the present invention, the second diode D2 or the resistor R may be used depending on the case.
May not be used in some cases.

The operation of the level conversion circuit 3 according to the present invention will be described. Now, as the ECL circuit 2, a circuit having the same configuration as that shown in FIG. 3 is used, and the voltage of the high potential power supply Vcc is 0V.
Further, when the voltage of the low-potential power supply Vee is set to -5.2 V, the level conversion circuit 3 from the output side of the CMOS circuit 1
When the “L” level (≈−5.2 V) is input to the input terminal IN1 of the first diode D1, the first diode D1 is turned on, but the transistor Q8 and the second diode D2 are turned off. The input terminal IN2 of the ECL circuit 2, that is, the base of the transistor Q1 to the first diode D1.
Through the low potential power source of the CMOS circuit 1.

In this case, the base of the transistor Q1 of the ECL circuit 2 is Vee of the transistor Q1 rather than Vee.
_BE Converted to a potential level of about -4.6V, which is one step higher. In this case, since the transistor Q1 is turned off and the transistor Q4 is turned on, a voltage of about -0.9 V is output to the output terminal OUT of the ECL circuit 2 and becomes "H" level.

On the other hand, from the output side of the CMOS circuit 1 to the input terminal IN1 of the level conversion circuit 3, an "H" level (≈-
0.0V) is input, the transistor Q8 and the second diode D2 are turned on, and the first diode D1 is turned off, so that the current flows from the high potential power supply Vcc to the transistor Q8 and the second diode. It will flow to the input terminal IN2 of the ECL circuit 2, that is, the base of the transistor Q1 via D2.

Therefore, the base potential of the transistor Q1 is from the high potential power source Vcc to the transistor Q8 and the second potential.
The voltage is lowered by the voltage drop due to the diode D2, that is, about -1.6V. In this case, the E
The transistor Q1 in the CL circuit 2 is turned on,
A voltage of about -1.8 V is output to the output terminal OUT of the ECL circuit 2 and becomes "L" level.

[0023]

Since the present invention has the above-mentioned structure, a level conversion circuit from the CMOS level to the ECL level which can be integrated at high speed and has low power consumption can be easily formed. As a result, it can greatly contribute to the performance improvement in a computer system or the like.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a specific example of a level conversion circuit according to the present invention.

FIG. 2 is a block diagram showing an example of a conventional level conversion circuit.

FIG. 3 is a block diagram showing another example of a conventional level conversion circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... CMOS circuit 2 ... ECL circuit 3 ... Level conversion circuit Q8 ... Bipolar transistor D1 ... 1st diode D2 ... 2nd diode

Claims (4)

[Claims] 1. In a semiconductor integrated circuit in which a CMOS circuit and an ECL circuit are mixed, the output of the CMOS circuit is the E
A level conversion circuit used when inputting to a CL circuit, the input terminal receiving the output of the CMOS circuit, the EC
An output terminal connected to the input section of the L circuit, provided between the input terminal and the output terminal, the cathode thereof is connected to the input terminal, and the anode thereof is connected to the output terminal.
, A transistor provided between the anode of the first diode and the power supply, the collector of which is connected to the power supply, and the emitter of the transistor whose anode is connected to the cathode of the first diode. A second diode connected to the anode of the diode or the emitter of the transistor and a resistor connected to the anode of the first diode, and the base of the transistor is the first diode. Level conversion circuit characterized by being connected to the cathode of. 2. The level conversion circuit according to claim 1, wherein the transistor is an NPN bipolar transistor. 3. The level conversion circuit according to claim 1, wherein the power supply is a high-potential power supply common to the ECL circuit. 4. The level conversion circuit according to claim 1, wherein the first diode and the second diode have characteristics different from each other.