JPH0621987B2 - Micro program controller - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a microprogram control device capable of prefetching a microinstruction to be executed next during execution of a microinstruction.

(Prior Art) Conventionally, this type of micro program control device holds a micro instruction read from a control memory in a register, and an output from this register causes a control memory control circuit to control hardware. .

(Problems to be Solved by the Invention) In the conventional micro program control device described above, the control storage control circuit controls the hardware by the output from the register holding the micro instruction read from the control storage. It takes a long time until the control memory control circuit decodes the contents of this register until the hardware control is actually completed. Since this time determines the cycle of the control clock, there is a problem that the cycle of the control clock cannot be shortened to improve the performance.

(Means for Solving Problems) In order to solve the above-mentioned conventional problems, a micro program control device provided by the present invention is different from a first register for holding a micro instruction read from a control memory. ,
A second register is provided for holding the result of decoding the contents of the first register by the storage means for storing the information for decoding a part of the output of the first register.

In addition, a branch control circuit and an address control circuit which operate by a part of the output of the first register are provided, and the address and the address of the micro-instruction control memory which is controlled by the address control circuit and is held in the first register. It has two address registers for holding the addresses of the control memory of microinstructions held in the two registers.

When the microinstruction is held in the first register, this microinstruction is decoded according to the contents of the storage means, and the decoding result is held in the second register. At this time, at the same time, the branch control circuit or the address control circuit is operated by the output of the first register to give the address of the microinstruction to be executed next to the control memory, and the microinstruction read from this control memory is Held in register 1.

The address of the microinstruction to be executed next, which is held in the first register, is the address next to the address of the microinstruction currently being executed, the address generated by hardware, or the jump destination address by a subroutine call or the like. Conceivable. The present invention has an address stack for holding a return address to be returned after executing the jump destination micro instruction when the jump destination address is held in the first register. The return address is given to the control memory when the returned address and the address of the microinstruction control memory held in the first register match.

(Example) Hereinafter, one example of the present invention will be described with reference to the drawings.

FIG. 1 is a block circuit diagram of a micro program controller according to an embodiment of the present invention.

The control memory (CS) 1 stores a micro program, which is a set of micro instructions. In this embodiment, four CSs are provided in order to read instructions at the time of branch at high speed.
1 are arranged in parallel, and the selector 2 selects one of these four CS1 outputs. CS
R3 is a register that temporarily holds the microinstruction selected and output by the selector 2. The RAM decoder 4 stores information necessary for decoding a part of the output of the CSR 3. In a circuit usually called a decoder, one of the output signals is valid by one input pattern, but in the RAM decoder, the output signals can be validated as one combination corresponding to one input pattern. Therefore, complicated control is possible with a small amount of hardware. The DR 5 is a register that temporarily holds a part of the CSR 3 and a part of the RAM decoder 4. The control storage control circuit (CSC) 6 is a control circuit that actually controls the hardware by the output of DR5. The branch control circuit (BRC) 7 is a control circuit that receives information from the CSR 3 and the CSC 6 and performs control at the time of a branch instruction in the microprogram. The ECC 8 is a circuit that performs error correction and detection of the output of the CSR 3. CIA9 and CC
A11 is an address register that holds address information for CS1. The CCA11 provides the read address of CS1. The selectors 10 and 13 are registers that select this address information. Address stack 14
Is a register file that stacks a plurality of return addresses after executing a micro instruction. The adder 12 is C
This is a circuit that adds 1 to the address output from CA11. The address control circuit (ARC) 15 includes CIA9, C
It is a circuit for controlling CA 11, address stack 14, CEA 16, selectors 10 and 13. The CEA 16 is a register that holds an address, and the match circuit 17 is a circuit that detects a match between the CEA 16 and the CCA 11.

FIG. 2 is a block diagram of an information processing system to which the micro program controller of this embodiment is applied.

This information processing system includes a main memory device (MM) 20 and 1
It comprises one or more central processing units (CPU) 22, one or more channel control units (IOPs) 23, and a bus 21 connecting them. The microprogram controller of this embodiment is included in the CPU 22.

FIG. 3 is a block diagram showing the configuration of the CPU 22 of FIG.

The CPU 22 comprises a main memory access control unit (MBU) 30, an arithmetic control unit (EXU) 31, a prefetch control unit (PFU) 32, and a micro program control unit (CSU) 33. The micro program control device of this embodiment is It corresponds to CSU33. The MBU 30 has a buffer memory, an address translation buffer and an address translation means, and controls an access request to the MM 20. The EXU 31 has an arithmetic circuit and performs arithmetic control. PFU32 has instruction buffer storage,
Preemption control of instructions is performed.

FIG. 4 is a circuit diagram of the BRC 7 of FIG. BRC7
Is a decoder 40, a counter 41, a branch decision circuit 42, a flip-flop 43, AND gates 44, 46, 47 and an OR gate 4.
It is composed of 5, 48 and 49.

Next, the operation of this embodiment will be described with reference to the drawings.

FIGS. 5, 6, and 7 are flowcharts showing an example of the processing of the microprogram, and FIGS. 5 and 6 show respective time charts.

First, in the FPU 32 of the CPU 22, one instruction is fetched, the instruction is decoded, a start address for CS1 is generated and given to the selector 13. This address is set in the CIA 9 and given to the selector 10. Here, the hardware control signal (H
The output of the CIA 9 is selected by the selector 10 by WC), the output of the selector 10 is stored in the CCA 11, and then provided to the CS 1 as the output of the CCA 11.

For example, in FIG. 5, when the address of the microinstruction A0 is given to the CS1 as described above and the microinstruction A0 is read to the CSR3, the next time the microinstruction A1 is read.
Has been instructed to execute
It is decoded by C15. Next microinstruction A1 executed
Address is fetched from microinstruction A0 and given as ARG. The selector 10 selects the output of the ARG according to the instruction of the ARC 15. As a result, the address of the microinstruction A1 is given to CS1 and the microinstruction A1 is
3 is read. At this time, the micro instruction A0 is
Decoded by decoder 4 and output to DR5, CSC
It is executed under the control of 6. Similarly, microinstructions
When A1 is output to DR5 and executed, microinstruction A2 is read to CSR3.

Here, in the example of FIG. 5, since the microinstruction A2 is a conditional branch instruction, the ARC 15 instructs the selector 10 to select the output of the ARG, and the selector 2 sets the B instruction to B.
According to the result of the condition judgment in RC7, the microinstruction B0 or B1 to be executed next is read into CSR3.

FIG. 6 is an example showing a loop instruction for setting a counter, decrementing the value of the counter with processing, and executing the next microinstruction when the value of the counter becomes “0”.

In FIG. 6, when the value “5” is set as the ARG in the counter 41 of FIG. 4 by the microinstruction C1, the microinstruction D0 subtracts 1 from the counter 41 and determines the result value. Processing is performed. This process 5
When the value of the counter 41 becomes "0" by repeating the times, the flip-flop 43 is set, and when the microinstruction D0 is executed for the sixth time, the branch condition is satisfied and the instruction jumps to the microinstruction D1.

FIG. 7 shows a case in which the microinstruction E0 → E1 → E2 → E3 → E4 is followed by the microinstructions F1 → F2 → F3 → F4 of another microprogram and then the microinstruction E5.

This is because the microinstruction E3 sets the address of the microinstruction F4 in CEA16, and the microinstruction E4 adds 1 to the address of the microinstruction E4 held in CIA9.
Add the address (the address of microinstruction E5) on the address stack 14, then add microinstruction F1
It is executed by jumping to. Micro instruction F1
After executing → F2 → F3 → F4, the output from the address stack 14 is selected by the selector 10 and the microinstruction E5 is executed. When only microinstruction F1 is executed after execution of microinstruction E4 and then microinstruction E5 is executed, jump to microinstruction F1 at microinstruction E4 and add 1 to address of microinstruction E4 to CIA 9 The address (the address of microinstruction E5) added with is stored, and then the output of CIA9 is stored in selector 10
It can be realized by selecting.

Further, the input to the counter 41 may be configured so that not only the output from the CSR3 but also the output from the EXU31 is selected and set.

All of them hold the output of CSR3 in DR5,
At the same time as executing the microinstruction held in DR5,
CS by controlling the address of the next microinstruction to be executed
By holding a microinstruction to be executed next in R3, processing can be performed without degrading performance.

(Effect of the Invention) As described above, the present invention has two stages of the first register for holding the microinstruction read from the control memory and the second register for holding the result of decoding the microinstruction. By using a register, the branch control circuit and the address control circuit operate by the output from the first register, and the branch control circuit after the conditional branch by the counter and the repeated execution is provided in the branch control circuit, it is simple. It is possible to execute the determination of a branch condition, which has a significant performance degradation, without delay by only having two stages of registers. Therefore,
According to the present invention, there is an effect that a control clock can be speeded up by using a two-stage register.

[Brief description of drawings]

FIG. 1 is a block circuit diagram of a micro program controller according to an embodiment of the present invention, and FIG. 2 is a block diagram of an information processing system to which the micro program controller according to the present embodiment is applied.
FIG. 3 is a block diagram showing the configuration of the central processing unit of FIG. 2, FIG. 4 is a circuit diagram of the branch control circuit of FIG. 1, FIG.
6 and 7 are flowcharts showing an example of the processing of the microprogram. 1 ... Control memory (CS), 2 ... selector, 3 ... CS
R, 4 ... RAM decoder, 5 ... DR, 6 ... Control storage control circuit (CSC), 7 ... Branch control circuit (BR
C), 8 ... ECC, 9 ... CIA, 10, 13 ... Selector, 11 ... CCA, 12 ... Adder, 14 ... Address stack, 15 ... Address control circuit (ARC), 16 ... CE
A, 17 ... Matching circuit, 20 ... Main memory (MM), 21 ...
... bus, 22 ... Central processing unit (CPU), 23 ... Channel control unit (IOP), 30 ... Main memory access control unit (MBU), 31 ... Operation control unit (EXU), 32 ... Preemption control Unit (PFU), 33 ... Micro program control unit (CSU), 40 ... Decoder, 41 ... Counter, 42 ...
Branch decision circuit, 43 ... Flip-flop, 44, 46, 47 ...
… AND gate, 45,48,49 …… OR gate.

Claims (3)

[Claims] 1. A first register for holding a microinstruction read from a control memory, and a memory for storing information for decoding a command indicated by a part of the microinstruction held in the first register. Means, a second register for holding the decoding result read from the storage means, a control storage control circuit for controlling hardware based on the output of the second register, an output of the first register, An address control circuit that gives an address of a microinstruction to be read from the control memory in accordance with an instruction from the branch control circuit or the control memory control circuit, and counter control based on the output of the first register, determination of a branch condition, and branching. A branch control circuit for controlling, a first address register for holding the address of the control memory of the microinstruction currently being executed, and A second address register holding an address obtained by adding 1 to the address held in the first address register, a hardware-generated address, or a jump destination address indicated by a part of the output of the first address register; An address stack for holding a return address to be returned after jumping to the jump destination address held in the second address register and executing the jump destination micro instruction. 2. An address equal to a return address held in the address stack when a jump destination address indicated by a part of the output of the first address register is held in the second address register. The microprogram controller according to claim 1, wherein the return address is provided to the control memory when is stored in the first address register. 3. When an address obtained by adding 1 to the address held in the first address register is held in the second address register, the address held in the first address register becomes After reading the corresponding microinstruction from the control memory and executing it, the second
3. The microprogram controller according to claim 1, wherein the microinstruction corresponding to the address held in the address register is read from the control memory and executed.