JPH0622226A - Defect correction device for solid-state imge pickup element - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a defect correction device for a solid-state image sensor that can deal with a defect change due to electrostatic breakdown or change over time and that does not require a distribution form of a pair of solid-state image sensor and defect data. . A CCD output (a) of the solid-state image pickup device 1 is delayed by a 1-bit delay circuit 5 for a period corresponding to one pixel pitch, and a CCD output (l) after the delay is delayed by a CCD output (i) before the delay. Is subtracted by a subtractor 7, a defective pixel is detected based on the subtraction output (m), and the detection outputs (p) and (q) are detected.
Is counted by the address counter 16 and converted by the address conversion circuit 17 to obtain address data, which is stored and held in the RAM 18. At the time of normal imaging, the defect correction pulse is generated by the correction pulse generation circuit 19 based on this defect address data to perform defect correction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a defect correction device for a solid-state image pickup device.

[0002]

2. Description of the Related Art In a solid-state image pickup device formed of a semiconductor such as CCD, a defective pixel whose sensitivity is lowered due to a local crystal defect of the semiconductor may occur. In such a case,
It is known that the image quality is deteriorated due to the defective pixel. In order to correct the image quality deterioration due to this defective pixel by signal processing, conventionally, the defect data of the defective pixel included in the solid-state imaging device is manufactured in the all-white or all-black imaging state. Detected in a semiconductor factory and stored in ROM in advance, specify a defective pixel based on the ROM data during normal image pickup, and replace the image pickup output of the defective pixel with the image pickup output one pixel before, for example. The defect was corrected by.

[0003]

However, in the conventional defect correcting apparatus, the defect correction is performed by using the defect data stored in the ROM at the manufacturing stage of the solid-state image pickup device, so that the local crystal of the semiconductor is not corrected. Although it is possible to deal with pixel defects due to defects, it is not possible to deal with electrostatic damage when the solid-state image sensor is built into the video camera and defect change due to aging after mounting on the video camera, and solid-state imaging There has been a problem that a distribution form in which an element and defect data are paired is indispensable. Therefore, an object of the present invention is to provide a defect correction apparatus for a solid-state image sensor that can cope with a change in defects due to electrostatic breakdown or a change over time and that does not require a distribution mode in which the solid-state image sensor and defect data are paired. And

[0004]

A defect correction apparatus for a solid-state image pickup device according to the present invention includes delay means for delaying the image pickup output of the solid-state image pickup device by a period corresponding to one pixel pitch, and input and output of the delay means. Subtraction means for performing a subtraction with the subtraction means, defect detection means for detecting defective pixels based on the subtraction output of the subtraction means, and storage means for storing and holding defect data regarding the defective pixels detected by the defect detection means,
A correction unit that corrects the imaging output of the defective pixel based on the defect data stored and held in the storage unit is provided.

[0005]

The image pickup output of the solid-state image pickup device is delayed by a period corresponding to one pixel pitch, the image pickup output after the delay is subtracted from the image pickup output before the delay, and the pixel defect (point Defect) is detected. In the case of a point defect, the subtraction output has a positive and negative waveform in units of 2 bits (pixels) in the case of a white point defect, and an opposite waveform in the case of a black point defect. Defective pixels of white dots and black dots are detected from this waveform, and these are stored and held in a RAM or the like as address data. At the time of normal image pickup, defect correction is performed based on address data stored and held in the RAM or the like to improve image quality deterioration due to pixel defects.

[0006]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, the solid-state imaging device according to the present invention uses, for example, a monochrome CCD imaging device 1 as a solid-state imaging device. The CCD image pickup device 1 adopts, for example, an interline transfer system as a charge transfer system. C
The image pickup output (CCD output) of the CD image pickup device 1 includes a reset section, a precharge section, and a data section.
It is supplied to the S (correlated double sampling) circuit 2 to reduce reset noise and the like.

The CDS circuit 2 samples / holds the precharge portion of the CCD output and delays it by a period corresponding to one pixel pitch S / H (sample / hold)
Sample the circuits 21 to 23 and the data part of the CCD output
S / H to hold and synchronize this with precharge section
And circuits 24 and 25. S / H circuits 21, 2
Reference numerals 3 and 25 perform the sampling operation by the sampling pulse SHP, and S / H circuits 22 and 24 perform the sampling operation by the sampling pulse SHD. Since the same noise component is superimposed on the synchronized precharge section and data section, the S / H outputs of the S / H circuits 23 and 25 are output by the AGC (automatic gain control) circuit 3. The noise component is removed by the subtraction processing, and only the signal component is derived as the imaging output (CDS output).

Each S / H output of the S / H circuits 23 and 25 is set to 2
The same subtraction output as the CDS output can also be obtained by the subtractor 4 that is an input. The respective S / H outputs of the S / H circuits 23 and 25 are further input to the subtractor 6 via the 1-bit delay circuit 5. That is, the S / H output of the S / H circuit 23 is S
Becomes the subtraction input of the subtractor 6 via the / H circuits 51 and 52,
The S / H output of the S / H circuit 25 becomes the subtracted input of the subtractor 6 via the S / H circuits 53 and 54. As a result, as the subtraction output of the subtractor 6, an imaging output delayed by 1 bit, that is, a period corresponding to one pixel pitch, is derived from the subtraction output of the subtractor 4, and the pixel information of adjacent pixels in the horizontal direction is synchronized. Is done.

The subtraction output of the subtractor 4 becomes the subtracted input of the subtractor 7, and the subtraction output of the subtractor 6 becomes the subtraction input of the subtractor 7. That is, the subtractor 7 performs the subtraction process between the image pickup outputs of the two pixels that are adjacent in the horizontal direction and are synchronized with each other. The subtracted output of the subtractor 7 is Schmitt circuits 8 and 9 having positive and negative detection levels Va and Vb.
Is supplied to. The Schmitt circuits 8 and 9 function as a level comparison circuit, generate a detection output when the subtraction output of the subtractor 7 exceeds the positive and negative detection levels Va and Vb, and supply it to the latch circuits 10 and 11. The positive and negative detection levels Va and Vb are variable by adjusting the variable resistors VR1 and VR2.

The latch circuits 10 and 11 latch the detection outputs of the Schmitt circuits 8 and 9 for a period corresponding to one pixel pitch. Each output of the latch circuits 10 and 11 is a NAN.
It becomes one input of each of the D circuits 12 and 13. Further, the respective inputs of the latch circuits 10 and 11 become the respective other inputs of the NAND circuits 13 and 12. The outputs of the NAND circuits 12 and 13 are inverted by the inverters 14 and 15 and supplied to the address counter 16 as defect information.

The address counter 16 performs a counting operation in synchronization with the horizontal scanning of the CCD image pickup device 1, and supplies the count value at the time when the defect information is supplied from the inverter 14 or 15 to the address conversion circuit 17. The address conversion circuit 17 converts the count value supplied from the address counter 16 into address data indicating the position of the defective pixel. This address data is stored and held in the RAM 18. The address indicating the position of the defective pixel may be either an absolute address or a relative address.

The address data relating to the defective pixel stored and held in the RAM 18 is used for defect correction during normal image pickup. That is, in the correction pulse generation circuit 19, the defective pixel is specified based on the address data stored in the RAM 18, and the defect correction pulse is generated in each field at a timing corresponding to the defective pixel. This defect correction pulse is a sampling pulse SHP, SH.
It is supplied to the sampling pulse generation circuit 20 for generating D. When the defect correction pulse is supplied, the sampling pulse generation circuit 20 stops the generation of the sampling pulse SHP one pixel before the defective pixel. As a result, the CCD output (imaging output) for the defective pixel is changed to the C one pixel before.
Defect correction is performed by pre-interpolation that replaces the CD output.

Next, defect detection and defect correction in the defect correction device having the above-mentioned structure will be described with reference to the timing waveform charts of FIGS. Note that the waveforms (a) to (q) in FIGS. 2 and 3 are the respective portions (a) to (q) in FIG.
Represents the waveform of. First, the operation at the time of defect detection will be described. The CCD output (a) is composed of a reset section, a precharge section and a data section, and the precharge section is the S / H circuit 21 as shown in FIG. Is sampled / held by the sampling pulse SHP (b), while the data section is sampled / held by the sampling pulse SHD (c) in the S / H circuit 24.

The S / H output (d) of the S / H circuit 21 is S
The S / H circuit 22 samples / holds by the sampling pulse SHD (c), and the S / H output (e) is further sampled by the S / H circuit 23 in the sampling pulse SHP (b).
Sampled / held by On the other hand, the S / H output (g) of the S / H circuit 24 is sampled / held by the S / H circuit 25 by the sampling pulse SHP (b). As a result, the precharge part and the data part of the CCD output (a) are synchronized. Then, in the subtractor 4,
From the S / H output (h) of the S / H circuit 25 to the S / H circuit 23
Is subtracted from the S / H output (f) of
As the subtraction output (i) of
D output is obtained.

The S / H output of the S / H circuit 23 (f)
Is sampled / held by the sampling pulse SHD (c) in the S / H circuit 51, and its S / H output is further sampled / held by the sampling pulse SHP (b) in the S / H circuit 52. On the other hand, S / H circuit 2
The S / H output (h) of 5 is sampled / held by the sampling pulse SHD (c) in the S / H circuit 53,
The S / H output is further sampled / held in the S / H circuit 54 by the sampling pulse SHP (b). Then, in the subtractor 6, S / H of the S / H circuit 54
By subtracting the S / H output (j) of the S / H circuit 52 from the H output (k), the subtraction output (l) of the subtractor 6 is 1 with respect to the subtraction output (i) of the subtractor 4. A CCD output delayed by a period corresponding to the pixel pitch can be obtained.

Next, in the subtractor 7, the subtraction output (l) of the subtractor 6 is subtracted from the subtraction output (i) of the subtractor 4,
That is, by taking the difference between the signals of two pixels that are adjacent in the horizontal direction, the subtraction output (m) of the subtractor 7 is positive in units of 2 bits (pixels) when a pixel has a white spot defect. When there is a black spot defect, negative and positive differential waveforms are obtained. Then, in the Schmitt circuits 8 and 9, the differential waveform output (m) is set to a certain detection level V
By triggering with a and Vb, defect pulses (n) and (o) are obtained.

These defect pulses (n) and (o) are passed through the latch circuits 10 and 11, the NAND circuits 12 and 13 and the inverters 14 and 15, and thereby the white dot defect pulse (p) or the black dot defect pulse (q). Becomes In the address counter 16, the position of the defective pixel is specified by address-counting the white spot defect pulse (p) or the black spot defect pulse (q). Then, the count value of the address counter 16 is converted into address data by the address conversion circuit 17 and stored in the RAM 18.

Next, to explain the operation at the time of defect correction, first, in the correction pulse generation circuit 19, the RAM 18 is used.
A defect correction pulse is generated based on the address data stored and stored in the sampling pulse generation circuit 20. As a result, the sampling pulse SHP one pixel before the defective pixel is blanked. As a result, the CCD output (imaging output) of the defective pixel is replaced with the CCD output of the previous pixel, and the defect correction is performed.

In the above embodiment, the case where the present invention is applied to the solid-state image pickup device using the monochrome CCD image pickup device as the solid-state image pickup device is explained.
A solid-state image pickup device using a CD image pickup element has a color separation S / H.
After that, the same processing as in the case of black and white is performed on the signal after color separation, so that the same can be realized. However, when the color filter is, for example, the complementary color checker system, the color coding is so-called horizontal 2-repetition. Therefore, in the delay circuit 5, it is necessary to delay the CCD output by a period corresponding to twice the pixel pitch.

Further, in the above embodiment, the 1-bit delay circuit 5 is constructed by using the S / H circuit, but it is not limited to the S / H circuit configuration, and the point is that it corresponds to one pixel pitch. CC for the period (double that for color)
Any configuration that can delay the D output may be used. further,
In the above embodiment, the defect correction is performed by the pre-interpolation in which the CCD output of the defective pixel is replaced by the CCD output of the previous pixel using the S / H circuit, but the adaptive interpolation using the digital signal processing is performed. In the system, the CCD output for the defective pixel is replaced with the CC output for the pixels before and after it.
It is also possible to perform defect correction using average value interpolation in which the average value of D output is replaced.

[0021]

As described above, according to the present invention,
The image output of the solid-state image sensor is delayed by a period corresponding to one pixel pitch, the image output after the delay is subtracted from the image output before the delay, the defective pixel is detected based on the subtracted output, and the defective data is stored. Since it is held and defect correction is performed based on this defect data during normal imaging, defect detection can be performed in real time even under normal imaging conditions, and it also supports defect changes due to electrostatic breakdown and aging. In addition, it is possible to obtain the effect that the distribution form in which the solid-state image sensor and the defect data are paired is unnecessary.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a timing waveform diagram (No. 1) for explaining the operation of defect detection and defect correction.

FIG. 3 is a timing waveform chart (No. 2) for explaining the operation of defect detection and defect correction.

[Explanation of symbols]

1 CCD image sensor 2 CDS (correlated double sampling) circuit 3 AGC (automatic gain control) circuit 4, 6, 7 subtractor 5 1-bit delay circuit 16 address counter 17 address conversion circuit 18 RAM 19 correction pulse generation circuit 20 sampling pulse Generation circuit 21-25, 51-54 S / H (sample / hold) circuit

Claims (6)

[Claims] 1. A delay means for delaying an image pickup output of a solid-state image pickup device by a period corresponding to one pixel pitch, a subtraction means for subtracting an input of the delay means and an output thereof, and a subtraction output of the subtraction means. Defect detecting means for detecting a defective pixel based on, a storage means for storing and holding the defect data regarding the defective pixel detected by the defect detecting means, for the defective pixel based on the defect data stored and held in the storage means A defect correction apparatus for a solid-state image pickup device, comprising: a correction unit that corrects an image pickup output. 2. The defect correction apparatus for a solid-state image pickup device according to claim 1, wherein the delay means is composed of a sample / hold circuit for sampling / holding the image pickup output. 3. The defect detection means has a pair of level comparison circuits for comparing the level of the subtraction output with two positive and negative detection levels, and the two detection levels are variable. Item 1. A defect correction device for a solid-state image sensor according to Item 1. 4. The defect detection means includes a pair of latch circuits for latching each comparison output of the pair of level comparison circuits for a period corresponding to one pixel pitch, one input and the other of the pair of latch circuits. 4. A pair of logical product circuits that take a logical product with an output, and the defect data is obtained based on each output of the pair of logical product circuits.
A defect correction device for a solid-state image sensor according to claim 1. 5. The defect correction apparatus for a solid-state image pickup device according to claim 1, further comprising an address conversion unit that converts the defect data into address data and stores the address data in the storage unit. 6. The pre-interpolation for replacing the image pickup output for the defective pixel with the image pickup output one pixel before,
2. The defect correction apparatus for a solid-state image pickup device according to claim 1, wherein correction is performed by average value interpolation in which an image pickup output of the defective pixel is replaced with an average value of image pickup outputs of pixels before and after the defective pixel.