JPH06224302A - Wiring mask manufacturing equipment considering wiring delay - Google Patents

Abstract

PURPOSE:To embody optimum line width and space at every wiring part in the case of determining mask layout. CONSTITUTION:A mask layout means 2 draws out mask layout according to figures inputted from an information inputting means 1, and an optimum line and space calculating means 3 detects data of wiring parts from the mask layout pattern, and finds optimum line and space which minimize RC delay from the resistance value and the capacitance value at each wiring part. A layout data changing means 4 changes mask layout so that the line and space at each wiring part may be the optimum line and space calculated respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for manufacturing a mask pattern used in a photolithography process of a semiconductor integrated circuit device, and more particularly to a wiring mask manufacturing apparatus for manufacturing a wiring layout pattern of a wiring layer.

[0002]

2. Description of the Related Art In a manufacturing process of a semiconductor integrated circuit device (hereinafter referred to as an LSI), a layout editor is used to create a layout of patterns such as wiring and diffusion layers. This is realized as software on a computer. In the layout editor,
A mask pattern of the LSI is created by inputting figures of each layer from an external input device such as a mouse or a keyboard. There is a graphic restriction called a design rule such as how much wiring line width and space should be set for each layer. This is mainly determined by constraints such as the minimum line width that can be patterned in the manufacturing technology. The computer also automatically checks whether the created mask layout complies with this design rule.

When the mask layout of the wiring layer is created, the delay due to the product RC of the resistance value R and the capacitance C of the LSI is
Is important in determining the operating speed of. The product of R and C is RC
It is called a delay, and when the wiring pitch is determined, the wiring width that minimizes RC can be determined. The relationship between RC and wiring width is, for example, the magazine "solid state technology / Japan version / Ja
nuary 1992 "in FIG.

If an LSI is designed according to a design rule, the wiring width and space of the LSI are designed to be uniform according to the design rule.
It has been conventionally performed to calculate the RC delay from the wiring capacitance and resistance value of the wiring layout pattern. As such a calculation method, for example, JP-A-1
-130280 and Japanese Patent Laid-Open No. 2-239373.

Given the performance target of the entire LSI, the design rules for the multilayer metal wiring are determined from the following viewpoints. (A) The pitch of the wiring metal is selected to suit the cell size and the integration density. (B) The line width and length of the wiring metal and the thickness of the insulating film between the wiring layers are determined so as to guarantee the performance of the LSI by referring to the calculation result based on the delay wiring model. (C) What kind of process is selected depends on the ease of manufacture. (D) The size of the wiring, the thickness of the interlayer insulating film, the size of the via hole, etc. are determined based on the materials used and the consistency and reliability of the process.

[0006]

RC delay is taken into consideration when determining the line width and space width of a wiring, and the capacitance is considered as a fringe capacitance and a coupling capacitance with an adjacent wiring. Calculated under the worst circumstances. However, in an actual circuit, since the conditions vary depending on the wiring section, the line width and space that are fixed in the LSI as a whole may be optimum in some parts, but not optimum in other parts. Therefore, the present invention has an object to realize a circuit having a small wiring delay even with the same chip size by realizing an optimum line width and space for each wiring portion in a mask layout on a mask layout. is there.

[0007]

As shown in FIG. 1, a wiring mask manufacturing apparatus of the present invention is provided with a mask layout means 2 for creating a mask layout according to a figure input from the information input means 1. Optimal line space calculating means 3 for detecting data in the wiring portion from the mask layout pattern and obtaining an optimum line space for minimizing RC delay from the resistance value and the capacitance value in each wiring portion.
And a layout data changing means 4 for changing the mask layout so that the line space of each wiring portion becomes the calculated optimum line space. Reference numeral 5 is an information output means for outputting the changed mask layout, and 6 is a data storage means for storing a database or the like.

In a preferred mode, the optimum line space calculation means 3 has three points of a minimum line width Lmin that can be manufactured, a maximum line width Lmax corresponding to the minimum space, and a line width in the middle between them for a given wiring pitch. Calculate the product RC of the resistance value and the capacitance value with. If the RC is the minimum when the minimum line width or the maximum line width, the minimum line width or the maximum line width is adopted, and the RC of the middle line width is the minimum. If so, RC is calculated for a plurality of line widths between the minimum line width Lmin and the maximum line width Lmax, and the line width is determined so that the line width with the minimum RC is adopted. In a further preferred aspect, the step shape of the wiring layer and the simulation result of the capacitance thereof are provided as a database,
The optimum line / space calculation means 3 retrieves the corresponding step shape from the database and reads the capacitance value,
Calculate RC.

[0009]

The operation of the present invention will be described with reference to FIGS. The mask layout means 2 includes a layout editor used in normal layout work, a device for automatically generating a layout pattern, and the like. Once the layout pattern is created, the optimum line
In the space calculation means 3, first, the data of the wiring portion is searched from the layout pattern and the wiring pattern is obtained as a two-dimensional pattern. A resistance value R is obtained for each of the wiring parts divided into a plurality based on the retrieved data of the wiring part.
And the capacitance value C is calculated, and the RC delay is calculated. At this time, the process parameters such as the resistivity of the wiring, the relative dielectric constant of the interlayer insulating film, and the film thickness of the interlayer insulating film are stored in the data storage unit 6 as a database, and the data storage unit 6 is stored.
It is read from and used for calculation. Optimal line width and space are sought to minimize RC delay for a given pitch. The layout data changing means 4 makes the calculated RC delay minimum line space.
The layout data is changed and output from the information output means 5.

[0010]

EXAMPLE As shown in FIG. 3 as an example, a first-layer metal wiring 14 and a third-layer metal wiring 18 are formed in parallel with each other so as to extend in the in-plane direction of the paper surface. The second-layer metal wirings 15, 16 and 17 are sandwiched between the metal wirings 14 and 18, with the interlayer insulating film 19 of a silicon oxide film interposed between the metal wirings 14 and 18, and between the metal wirings 18 and 18. Metal wiring 1 through the interlayer insulating film 20 of silicon oxide film
It is assumed that they are formed in a direction orthogonal to 4, 18.
Focusing on the second layer metal wiring 16, the resistance R of the wiring 16 is derived by calculation from the thickness, width and resistivity of the wiring layer. Capacitance C is the capacity of the second layer wiring (wiring 1
6 between the wiring 15 and between the wiring 16 and the wiring 17), and the capacitance existing between the wiring 14 of the first layer via the interlayer insulating film 19 and the third layer via the interlayer insulating film 20. It is the sum of the capacitance existing between the wiring 18 and the wiring. Since it is important to consider the fringe capacitance in order to calculate the capacitance between wirings, it is possible to obtain the capacitance using, for example, a device simulator.

A method of deriving an optimum line space will be described. The optimum line space is to optimize the line width L and the space S to minimize the RC delay when the pitch P is given as shown in FIG. 3, thereby obtaining a wiring capable of operating at higher speed. It is a thing. There is a minimum line width Lmin and a minimum space Smin that can be patterned in terms of manufacturing technology. These tend to be miniaturized by improving manufacturing technology and introducing the latest manufacturing equipment. If the pitch P is set to a pitch consisting of Lmin and Smin, the line space cannot be changed.

Unless otherwise, that is, when L and S are both minimum values, first, the data of the wiring portion as shown in FIG. 3 is derived from the mask layout. A line width L and a space S are obtained from the mask layout data. Since the film thickness of the wiring and the film thickness of the interlayer insulating film between the wiring layers are determined by the manufacturing method, a cross-sectional view of the wiring can be easily derived from these data.

Next, paying attention to a certain wiring, for example, the wiring 16 in FIG. 3, the wiring resistance R and the wiring capacitance C connected to the wiring.
To calculate. In order to derive the minimum RC, RCs at Lmin and Smin (L becomes Lmax at this time) are calculated, and R at the median value (Lmin + Lmax) / 2 is calculated.
Calculate C. Compare the RC of these 3 points, Lmin or Lm
If RC at ax is minimum, then Lmin or Lm at that time
Use ax as the line width. If (Lmin + Lmax) /
If RC at 2 is minimized, R between Lmin and Lmax
Since it has a minimum value of C, RC is calculated for a plurality of line widths between Lmin and Lmax, and L giving the minimum RC is adopted as the line width.

Another method for deriving the optimum line space is to create a database having the optimum line width as data in accordance with the conditions such as the film thickness of the wiring and the film thickness of the interlayer insulating film, and use that database. This is a method of reading the optimum line space. When the optimum line width and space are determined in a wiring section, the wiring section automatically converts the layout data into the optimum values. Similarly, for the other wiring parts, the optimum line width and space are determined, and the layout data is converted to the optimum value.

In the model of FIG. 3, the wiring layer is flat, but since the actual interlayer insulating film is not flat, a step is formed in the wiring layer. When this step difference is taken into consideration, a simulation result of the step shape of the wiring layer and its capacitance is held as a database, the corresponding step shape is searched from the database, the capacitance value is read, and RC is calculated. do it.

[0016]

According to the present invention, in each wiring portion of the LSI, the R
Layout data lines to minimize C delay
Since the space is changed, the line width and space are optimized for each wiring part, and LSIs with the same cell size
If so, a higher-speed circuit can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing the present invention.

FIG. 2 is a flowchart showing an example of operation.

FIG. 3 is a cross-sectional view showing an example of wiring.

[Explanation of symbols]

 2 mask layout means 3 optimum line / space calculation means 4 layout data change means 6 data storage means

Claims (3)

[Claims] 1. A mask layout means for creating a mask layout according to a graphic input from an information input means, data of a wiring portion is detected from the created mask layout pattern, and resistance value and capacitance value of each wiring portion are detected. An optimum line space calculating means for obtaining an optimum line space that minimizes RC delay, and a layout for changing the mask layout so that the line space of each wiring portion becomes the calculated optimum line space. A wiring mask manufacturing apparatus provided with data changing means. 2. The minimum line width Lmi which can be manufactured is given line pitch calculation means for a given wiring pitch.
n, the maximum line width Lmax corresponding to the minimum space, and the product RC of the resistance value and the capacitance value are calculated at three points of the intermediate line width, and if RC is the minimum when the minimum line width or the maximum line width, then If the minimum line width or the maximum line width is adopted and the intermediate line width RC is minimum, then the minimum line width Lmin
R for multiple line widths between the line width and the maximum line width Lmax
The wiring mask manufacturing apparatus according to claim 1, wherein C is calculated and a line width that minimizes RC is adopted. 3. A database containing simulation results of the step shape of a wiring layer and its capacitance,
3. The wiring mask manufacturing apparatus according to claim 1, wherein the space calculation means retrieves the corresponding step shape from the database, reads the capacitance value thereof, and calculates RC.