JPH06224519A - Semiconductor light emitting device and method of manufacturing the same - Google Patents

Abstract

(57) [Summary] [Object] To provide a semiconductor light emitting device such as a semiconductor laser having a semi-insulating high resistance layer embedded structure, which is important as a light source for optical transmission, and a method for manufacturing the same. A structure in which a semi-insulating high-resistance crystal layer serves as a current blocking layer 7 and a part of the conductive semiconductor layer serving as a conductive cladding layer 4 and an electrode layer 5 expands toward the upper part of the device. In the provided semiconductor light emitting device, the interface between the portion of the conductive type semiconductor layer forming the mesa stripe 11 and the current blocking layer 7 is not exposed on the upper surface of the element,
The p-type InP clad layer 4 and the p-type I formed in the groove 12
It is covered with a part of the conductivity type semiconductor layer composed of the nGaAs electrode layer 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor light emitting device such as a semiconductor laser having a semi-insulating high resistance layer embedded structure, which is important as a light source for optical transmission, and a method for manufacturing the same.

[0002]

2. Description of the Related Art A semiconductor laser with a high resistance layer embedded structure having a semi-insulating InP crystal as a buried layer has a small element capacitance and enables high-speed modulation. It is regarded as an important light source for automobiles. For high speed operation of this device,
It is necessary to reduce the element resistance.

FIG. 8 shows a cross-sectional view of the structure of a conventional semiconductor laser with a semi-insulating high resistance layer embedded structure (reference: T. Sasaki et al., Journal of Light Wave Technology, vol. 8 (1990) 1343-134).
9). In FIG. 8, 01 is MQW, 02 is n-InG
aAsP, 03 is p-InP, 04 is p-InP, 05
Is p ⁺ -InGaAsP, 06 is Fe-doped SI-In
P, 07 is n-InP, 08 is n-InP substrate, 09 is SiO ₂ , 010 is Ti / Au, 011 is Ti / Pt /
The Au is illustrated. In this device, a semi-insulating high resistance layer made of Fe-doped InP crystal 06 and an n-type I are provided in the current blocking region.
A conductive block layer made of nP crystal 07 is arranged, and a p-type clad layer 04 and a p-type InGaAsP electrode layer 05 are formed on the entire surface of the element including the upper surface of the current blocking region. This reduces the resistance due to the p-type semiconductor layer inside the element, reduces the series resistance of the element, and is advantageous in realizing high-speed operation and high-output operation. However, arranging the p-type semiconductor layer widely is advantageous in reducing the resistance, but there is a problem that there is a limit in reducing the element capacitance.

FIG. 9 shows another conventional semi-insulating high resistance buried layer.
Shows a cross-sectional view of the structure of an embedded semiconductor laser (reference text)
Courtesy: Tanaka et al. Applied Physics vol. Four
7 (1985) 1127-1129). In FIG.
012 is an active layer, 013 is n-InP, and 014 is InG.
aAsP, 015 is p-InP, 016 is p⁺-InG
aAsP, 017 is n-InP substrate, 018 is semi-insulating
InP, 019 is SiO ₂, 020 is an n-type electrode, 021
Shows a p-type electrode. In this device, the active layer 012 is
Both sides of the included stripes are made of semi-insulating InP crystal 01
It is embedded by a current blocking layer composed of 8. This element
In the child, the stripe shape is an inverted mesa, and
The structure is such that the stripe width widens. others
Therefore, there is an advantage that the element resistance can be reduced.

However, the semi-insulating InP crystal embedded structure semiconductor laser having the inverted mesa stripe has the following problems.

1) Fabrication of an inverted mesa-shaped stripe is carried out by wet etching. Therefore, it is difficult to strictly control the active layer width and stripe height.

2) Semi-insulating InP for reducing device capacitance
In order to increase the thickness of the current blocking layer made of a crystalline layer, the height of the stripe must be increased, and therefore, the clad layer disposed above the active layer in the stripe must also be increased. . This causes a problem that the element resistance becomes large when the cladding layer in the mesa stripe is composed of a p-type semiconductor layer like a semiconductor laser on an n substrate. In addition, including the clad layer and electrode layer,
The necessity of forming a thick crystal layer of about 3 to 4 μm, which corresponds to the stripe height, leads to a long crystal growth time.

3) In the inverted mesa-shaped stripe,
The crystal planes forming the side surfaces of the stripe are (111) A planes. Therefore, in the embedded growth process, the Fe-doped InP crystal layer grows not only on the (100) plane which is the substrate crystal plane but also on the crystal plane deviated from the (100) plane. In the metalorganic vapor phase epitaxy method, in which Fe doping into InP is easy, it has been clarified that the Fe doping efficiency into InP depends on the crystal plane orientation (Reference: Takeuchi et al. 53rd Applied Physics Society of Japan). Lecture Proceedings N
o. 1p. 287 18p-ZE-7). Therefore,
On the side surface of the stripe, the Fe doping amount is small and a low resistance crystal layer is formed, and this region serves as a current leakage path, impairing the device characteristics.

This is true in the case of a semiconductor laser having a structure produced by embedding vertical stripes as shown in FIG. 10 (Reference: OK Kebon et al., Abride Physics of Letters, vol. 59 (1).
It also becomes a problem in 991) 253-255). still,
In FIG. 10, 022 is MQW and 023 is n-In.
P, 024 is p-InP, 025 is p-InP, 026
Is p-GaInAs, 027 is Fe-doped SI-In
P, 028 is an n-InP substrate, 029 is a SiN _x film, 0
Reference numeral 30 is an n-type electrode, and reference numeral 031 is a p-type electrode.

The present invention provides a semiconductor light emitting device such as a high resistance layer embedded structure semiconductor laser having a semi-insulating InP crystal layer as an embedded layer and a method for manufacturing the same, which has a structure in which the element resistance is reduced. To aim.

[0011]

The structure of a semiconductor light emitting device according to the present invention which achieves the above object is such that a semi-insulating high resistance crystal layer serves as a current blocking layer, and a conductive clad layer,
And a part of the width of the conductive semiconductor layer serving as the electrode layer is
In a semiconductor light emitting device having a structure that spreads toward the upper part of the element, the interface between a portion of the conductive type semiconductor layer forming the mesa stripe and the current blocking layer is not exposed on the upper surface of the element, It is characterized by being partially covered.

In the above structure, the conductive clad layer and the electrode layer may be separated into at least two regions by a separation layer formed of a semi-insulating high resistance semiconductor layer.

On the other hand, according to a first method of manufacturing a semiconductor light emitting device of the present invention, a semiconductor substrate having a first conductivity type, a buffer layer having at least a first conductivity type, an active layer, and a second layer. Forming a laminated body by sequentially laminating buffer layers having a conductivity type of 1., forming a first mask having a predetermined shape on the laminated body, and forming the first mask through the first mask. A step of etching the stacked body to at least the active layer to form a mesa stripe; and a current blocking layer having at least a semi-insulating high resistance semiconductor layer on both sides of the mesa stripe, at least the second layer.
At a position beyond the buffer layer having the conductivity type to form a groove constituted by the current blocking layer, and at least removing the first mask,
A step of forming a second mask on the upper surface of the current blocking layer excluding the groove bottom surface, the groove side surface, and the corners of the groove opening; and including the groove opening including the second mask as a selective growth mask. And a step of forming a clad layer having a second conductivity type and an electrode layer inside the groove.

A second method for manufacturing a semiconductor light emitting device according to the present invention is characterized in that, on a semiconductor substrate having a first conductivity type,
A buffer layer having at least a first conductivity type, an active layer,
And a step of laminating a buffer layer having a second conductivity type in this order to form a laminated body, a step of forming a first mask having a predetermined shape on the laminated body, and the first mask. Via at least the active layer to form a stripe, and at least a part of the upper surface of the stripe is removed to expose the semiconductor surface to form an inter-electrode separation layer forming region. And filling both sides of the stripe with a current blocking layer having at least a semi-insulating high-resistance semiconductor layer at least to a position beyond the buffer layer having the second conductivity type,
Forming a groove constituted by the current blocking layer, forming a semi-insulating high resistance semiconductor layer in the inter-electrode separation layer forming region formed on the upper surface of the stripe, and removing the first mask A step of forming a second mask on the upper surface of the current blocking layer and the upper surface of the inter-electrode separation layer except at least the corners of the groove bottom surface, groove side surface, and groove opening, and the second mask As a mask for selective growth, a second mask is formed inside the groove including the groove opening.
And a step of forming a clad layer having a conductivity type and an electrode layer.

The device according to the present invention has a structure in which the width of a part of the conductive semiconductor layer corresponding to the clad layer and the electrode layer widens toward the upper part of the device. The current blocking layer is composed of a semi-insulating high resistance layer. The main feature is that the interface between the conductive semiconductor layer and the conductive semiconductor layer forming the mesa stripe is not exposed in the upper part of the element and is covered with a part of the conductive semiconductor layer.

In a buried structure semiconductor device having such a structure, a groove is formed by forming a current blocking layer made of a semi-insulating high resistance layer up to a position sufficiently exceeding the height of a mesa stripe having an active layer. Then, in the groove, covering the corner of the groove opening, a clad layer made of a conductive semiconductor layer,
Alternatively, it is produced by arranging the electrode layers by selective growth.

[0017]

1) The thickness of the conductive clad layer can be set regardless of the thickness of the current blocking layer. Therefore, even if the thickness of the current blocking layer is increased, the thickness of the clad layer can be minimized, which is advantageous in reducing the device resistance. Further, since the selective growth capable of increasing the growth rate is used, the growth time of the conductive type semiconductor layer can be shortened. 2) The height of the stripe formed in the device manufacturing process may be as low as about 1 μm, and the shape thereof may be a vertical shape. Therefore, dry etching, which has higher processing accuracy than wet etching, can be used for forming the stripe. This is advantageous in strictly controlling the active layer width. 3) By making the height of the stripe formed in the device manufacturing process as low as possible, the side surface of the stripe, that is,
The region of the semi-insulating Fe-doped InP layer grown on the crystal plane deviated from the (100) crystal plane can be narrowed. This is advantageous in reducing the current leakage because the formation region of the low resistance layer in the stripe side can be made narrower than that in the conventional technique.

[0018]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a structural diagram of an n-substrate Fe-doped InP buried structure semiconductor laser, which is an embodiment of the present invention. In FIG. 1, the active layer 1 is an InGaAsP semiconductor crystal having an emission wavelength of 1.30 μm. The active layer 1 is sandwiched between the p-type InP buffer layer 2 and the n-type InP buffer layer 3 from above and below in the mesa stripe 11 on the n-type InP substrate 6. Mesa stripe 1
Both sides of 1 are filled with the semi-insulating current blocking layer 7, and the p-type InP clad layer 4 and the p-type InGaAs electrode layer 5 are also filled with the current in the groove 12 formed by the current blocking layer 7. A SiO ₂ mask 8 is arranged on the upper surface of the blocking layer 7. The n-type electrode 10 is the n-type InP substrate 6
Is formed on the entire back surface and the p-type electrode 9 is formed on the upper surface of the element.

FIG. 2 is a sectional view of a product formed at each stage of the manufacturing process of this embodiment. In this example, all the semiconductor layers were formed by the low pressure metal organic vapor phase epitaxy.

First, as shown in FIG.
0) surface n-type InP substrate 6 (carrier concentration 2 × 10 ¹⁸ c
m ⁻³ ) on the n-type InP buffer layer 3 with Se as a dopant (carrier concentration 1 × 10 ¹⁸ cm ⁻³ , thickness 0.1 μm).
m), non-doped InG having an emission wavelength of 1.30 μm
aAsP active layer 1 (thickness 0.15 μm), p-type InP buffer layer 2 having Zn as a dopant (carrier concentration 3 × 1)
0 ¹⁸ cm ⁻³ , thickness 0.2 μm), and an undoped InGaAsP buffer layer 13 (thickness 0.2 μm) corresponding to an emission wavelength of 1.30 μm.
After forming the 05μm), SiO ₂ film 14 (thickness of 0.1μ
m) and a second mask having a width of 1.5 μm are used to perform etching by a highly controllable reactive ion etching method to form a mesa stripe 11 having a height of 0.6 μm and a width of 1.5 μm.

Next, as shown in FIG. 2 (b), both sides of the mesa stripe 11 are filled with an Fe-doped InP layer, a semi-insulating current blocking layer 7 having a thickness of 4.0 μm is arranged, and the current is reduced. Side of blocking layer 7 and mesa stripe 1
A groove 12 constituted by the upper surface of 1 is formed. At this time, the (111) plane constituting the side surface of the groove 12 becomes a regrowth interface by disposing the p-type semiconductor layer thereafter, and the semi-insulating current blocking layer 7 near the (111) plane is This is a region formed while maintaining the (100) plane growth in the crystal growth process, and thus is a high resistance layer sufficiently doped with Fe.

Next, as shown in FIG. 2C, the SiO ₂ film 14 as the _second mask and the non-doped InGaAsP buffer layer 13 arranged for removing the damage introduced at the time of forming the SiO ₂ mask are removed. . And
Except for the corners of the groove side surface, groove bottom surface, and groove opening, SiO
_{2 A} first mask made of the film 8 is arranged.

Thereafter, as shown in FIG. 2D, the p-type InP clad layer 4 and the p-type InGaAs electrode layer 5 are formed in the groove 12 using the first mask 8 as a mask for selective growth.
To place. In the conventional (111) plane, which is the buried growth interface of the inverted mesa-shaped stripe, there was a problem that the electrode material permeated along the interface and impairs the stable operation of the element. However, in the present invention, it is shown in this example. As described above, the p-type semiconductor layer is arranged so as to cover the corner of the groove opening,
The (111) plane was kept out of contact with the electrode material.

After that, the n-type electrode 10 is connected to the n-type InP of the device.
The p-type electrode 9 is formed on the entire back surface of the substrate 6 and on the p-type electrode layer 5, which is the upper surface of the element, and the resonator length is 30.
It was cut into chips so as to have a thickness of 0 μm, and an n-substrate semi-insulating high resistance layer embedded semiconductor laser having a structure as shown in FIG. 1 was obtained.

The characteristics of the manufactured semiconductor laser at room temperature are as follows: oscillation threshold current: 15 mA, maximum output: 20 mW, compared to a conventional semi-insulating high resistance layer embedded structure semiconductor laser.
It is a comparable value. In addition, the series resistance of the device is as low as 3 ohms, the device capacitance is 1.5 pF, and the cutoff frequency at which the modulation intensity decreases by 3 dB is 13 GHz. I could get a laser.

In this embodiment, p-type InGaA is used.
After forming the s-electrode layer 5, as shown in FIG. 3, by arranging the polyimide layers 15 on the upper surface of the current blocking layer 7, it is possible to realize the planarization of the entire device.

Further, as shown in FIG. 4, p-type InGaAs
Even if the electrode layer 5 is separated in the groove 12 and on the insulating current blocking layer 7, the current blocking layer 7 and the mesa stripe 1 are separated.
If the interface with 1 is covered with the p-type InP clad layer 4 on the upper part of the device, it is possible to obtain a device having characteristics similar to those of the present embodiment.

In addition, as shown in FIG. 5, even if the interface between the current blocking layer 7 and the mesa stripe 11 is covered with the electrode layer 5 on the upper part of the device, the effect of the present invention is impaired. There is no such thing.

Further, in this embodiment, as the active layer 1, I
Although the present invention is not limited to the nGaAsP semiconductor layer, the present invention is not limited to this. For example, in the case of a semiconductor laser having an active layer composed of a plurality of semiconductor layers such as a multiple quantum well structure or a strained layer superlattice, Also in the case of a semiconductor laser provided with a diffraction grating, it is possible to obtain a semiconductor laser with a high resistance layer embedded structure similar to that of the present embodiment. In addition to the semiconductor laser, an external modulator, or
The structure and manufacturing method described in this embodiment can be applied to an element in which a semiconductor laser and an external modulator are integrated.

(Embodiment 2) FIG. 6 shows another embodiment of the present invention, which is a structural diagram of an n-substrate Fe-doped InP buried structure semiconductor optical device.

As shown in FIG. 6, the device according to the present embodiment is provided with a first current injection region 20 and a second current injection region 21 on the n-type InP substrate 6. The mesa stripe 23 including the active layer 1 and the guide layer 22 is arranged over both current injection regions, and the semi-insulating current blocking layer 7 is arranged on both sides of the mesa stripe 23. In the groove 12 of the first current injection region 20, the p-type cladding layer 4 and the p-type electrode layer 5 are arranged, and similarly, in the groove 31 of the second current injection region 21, the p-type cladding layer 4 and the p-type electrode layer 5 are formed.
The mold clad layer 24 and the p-type electrode layer 25 are arranged. The p-type semiconductor layer in the first current injection region 20 and the second
The current injection region 21 is electrically isolated from the p-type semiconductor layer by the interelectrode isolation layer 26. n
The mold electrode 10 is on the entire back surface of the element, and the p-type electrode 9 and the p-type electrode 27 are the first current injection region 20, respectively.
And the second current injection region 21.

FIG. 7 is a sectional view of a product formed at each stage of the manufacturing process of this embodiment. In this example, all the semiconductor layers were formed by the low pressure metal organic vapor phase epitaxy.

First, as shown in FIG.
0) surface n-type InP substrate 6 (carrier concentration 2 × 10 ¹⁸ c
m ⁻³ ) on the n-type InP buffer layer 3 with Se as a dopant (carrier concentration 1 × 10 ¹⁸ cm ⁻³ , thickness 0.1 μm).
m), non-doped InG having an emission wavelength of 1.30 μm
aAsP active layer 1 (thickness 0.15 μm), emission wavelength 1.1 μm
Non-doped InGaAsP guide layer 22 corresponding to m
(0.15 μm), p-type InP buffer layer 2 having Zn as a dopant (carrier concentration 3 × 10 ¹⁸ cm ⁻³ , thickness 0.2 μm)
m), non-doped InG having an emission wavelength of 1.30 μm
An aAsP buffer layer 28 (thickness: 0.05 μm) is formed. After that, using a second mask of SiO ₂ film 29 (thickness 0.1 μm) having a width of 1.5 μm, etching is performed by a highly controllable reactive ion etching method to obtain a height of 0.7 μm and a width. A mesa stripe 23 of 1.5 μm is formed. Then, using the resist mask, a part of the SiO ₂ film arranged above the mesa stripe 23 is removed to expose the surface of the non-doped InGaAsP buffer layer.
Then, using a sulfuric acid-based etching solution, non-doped InGa
The AsP buffer layer 28 is selectively removed, and then the p-type InP buffer layer 2 is selectively removed with a hydrochloric acid-based etching solution to expose the surface of the non-doped InGaAsP guide layer 22. By these steps, the mesa stripe 23 including the first current injection region 20, the second current injection region 21, and the inter-electrode separation layer formation region 30 is formed.

Next, as shown in FIG. 7B, both sides of the mesa stripe 23 are filled with an Fe-doped InP layer, a semi-insulating current blocking layer 7 having a thickness of 4.0 μm is arranged, and the current Grooves 12 and 31 formed by the side surface of the blocking layer and the upper surface of the mesa stripe 23 are formed. In the process of forming the semi-insulating current blocking layer 7,
Non-doped InGa that is the inter-electrode separation layer forming region 30.
Even on the crystal plane where the AsP guide layer 22 is exposed, F
The e-doped InP layer grows to form the interelectrode separation layer 26.

Next, as shown in FIG. 7C, a SiO ₂ 29 as a _second mask and a non-doped InGaAsP buffer layer 28 arranged to remove damage introduced during formation of the SiO ₂ mask are formed. Remove. Then, except for the corners of the groove side surface, the groove bottom surface, and the groove opening, S
A first mask made of the iO ₂ film 8 is arranged.

After this, as shown in FIG. 7D, the first
P as a mask for selective growth in the groove 12
The type InP clad layer 4 and the p type InGaAs electrode layer 5 and the p type InP clad layer 24 and the p type electrode layer 25 are grown in the groove 31 to form the current injection region 20 and the current injection region 21.

The n-type electrode 10 is provided on the entire back surface of the device, and
The p-type electrode 9 is formed on the p-type electrode layer 5, and the p-type electrode 27 is formed on the p-type electrode layer 25. Resonator length is 3
A semiconductor optical device having an n-substrate semi-insulating high resistance layer embedded structure having a structure as shown in FIG. 6 was obtained by cutting into chips so as to have a thickness of 00 μm.

Isolation resistance of 10 Mohm or more is obtained from the leak current when 10 V is applied between the p-type electrodes of the first current injection region 20 and the second current injection region 21, and
It was possible to secure a sufficient separation resistance between the electrodes.

According to this embodiment, it is possible to easily realize a composite device of optical functional elements such as a semiconductor laser, an optical modulator and a photodetector.

[0041]

As described above, according to the present invention, the clad layer having the opposite conductivity type to the substrate can be formed with the minimum necessary thickness without being restricted by the thickness of the current blocking layer. As a result, a semi-insulating Fe-doped InP buried structure semiconductor laser having a low device resistance could be manufactured.

Further, in manufacturing the element, the mesa stripe of the active region can be set to have a mesa height lower than that of the conventional manufacturing method, and in addition, a vertical shape by dry etching can be used. For this reason, the active layer width could be determined more precisely than in wet etching. Further, since the stripe height is low, it is possible to narrow the low resistance layer region formed on the side surface of the stripe where Fe doping is insufficient, and it is possible to improve the device characteristics such as reduction of leak current.

In addition, the device manufacturing method according to the present invention can be applied to a device having a plurality of electrodes, and in the manufactured device, sufficient isolation resistance between the electrodes could be secured. .

[Brief description of drawings]

FIG. 1 is a schematic diagram of a semi-insulating high-resistance layer-embedded structure semiconductor laser according to an embodiment of the present invention.

FIG. 2 is a manufacturing process diagram of a product formed at each stage of the manufacturing process of the first embodiment.

FIG. 3 is a schematic diagram of a semi-insulating high-resistance layer-embedded structure semiconductor laser according to an embodiment of the present invention.

FIG. 4 is a schematic view of a semi-insulating high-resistance layer-embedded structure semiconductor laser according to an embodiment of the present invention.

FIG. 5 is a schematic view of a semi-insulating high resistance layer-embedded structure semiconductor laser according to an embodiment of the present invention.

FIG. 6 is a schematic diagram of a semi-insulating high-resistance layer-embedded structure semiconductor laser according to an embodiment of the present invention.

FIG. 7 is a manufacturing process diagram of a product formed at each stage of the manufacturing process of the second embodiment.

FIG. 8 is a schematic view of a conventional semi-insulating high-resistance layer-embedded structure semiconductor laser in which a p-type semiconductor layer is arranged over the upper surface of the device.

FIG. 9 is a schematic view of a conventional semi-insulating high resistance layer-embedded structure semiconductor laser having an inverted mesa stripe.

FIG. 10 is a schematic view of a conventional semi-insulating high-resistance layer-embedded structure semiconductor laser having vertical stripes.

[Explanation of symbols]

1 Active layer 2 p-type InP buffer layer 3 n-type InP buffer layer 4,24 p-type InP clad layer 5,25 p-type InGaAs electrode layer 6 n-type InP substrate 7 semi-insulating current blocking layer 8 SiO ₂ film 9,27 p-type electrode 10 n-type electrode 11,23 mesa stripe 12,31 groove 13,28 non-doped InGaAsP buffer layer 14,29 SiO ₂ film 15 polyimide layer 20 first current injection region 21 second current injection region 22 non-doped InGaAsP guide Layer 26 Electrode separation layer 30 Electrode separation formation region

Claims (4)

[Claims] 1. A structure having a semi-insulating high-resistance crystal layer as a current blocking layer, and a part of the conductive clad layer and a conductive semiconductor layer serving as an electrode layer widening toward the upper part of the device. In the semiconductor light emitting device, the interface between the current-blocking layer and the portion of the conductive semiconductor layer that forms the mesa stripe is not exposed on the upper surface of the device,
A semiconductor light emitting device characterized by being covered with a part of the conductive type semiconductor layer. 2. The semiconductor light emitting device according to claim 1, wherein the conductive clad layer and the electrode layer are separated into at least two or more regions by an electrode separation layer made of a semi-insulating high resistance semiconductor layer. A semiconductor light emitting device characterized by the above. 3. On a semiconductor substrate having a first conductivity type,
A buffer layer having at least a first conductivity type, an active layer,
And a step of sequentially stacking buffer layers having a second conductivity type to form a stacked body, forming a first mask having a predetermined shape on the stacked body, and interposing the first mask. At least the second conductive layer is formed by etching the laminate to at least the active layer to form a mesa stripe, and a current blocking layer having at least a semi-insulating high resistance semiconductor layer on both sides of the mesa stripe. A step of burying up to a position beyond the buffer layer having a mold to form a groove constituted by the current blocking layer, a step of removing the first mask, at least the groove bottom surface, groove side surface, and groove opening Forming a second mask on the upper surface of the current blocking layer, except for the corners, and using the second mask as a mask for selective growth, including the groove opening, and inside the groove. Forming a cladding layer, and an electrode layer having a second conductivity type, a method of manufacturing a semiconductor light emitting device characterized by comprising a city. 4. On a semiconductor substrate having a first conductivity type,
A buffer layer having at least a first conductivity type, an active layer,
And a step of laminating a buffer layer having a second conductivity type in this order to form a laminated body, a step of forming a first mask having a predetermined shape on the laminated body, and the first mask. Through, to form a stripe by etching the laminate to at least the active layer; and removing at least a part of the upper surface of the stripe to expose the semiconductor surface and form an inter-electrode separation layer forming region. And filling both sides of the stripe with a current blocking layer having at least a semi-insulating high resistance semiconductor layer at least to a position beyond the buffer layer having the second conductivity type to form a groove formed by the current blocking layer. Forming and forming a semi-insulating high resistance semiconductor layer in the inter-electrode separation layer forming region formed on the upper surface of the stripe; and the first mask. And a step of forming a second mask on the upper surface of the current blocking layer and on the upper surface of the inter-electrode separation layer except at least the corners of the groove bottom surface, groove side surface, and groove opening. Forming a clad layer having a second conductivity type and an electrode layer inside the groove, including the groove opening, using the mask of 1. as a mask for selective growth. A method for manufacturing a light emitting device.