JPH06224711A - Digital signal reception circuit - Google Patents

Abstract

(57) [Abstract] [PROBLEMS] To provide a digital signal receiving circuit capable of improving the transmission quality by reducing the variation of the reproduced output pulse width with respect to the variation of the length of the transmission path connected. A voltage comparator 1 for comparing a level of an input signal Vs with a reference voltage and outputting a waveform-reproduced digital signal Va.
And a reference voltage setting circuit 2 for setting the reference voltage of the voltage comparator 1 and causing the reference voltage to follow the input signal Vs.
And a delay circuit 3 that corrects the pulse width of the output signal Va by delaying the reference voltage that follows the input signal Vs. [Effect] When the waveform of the blunted input signal that has passed through the transmission path is shaped, the pulse width does not become longer and is output as a rectangular wave signal close to the original pulse width, improving the transmission quality. It becomes possible.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal receiving circuit used in a digital communication system.

[0002]

2. Description of the Related Art Generally, in a digital signal receiving circuit for receiving a digital signal, an input signal waveform has a dull waveform due to a connected transmission line and is not an original rectangular wave pulse. In order to reproduce this signal waveform into the original pulse waveform, a voltage comparator is used to compare the input signal with a reference voltage to create an output signal of a rectangular wave pulse. However, in general, when the reference voltage is at a level of 50% or less of the input signal, if the reference voltage of the voltage comparator is kept constant, the reproduced output pulse width tends to be longer than the original rectangular wave pulse width. is there. Therefore, it has been proposed to make the reference voltage of the voltage comparator follow the input signal.

FIG. 5 is a circuit diagram of a conventional digital signal receiving circuit. The input signal Vs is applied to the positive input terminal of the voltage comparator 1. The positive input terminal of the voltage comparator 1 has a resistor Rc.
Is connected to the negative input terminal via. Power supply voltage Vcc
Is divided by resistors R1 and R2 and applied as a reference voltage Vth to the negative input terminal of the voltage comparator 1. In this conventional example, the reference voltage Vth of the voltage comparator 1 is configured to follow the input signal Vs via the resistor Rc.

FIG. 6 is a circuit diagram of another conventional example. In this conventional example, the input signal Vs is applied to the positive input terminal of the voltage comparator 1 via a low-pass filter composed of a resistor R3 and a capacitor C1. The negative input terminal of the voltage comparator 1 is grounded via the capacitor C2. In this conventional example, in addition to the reference voltage of the voltage comparator 1 following the input signal Vs, a transfer characteristic is obtained by a low-pass filter including capacitors C1 and C2 at the positive and negative input terminals of the voltage comparator 1. The change in the reproduced output pulse width is reduced by adding the frequency band difference.

[0005]

However, in the conventional digital signal receiving circuit, it cannot be said that the change in the reproduced output pulse width is sufficiently small with respect to the change in the length of the connected transmission line. It was a cause of lowering the transmission reliability.

The present invention has been made in view of the above points, and an object of the present invention is to change a reproduced output pulse width with respect to a change in the length of a transmission line to be connected. Another object of the present invention is to provide a digital signal receiving circuit which can reduce the transmission noise and improve the transmission quality.

[0007]

In order to solve the above-mentioned problems, the digital signal receiving circuit of the present invention has the configuration shown in FIG.
As shown in FIG. 4, the voltage comparator 1 that outputs the waveform-reproduced digital signal Va by comparing the level of the input signal Vs with the reference voltage Vth, and the reference voltage Vth of the voltage comparator 1.
And a reference voltage setting circuit 2 that sets the reference voltage Vth to follow the input signal Vs, and a reference voltage Vth that follows the input signal Vs is delayed to output the output signal Vs.
and a delay circuit 3 for correcting the pulse width of a.

[0008]

In the digital signal receiving circuit of the present invention, the reference voltage Vth of the voltage comparator 1 is made to follow the input signal Vs by the reference voltage level setting circuit 2 and is delayed. When the waveform is reproduced, it has an effect of outputting a rectangular wave pulse signal close to the original pulse width without lengthening the pulse width of the output signal Va.

[0009]

FIG. 2 is a diagram showing the construction of an embodiment of the present invention. In this embodiment, the power supply voltage Vcc is divided by the resistors R1 and R2 to set the reference voltage Vth, which is applied to the negative input terminal of the voltage comparator 1 via the delay circuit 3. Further, the reference voltage Vth is configured to follow the input signal Vs by the resistor Rc. The input signal Vs is applied to the positive input terminal of the voltage comparator 1. Reference voltage V of voltage comparator 1
th is set to Vcc × R2 / (R1 + R2) by dividing the power supply voltage Vcc by the resistors R1 and R2, and ΔV = Vs × Rb / depending on the input signal Vs by the resistor Rc.
Only (Rb + Rc) changes. Here, Rb = R1 × R
2 / (R1 + R2). Therefore, the voltage comparator 1
The reference voltage level Vth is as follows. Vth = Vcc × R2 / (R1 + R2) + Vs × Rb / (Rb + Rc) This reference voltage Vth passes through the delay circuit 3, is delayed for a certain period of time τ, and is applied to the negative input terminal of the voltage comparator 1. This delay time τ needs to be set shorter than the time (T−t) obtained by subtracting the longest pulse width t from the bit period T.

The relationship between the input signal Vs and the reference voltage Vth in this embodiment is shown in FIG. Here, the delay time τ of the reference voltage Vth with respect to the input signal Vs is (T−t)
It is set to / 2. Further, FIG. 3C shows the relationship between the input signal Vs and the reference voltage Vth in the conventional example of FIG.
Further, FIG. 3B shows the waveforms of the output signal Va in this embodiment and the output signal Vc in the conventional example. As is clear from this waveform diagram, since the reference voltage Vth is delayed and follows the input signal Vs, the input signal dulled through the transmission line is
It is output as a rectangular signal whose pulse width is close to the original pulse width. Therefore, in this embodiment, even if the signal passes through the transmission line, the output pulse width can be prevented from becoming long and the code distortion can be reduced.

FIG. 4 is a circuit diagram of another embodiment of the present invention. In this embodiment, the reference voltage Vth is set to the input signal Vs.
The arrangement of the resistor Rc for making the input signal Vs and the delay circuit 3 for delaying the reference voltage Vth relative to the input signal Vs are reversed. Similar effects can be obtained in this embodiment as well.

[0012]

Since the digital signal receiving circuit of the present invention is configured as described above, the reference voltage of the voltage comparator delays and follows the input signal, so that the bluntness through the transmission line is reduced. When the waveform of an existing input signal is shaped, the pulse width does not become long and is output as a rectangular wave signal close to the original pulse width, so that there is an effect that the transmission quality can be improved.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing a basic configuration of the present invention.

FIG. 2 is a circuit diagram of an embodiment of the present invention.

FIG. 3 is an operation waveform diagram showing a comparison between operations of the embodiment of the present invention and a conventional example.

FIG. 4 is a circuit diagram of another embodiment of the present invention.

FIG. 5 is a circuit diagram of a conventional example.

FIG. 6 is a circuit diagram of another conventional example.

[Explanation of symbols]

 1 voltage comparator 2 reference voltage setting circuit 3 delay circuit

Claims (1)

[Claims] 1. A voltage comparator which outputs a waveform-reproduced digital signal by comparing the level of an input signal with a reference voltage, and a reference which sets the reference voltage of the voltage comparator and causes the reference voltage to follow the input signal. A digital signal receiving circuit comprising a voltage setting circuit and a delay circuit for correcting a pulse width of an output signal by delaying a reference voltage that follows an input signal.