JPH06224873A - Transmission / reception timing synchronization method and control circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] In TDMA mobile communication in which communication is performed via a base station, noise is generated on the receiving side when the transmission / reception timing is synchronized with the timing of the partner station of burst transmission / reception or the upper network. Eliminate the effects of jitter, and reduce ICs and power consumption. [Structure] Frame timing FT of a synchronization signal included in a burst signal (1) addressed to itself in one TDMA frame
And the phase difference between the frame clock FC generated in the local station and the guard space a after the end of the burst signal.
The clock output of the local station is controlled and synchronized so that the phase difference becomes 0 at points b and b.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is necessary in a communication system for performing burst communication with each other by a time division multiplexing method or the like when synchronizing the speed of transmission / reception timing of its own station with a partner station or network. The present invention relates to a timing synchronization method and control circuit.

[0002]

2. Description of the Related Art In the case of transmitting and receiving continuous information by burst communication such as time division multiplexing, burst information obtained by compressing the continuous transmission information, which is continuous information on the transmitting side, on the time axis and the burst information are transmitted. Both of the continuous reception information received and expanded to the original continuous information on the time axis need to be synchronized in terms of speed. FIG. 3 shows an example of the timing relationship between the above continuous transmission information, burst information, and continuous reception information. FIG. 3 shows a case of a 4-channel time division multiplexing system in which four slots are formed per frame. Continuous transmission information of one frame length is compressed into burst information of one slot, and continuous reception of one frame length is received again. It shows how the information is expanded. In the figure, in the middle burst information, a so-called overhead signal such as a preamble for burst reception timing extraction necessary for the receiving side and a synchronization signal (shaded portion in the figure) for identifying the burst information portion is generally used. Will be added. In addition, a card space, which is a non-signal section for allowing a deviation in processing delay and a deviation in transmission delay of a communication terminal occupying the slot, is required between the slots.

As an example of realizing the timing relationship shown in FIG. 3, the case of generating a transmission / reception timing synchronized with a reception signal from a partner station will be taken up. FIG. 4 shows a conventional configuration example of the timing synchronization control circuit used in this case. In the figure, 41 is a voltage controlled oscillator (VCO), which outputs an oscillating wave having a frequency controlled by a control voltage input. 42 is a frequency dividing circuit for dividing the output of the (VCO) 41 up to the frequency of the symbol timing of burst communication, and 43 is a phase for performing a phase comparison between the symbol timing input ST given from the receiving system and the output of the frequency dividing circuit 42. A comparator, 44 is a loop filter that removes harmonic components from the output of the phase comparator 43, and is usually composed of a first-order or second-order low-pass filter (LPF), the output of which is the control voltage of the VCO 41. It is fed back to the input. Reference numeral 45 is a transmission / reception timing generation circuit, which uses the output of the VCO 41 as a clock source to generate and output various transmission / reception timing outputs TO required for the frame configuration shown in FIG.

In the above structure, the VCO 41, the frequency dividing circuit 42, the phase comparator 43, and the loop filter 44 are PLL.
(Phase Locked Loop), and a transmission / reception timing output TO that is phase-synchronized with the symbol timing input ST given from the receiving system can be obtained. At this time, the output frequency of the VCO 41 is set to K times the frequency of ST, where K is the frequency division number of the frequency dividing circuit 42.

[0005]

However, in the above-mentioned conventional configuration, since the VCO output which is successively phase-synchronized with the symbol timing input ST is used as the transmission / reception timing generation source, the jitter of the ST is affected by the noise in the receiving system. When it becomes large, it has a considerable influence on the timing generation of the transmission system. The influence of the jitter can be changed by the loop band width of the PLL determined by the loop filter 44, the frequency division number K, the gain of the VCO 41, etc.
Generally, when the loop bandwidth is narrowed to suppress the influence of jitter to a low level, the response speed of synchronization pull-in becomes slow and it takes time to establish synchronization of the system. Also, the loop filter 4
In general, the VCO 41 and the like are not suitable for IC, and there is a problem that the miniaturization of the entire circuit is limited.

A method of simply replacing the PLL part in the configuration of FIG. 4 with a digital PLL is also conceivable. However, since the configuration is such that phase synchronization is executed in real time by sampling for each sync, it affects timing generation during transmission and reception. This cannot be avoided, and the above-mentioned problem of jitter cannot be solved at all. This also causes a problem when the transmission / reception timing of the own station is synchronized with the timing of the upper network. Generally, a clock synchronous system in a digital communication network has a very high accuracy of a reference clock source, but as the number of stages of a subordinate synchronous loop increases, a loop far from the reference clock may temporarily experience a phenomenon such as wandering. It is known that accuracy decreases. Therefore, in the conventional configuration, the timing accuracy of the transmission system of burst communication may not satisfy the standard.

An object of the present invention is to provide a transmission / reception timing synchronization method which can avoid the influence of jitter, which is a problem in the conventional configuration, and a transmission / reception timing synchronization control circuit which can be easily integrated into an IC.

[0008]

A transmission / reception timing synchronization method according to the present invention is for receiving a burst signal in TDMA mobile communication and synchronizing a clock for reception processing and a transmission synchronization signal of the own station with the reception burst signal. , Detecting, for each frame, a phase difference between a frame clock obtained from the synchronization signal and the clock included in the burst signal addressed to the own station among a plurality of burst signals forming a frame,
The output timing of the clock is controlled so that the phase difference becomes 0 in the guard space after the end of the burst signal.

Further, the transmission / reception timing synchronization control circuit of the present invention for carrying out the above-mentioned synchronization method has the processing clock frequency necessary for generating the transmission / reception timing in order to synchronize the transmission / reception timing with the burst reception input signal as a synchronization reference. A clock generating circuit for generating a clock output having a frequency of N times, and a variable frequency dividing circuit for dividing the output of the clock generating circuit with a sum (N + ΔN) of the N and a variable value ΔN given from the outside as a frequency dividing number. A frequency dividing circuit for dividing the output of the variable frequency dividing circuit to obtain a frame timing clock having the same cycle as one frame defined in communication; and a frame timing input of the frame timing clock and the burst reception input signal. Of a phase comparator for detecting the phase difference of the The temporary storage that outputs the temporarily stored value as the variable numerical value ΔN to the variable frequency divider circuit when the switching signal is in the ON state and resets the temporary storage value to 0 when the gate timing signal changes to the OFF state A circuit and a transmission / reception timing generation circuit for generating a desired transmission / reception timing output using the output of the variable frequency dividing circuit and the gate timing signal to be supplied to the temporary storage circuit. is there.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (Structure) FIG. 1 is a time chart for explaining a synchronization method of the present invention, and FIG. 2 is a block diagram showing an example of the structure. First, the configuration of FIG. 2 will be described. In the figure,
Reference numeral 1 is a clock generation circuit for generating a clock output having a frequency N times as high as the processing clock frequency required for transmission / reception timing generation. Reference numeral 2 denotes a variable frequency divider circuit, which is a sum (N +) of a variable numerical value ΔN given from the outside and a constant N set internally.
ΔN) is the frequency division number, and the output from the clock generation circuit 1 is frequency divided. Such a circuit can be easily realized by using a preset type counter circuit. 3 is a variable frequency dividing circuit 2
A frequency divider circuit for obtaining the frame timing clock FC having the same cycle as the frame by dividing the output of the above-mentioned F.C. and a phase comparison for detecting the phase difference between the FC and the frame timing input FT of the received burst signal given as a reference of the frame timing. It is a vessel. This circuit may use a circuit for binarizing the phase difference like a D-type flip-flop, or
A circuit that multi-values the phase difference may be used by latching the frequency-divided output of the frequency divider 3 at the timing of FT. Reference numeral 5 denotes a temporary storage circuit, which temporarily stores the phase comparison output and supplies the temporary storage value to the variable frequency dividing circuit 2 as the variable numerical value ΔN when the externally applied gate timing signal GT is in the ON state. , GT has a function of resetting the temporarily stored value to 0 when the GT is turned off. Such a function can be easily realized by using a register including a flip-flop. Reference numeral 6 denotes a transmission / reception timing generation circuit, which uses the output of the variable frequency dividing circuit 2 to output various desired transmission / reception timing outputs T necessary for frame construction in a communication line.
O and the gate timing signal GT are generated.

[0011]

The operation of the present invention based on the configuration example of FIG. 2 will be described below with reference to FIG. FIG. 1 is a time chart for explaining the synchronization method of the present invention. In the figure, the uppermost stage is the received signal, and shows the case where the number of time division multiplexing is 4, as in the case of FIG. At this time, one frame has four burst signals,
That is, it is composed of four slots (1), (2), (3), and (4), and in addition to burst information in each slot,
An overhead signal composed of a preamble and a synchronization signal is added, and a guard space is provided between burst signals. Also, FT in the figure is a frame timing input,
FC is a frame timing clock, and GT is a time chart of a gate timing signal.

Now, assuming that the slot assigned to the own station is (1), the detection result becomes the frame timing FT every time the synchronization signal of the slot (1) (hatched portion in the figure) is received. It is input to the phase comparator 4. The other input of the phase comparator 4 is the output of the variable frequency dividing circuit 2 and the frequency dividing circuit 3
It is a frame timing clock FC obtained by frequency division by, and the phase difference between FT and FC is determined at each time point A and B in the figure. In the example of the figure, with respect to the reference FT,
FC phase is "delayed" at time A, "advanced" at time B
The state of is fixed. The phase difference at this time is stored as ΔN in the temporary storage circuit 5, and the gate timing signal GT is stored.
Is supplied to the variable frequency dividing circuit 2 when it is turned on at the time points a and b in FIG. In the example shown in the figure, “delay” at time A (Δ
The operation of the variable frequency dividing circuit 2 corresponding to “advance” (N is negative) and “advance” at time B (ΔN is positive) is (N−
| ΔN |) frequency division (operation to advance the phase) and (b) (N + | ΔN |) frequency division (operation to delay the phase) at the time point b. Therefore, the output of the variable frequency division circuit 2 is the timing of the partner station. It can be seen that the processing frequency for transmission / reception timing synchronized with is obtained and the negative feedback control is executed. However, | Δ
N | indicates the absolute value of ΔN.

What should be noted is the timing of executing the negative feedback control. The ON state of GT is given in the guard space after the slot (slot (1)) of the received signal is finished. By giving the GT timing in this way, it is possible to perform synchronization without affecting the transmission / reception timing generation during transmission / reception.
That is, the conventional analog PLL or digital PLL
It is possible to realize phase synchronization by intermittent off-line processing which is completely different from real-time phase synchronization in the configuration using.

The above example of FIG. 1 is for the case where the own station generates the transmission / reception timing synchronized with the received signal from the partner station, but as another example, the same is true for the case of synchronizing with the timing of the upper network. Therefore, at this time, the frame timing input FT of FIG. 1 is given from the network to its own station. In this case, in the configuration of the present invention, even if the timing accuracy of the network temporarily decreases,
During transmission / reception of the burst signal, the synchronous system operates not in the negative feedback closed loop configuration but in the open loop configuration completely dependent on the frequency accuracy of the clock generation circuit 1 of the local station, so that it is easy to satisfy the standard for burst communication. is there.

[0015]

As described above in detail, according to the present invention, it is possible to generate a transmission / reception timing which does not depend on noise or timing accuracy of the other station with respect to the other station or a host network. In realizing,
There are advantages that IC, low power consumption, and miniaturization are easy.

[Brief description of drawings]

FIG. 1 is a time chart illustrating a synchronization method of the present invention.

FIG. 2 is a diagram showing a configuration example of the present invention.

FIG. 3 is an explanatory diagram showing an example of a timing relationship between continuous information and burst information.

FIG. 4 is a diagram illustrating a conventional configuration example.

[Explanation of symbols]

 1 Clock Generation Circuit 2 Variable Frequency Division Circuit 3 Frequency Division Circuit 4 Phase Comparator 5 Temporary Storage Circuit 6 Transmission / Reception Timing Generation Circuit 41 VCO 42 Frequency Division Circuit 43 Phase Comparator 44 Loop Filter 45 Transmission / Reception Timing Generation Circuit

Claims (2)

[Claims] 1. A self-station among a plurality of burst signals constituting a frame for receiving a burst signal in TDMA mobile communication and synchronizing a clock for reception processing and a transmission synchronization signal of the self-station with the reception burst signal. The phase difference between the synchronization signal included in the addressed burst signal and the frame clock obtained from the clock is detected for each frame, and the phase difference of the clock is adjusted so that the phase difference becomes 0 in the guard space after the end of the burst signal. A transmission / reception timing synchronization method for controlling output timing. 2. A clock generation circuit for generating a clock output having a frequency N times as high as a processing clock frequency required for transmission / reception timing generation in order to synchronize transmission / reception timing with a burst reception input signal as a synchronization reference. Sum (N +) with variable value ΔN given from the outside
ΔN) is a frequency division number, and a variable frequency dividing circuit for frequency-dividing the output of the clock generating circuit, and 1 defined for communication by frequency-dividing the output of the variable frequency dividing circuit
A frequency divider circuit for obtaining a frame timing clock having the same cycle as the frame, a phase comparator for detecting a phase difference between the frame timing clock and the frame timing input of the burst reception input signal, and an output of the phase comparator temporarily stored. , When the externally applied gate timing signal is in the on state, the temporarily stored value is output to the variable frequency dividing circuit as the variable numerical value ΔN, and when the gate timing signal changes to the off state, the temporarily stored value is changed. A transmission / reception including a temporary storage circuit for resetting to 0, a desired transmission / reception timing output using the output of the variable frequency dividing circuit, and a transmission / reception timing generation circuit for generating the gate timing signal to be supplied to the temporary storage circuit. Timing synchronization control circuit.