JPH06232002A - Chip type capacitor - Google Patents

Abstract

(57) [Summary] [Construction] In a chip type capacitor 10 having electrodes 12 formed at both ends of a dielectric 11, a recess 13 is formed on one or both sides of the end of the dielectric, and a metal for electrodes is provided in the recess 13. Filled chip type capacitor 10. [Effect] The capacitance value can be finely controlled within a wide range without changing the external dimensions of the chip. Therefore, it can be used for a resonance circuit or an oscillation circuit in a high frequency region. Further, the concave portion 13 can be formed immediately before the electrode 12 is formed, the variation in the capacitance value due to the difference in the outer dimension and the dielectric material can be corrected, and the yield can be increased and the cost can be reduced. it can. In addition, the adhesion force between the electrode 12 and the dielectric 11 can be increased, and high reliability can be obtained. Further, since the chip sizes can be unified, the mounting can be facilitated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip type capacitor, and more particularly to a chip type capacitor having electrodes formed at its ends and used in high frequency electronic circuits and the like.

[0002]

2. Description of the Related Art Conventionally, a capacitor used in a high frequency electronic circuit is generally required to have a small electrostatic capacitance value (hereinafter, referred to as a capacitance value), and depending on a dielectric material, it may be formed at both ends of the dielectric substance. There is a structure in which the required capacitance value is reached only with the formed electrodes, and the internal electrodes are not formed. In addition, in order to reduce the size and weight of electronic equipment and achieve high-density mounting, a chip-type capacitor that is made into a small chip is known as this type of capacitor.

7 and 8 are a schematic cross-sectional view and a schematic side view showing a conventional chip type capacitor, and a chip type capacitor 30 is constructed by forming electrodes 12 on both ends of a dielectric 11. There is. Further, in such a chip-type capacitor 30, in order to unify the mounting apparatus, the length (L) of the chip, as seen in EIAJ, RC-3402 (multilayer porcelain chip-type capacitor for electronic equipment) and the like, is used. ), Width (W) and height (T) are standardized. According to this standard, the range in which the L and W dimensions can be changed is determined to be ± 0.2 mm when the chip size is 2.0 mm x 1.25 mm, and the T dimension is 1.45.
It is determined to be less than or equal to mm.

[0004]

The capacitance value C of the above chip type capacitor 30 is C = ε _s × ε _o × s ÷
d [F] (ε _s : relative permittivity, ε _o : 8.854 × 10
^-12 [F / m], s: electrode area, d: distance between electrodes).

Generally, when a capacitor is used in a resonance circuit or an oscillation circuit, it is necessary to finely select the capacitance value. Therefore, in order to use the chip capacitor 30, it is necessary to change the area (s) of the electrodes, the distance (d) between the electrodes, and the relative permittivity (ε _s ) of the dielectric material to change the capacitance value. However, in order to change the distance between electrodes, it is necessary to change the L dimension, and since the range in which the L dimension can be changed is narrow, it is difficult to change the distance between electrodes.

Therefore, as a method of changing the capacitance value without changing the L dimension, there is a relatively wide changeable range, in which the T dimension is changed to change the electrode area, and a different dielectric material is used to change the relative dielectric constant. There is a way to change.

However, in the method of changing the electrode area, the W dimension is almost constant according to the standard, and it is necessary to change only the T dimension. Therefore, the relative permittivity is 100
In the chip type capacitor 30 using the grain boundary layer type dielectric material of about 000, the capacitance value of 300 pF to 800 pF was obtained by changing T from 0.5 mm to 1.45 mm. There was a problem that was narrow and limited.

Further, in the case of the method of changing the relative permittivity, there is a problem that the capital investment increases because the techniques for producing the materials having different relative permittivities are different from each other.

Further, there is a problem that the yield is reduced due to the variation of the relative dielectric constant between lots and the variation of each dimension.

The present invention has been made in view of the above problems, and it is easy to mount, the yield is high, the cost is low, the capacitance value can be finely controlled, and the resonance circuit or the oscillation circuit in the high frequency region is provided. The purpose is to provide a chip type capacitor that can be used for.

[0011]

In order to solve the above-mentioned problems, a chip type capacitor according to the present invention is a chip type capacitor in which electrodes are formed on both ends of a dielectric, and one side or both sides of the dielectric end is It is characterized in that a concave portion is formed and the concave portion is filled with a metal for an electrode.

[0012]

According to the above construction, the concave portion is formed on one side or both sides of the dielectric end portion, and the concave portion is filled with the electrode metal, so that a parallel circuit including two capacitors is formed. The circuit configuration is as described above. The circuit configuration differs between the case where the concave portion is formed on one surface and the case where the concave portion is formed on both surfaces. When the concave portion is formed on one surface, the inter-electrode distance in the one capacitor is the maximum of the concave portion. It can be regarded as the distance between the back surface and the electrode on the other surface, and the distance between the electrodes in the other capacitor can be regarded as the distance between the other end surface other than the recess and the electrode on the other surface. When the recesses are formed on both sides, the inter-electrode distance in the one capacitor can be regarded as the distance between the recessed innermost surface of the other recessed portion and the other recessed member innermost surface that faces the recessed portion innermost surface. The inter-electrode distance in the capacitor can be regarded as the distance between the remaining end surface other than the recess and the remaining end surface other than the recess. Therefore, even if the dimensions of L, M, and T of the chip are not changed, the apparent distance between the electrodes and the apparent electrode area of the two capacitors are changed by changing the depth and diameter of the recess. It becomes possible. Therefore, in a chip of the same size, by selecting the diameter and depth of the recess, it becomes possible to finely control the capacitance value within a wide range.

Further, since the surface area of the electrode is increased due to the formation of the concave portion, the dielectric and the electrode are firmly fixed to each other, and the peeling of the electrode is prevented. Therefore, high reliability can be ensured.

[0014]

Embodiments of a chip type capacitor according to the present invention will be described below with reference to the drawings. It should be noted that components having the same functions as those of the conventional example are designated by the same reference numerals.

1 to 3 show an embodiment of a chip type capacitor according to the present invention, FIG. 1 is a schematic sectional view, FIG. 2 is a schematic side view and FIG. 3 is a perspective view. 1 in the figure
Reference numeral 0 denotes a chip type capacitor, in which a concave portion 13 is formed at one end 11a of a dielectric substrate 11 which is grain boundary insulated, and the concave portion 13 is filled with a metal for electrodes.
The electrode 12a including 3 is formed. An electrode 12b is formed on the other end 11b, and the chip capacitor 10 is constructed in this manner.

In manufacturing the grain boundary layer insulated chip type capacitor 10 having the above structure, first, SrTiO ₃ is prepared.
A semiconductorizing agent or the like is added to the powder, a binder or the like is further added, and the mixture is kneaded and then molded into a sheet by an extrusion molding method. Next, this ceramic green sheet is, for example, 2.
It is cut into a size of 0 mm x 1.25 mm x 1.45 mm to be a baked dimension and fired in a reducing atmosphere to form a semiconductor porcelain substrate. Furthermore, after applying a metal oxide paste for insulation, it is fired at a temperature of about 1000 ° C. in the air to insulate the grain boundary layer, and SrTiO ₃
A system grain boundary layer insulating type semiconductor capacitor substrate is obtained. In addition,
The apparent dielectric constant of this substrate is about 100000.

This substrate is used as a dielectric substrate 11, and a recess 13 having a diameter of 1.0 mm and a depth of about 0.5 mm is formed on one end 11a of the dielectric substrate 11 by using a CO ₂ laser. Next, a metal paste containing Ag as a main component is continuously applied to the surface of the end portion 11a and the surface of the end portion 11b from the concave portion 13, and the electrode 12 is subjected to a baking treatment.
a and the electrode 12b are formed.

As a result of measuring the capacitance value of the chip-type capacitor 10 thus manufactured, the maximum value is 10
A value of 00 pF could be obtained. Thus, the recess 1
Although the depth of 3 was small, a capacity value higher than the theoretical value was obtained. This is because when the grain boundary layer in one direction is shallowly broken as shown in FIG. 4A, the recess 13 is apparently formed at a depth of one average grain size as shown in FIG. 4B. For example, the average grain size of the grain boundary layer is about 50 μm, and the thickness of the grain boundary insulating layer is several μm.
In this case, even if the recess 13 has a depth of several μm, the same result as in the case of the recess 13 having a depth of about 50 μm, which is the average particle size, can be obtained.

Further, the dielectric substrate 1 as shown in FIG.
The end portion 11a and the end portion 11b of 1 have a diameter of 1.0 mm,
In a chip type capacitor 10 according to another embodiment in which a recess 13 having a depth of about 1.2 mm is formed on both sides,
A capacitance value of 00 pF could be obtained.

Further, in the chip type capacitor 10 according to another embodiment described above, as a result of measuring the adhesion force between the dielectric substrate 11 and the electrode 12, a value of 40 Newton can be obtained, which is a conventional chip type capacitor. 20 in 30
I was able to double the Newton value. Therefore, by filling the recess 13 with the electrode metal, the surface area of the electrode 12 can be increased, and the dielectric substrate 11 can be formed.
It was found that the adhesive force between the electrode 12 and the electrode 12 can be enhanced.

As described above, the recess 13 may be formed on one side or both sides, and the same effect can be obtained not only by one but also by several.

The dielectric is not limited to a grain boundary insulated substrate, but a surface layer insulated substrate can be used. In the case of a chip type capacitor 20 according to still another embodiment in which a conductor porcelain substrate is heat-treated to have its surface insulated,
The capacity value could be increased up to about twice. From this, in the chip type capacitor 20 having the insulating layer formed on the surface layer, even if the recess 13 (FIG. 6A) in which one side of the insulating layer 14 on the surface is shallowly broken is used, It was found that it has the same effect as the recess 13 (FIG. 6B) destroyed to the vicinity of the layer 14 and can significantly reduce the apparent inter-electrode distance. Therefore, the insulating layer 14
When the structure of (3) is used, a large capacitance value can be obtained by forming the shallow recess 13.

Furthermore, since the concave portion 13 can be formed immediately before the electrode 12 is formed, it is possible to correct the variation in capacitance value due to the difference in external dimensions and the dielectric material.

[0024]

As described above in detail, in the chip type capacitor according to the present invention, in the chip type capacitor in which the electrodes are formed on both ends of the dielectric, concave portions are formed on one side and both sides of the dielectric end. Since it is formed and the concave portion is filled with the metal for the electrode, without changing the outer dimensions of the chip,
The capacitance value can be finely controlled within a wide range. Therefore, it can be used for a resonance circuit or an oscillation circuit in a high frequency region.

Further, the concave portion can be formed immediately before the electrode is formed, and the variation in the capacitance value due to the difference in the outer dimension and the dielectric material can be corrected, and the yield can be increased and the cost can be reduced. You can also

In addition, the fixing force between the end electrodes and the dielectric can be increased, and high reliability can be obtained.

Further, since the chip sizes can be unified, the mounting can be facilitated.

[Brief description of drawings]

FIG. 1 is a schematic sectional view showing an embodiment of a chip capacitor according to the present invention.

FIG. 2 is a schematic side view showing a chip capacitor according to an example.

FIG. 3 is a perspective view showing a chip capacitor according to an example.

FIG. 4A and FIG. 4B are structural views schematically shown in order to explain the effect of the recess in the chip capacitor according to the example.

FIG. 5 is a schematic cross-sectional view showing a chip type capacitor according to another embodiment in which concave portions are formed at both ends of a dielectric.

6A and 6B are cross-sectional views schematically showing the effect of a recess in a chip capacitor according to another embodiment in which an insulating layer is formed on the surface layer.

FIG. 7 is a schematic cross-sectional view showing a conventional chip type capacitor.

FIG. 8 is a schematic side view showing a conventional chip type capacitor.

[Explanation of symbols]

 10 Chip Capacitor 11 Dielectric (Dielectric Substrate) 12 Electrode 13 Recess

Claims (1)

[Claims] 1. A chip-type capacitor having electrodes formed on both ends of a dielectric, wherein a recess is formed on one or both sides of the end of the dielectric, and the recess is filled with a metal for an electrode. Chip type capacitors that do.