JPH06232702A - 3-level pulse generator - Google Patents

Abstract

(57) [Summary] [Object] To provide a circuit configuration that can be formed in an image sensor chip in a three-value level generation circuit for CCD. A circuit 3 for generating a binary level clock, a transfer switch element TSW ₂ for controlling connection or opening of a circuit output terminal and a CCD transfer electrode,
The transfer switch element TSW ₁ controls connection or opening of the CCD transfer electrode and the third-level reference voltage source 2. [Effect] When a high S / N ratio can be easily formed in the image sensor chip, only the binary level generating circuit 3 which is the heat source thereof is not on-chip. , And its versatility is high.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ternary level pulse signal generating circuit, and more particularly to a pulse signal generating circuit used for generating a transfer clock of a charge transfer device.

[0002]

2. Description of the Related Art In an image sensor using a CCD as a charge transfer element, by applying a clock having a ternary level clock amplitude as a transfer clock,
A so-called transfer gateless (TG-less) structure is proposed in which charge transfer from the photoelectric conversion element to the CCD shift register can be controlled at the same time (for example, JP-A-56-85981). Conventionally, the clock amplitude of the three-valued level is applied from the outside by using the circuit shown in FIG. The clock generation circuit of FIG. 3 operates as shown in the timing chart of FIG. That is, the current time t ₁
In the CMO in which the pulse φ _T is at a high level and P-channel type and N-channel type MOSFETs are connected in series.
The voltage V _{A at} the output node A of the S structure inverter 1 is at a low level (V _A = 0V). Further, the potential VB of the node B connected to the P-channel MOSFET of the inverter 2 having the same CMOS structure is higher than the voltage V _{2 of the} power source ₂ by the diode D ₁
By the forward voltage V _D due to V _B =
And has a V ₂ -V _D. At this time, since the pulse φ ₁ is at high level, the output voltage φ _V of the inverter 2 is at low level (φ _V = 0V). At this time, V _A = 0V, V _B =
Since it is V ₂ −V _D , the capacitor C ₁ has a potential difference (V _B −V _A ) between its two terminals.
_If the capacitance of ₁ is C ₁ , the charge Q ₁ = C ₁ (V ₂ −V _D ).
Has been accumulated.

At time t ₂ , the pulse φ _T remains at the high level and does not change. Therefore, the potentials V _A and V _{B of the} nodes A and B are
Does not change. Since the pulse φ ₁ becomes low level, the P-channel MOSFET Tr2p of the inverter 2 is turned on and the N-channel MOSFET Tr2N is turned off, so that the output pulse φ _V is the same voltage as the voltage V _{B at the} node B (V ₂ -V _D ). This output pulse φ _V is C
CD is connected to the transfer electrodes, when the capacity and C _L, so that _{Q L = C 1 (V 2} -V D) only charge is accumulated in the capacitor C _L.

At time t ₃ , the pulse φ ₁ remains low so that the P-channel MOSFET of inverter 2
Tr ₂ p remains on. Since the pulse φ _T changes from the high level to the low level, the P-channel MOSFET Tr ₁ p of the inverter 1 turns on and the N-channel M
Since the OSFET Tr1N is turned off, the potential V _{A at the} node A rises from 0V to V ₁ . This increases the charge potential V _B at the node B is stored in the capacitor _{C 1, C L Q 1,} Q L
Is stored, V _B = (V ₂ −V _D ) + C ₁ · V ₁ / (C ₁ + C _L ) ...
... rises to (1). Since the P-channel transistor Tr ₂ p of the inverter 2 remains on, this is also the potential of the output pulse φ _V. Here C ₁ becomes if you set as of _{>> C L V B ≒ V 2} -V D + V 1 ...... (2). The potential of the node B of the diode D ₁ is the power source 12
The current is prevented from flowing back to the power supply 2 even when the voltage rises above the voltage V _{2 of the} above.

At time t ₄ , the pulse φ ₁ remains low so that the P-channel transistor Tr _{2 of the} inverter 2 is
Since p remains on and the pulse φ _T changes to a high level, the voltage V _{A at the} node A becomes 0 V, and the voltage V _{B at the} node B changes from the potential of the formula (2) to V ₂ −V _D. Lowered by C ₁ . Since there is no change in the pulse φ _T after this,
A normal binary clock in which the pulse φ ₁ is simply inverted is output as the output pulse φ _V. As described above, in the conventional three-value level generation circuit, the basic operation is to raise the potential of the output pulse φ _V by the charge accumulated in the capacitor C ₁ by setting C ₁ >> C _L.

[0006]

In such a conventional three-value level generating circuit, the capacitance element C ₁ needs to have a capacitance sufficiently larger than the capacitance C _L of the CCD transfer electrode, and drives the large load capacitance. Inverter 1 with sufficient capacity is required. However, since the capacitance C _L of the CCD transfer electrodes are present about 1000pF, capacitor C ₁ is required tens .mu.F, to drive a large capacitive Thus is is large driving capability to the inverter 1 is required It was Thus, the need for a large capacity and the need for an inverter with a large drive capacity are major problems in forming this circuit in an image sensor chip in order to reduce the number of peripheral circuit components. At present, it is impossible to form a ternary level generating circuit in the image sensor chip.

[0007]

SUMMARY OF THE INVENTION According to the present invention, a switch having two first and second voltage levels in response to a first pulse.
A binary level clock generating means for generating a value level clock, an output terminal of the binary clock generating means, and a CCD
First switch means for controlling the connection with the transfer electrode by the second pulse, a voltage source for generating a third voltage level, and ON / OFF of the first switch means controlled by the second pulse. Performs a reverse operation to obtain a ternary level pulse generation circuit having the above-mentioned voltage source and the second switch means for controlling the connection between the CCD transfer electrode.

[0008]

The present invention will now be described in more detail with reference to the drawings. FIG. 1A is a circuit diagram of an embodiment of the present invention.
(B) is a specific example thereof, and FIG. 2 is a timing chart thereof.
Now, at time t _1A , the pulse φ ₁ is at high level, and P
The output voltage V _C of the inverter 3 having a CMOS configuration in which the channel type MOSFET Tr ₃ p and the N channel type MOSFET Tr ₃ N are connected in series is at a low level. At this time, for example, a P-channel MOSFET Tr ₅
The transfer switch TSW ₂ configured by connecting p and N-channel type MOSFET Tr ₅ N in parallel is turned on, and similarly P-channel type MOSFET Tr ₄ p and N
Since the transfer switch TSW ₁ configured by connecting the channel type MOSFET Tr ₄ n in parallel is off, the pulse φ _V applied to the CCD transfer electrode has the same potential as the output V _{C of the} inverter 3. Time t _2A
The transfer switch TSW ₂ is kept on and the transfer switch FSW ₁ is kept off, so that the pulse φ ₁ becomes low and the inverter 3
Output V _C becomes high level and pulse φ _V becomes
Output V _C has the same potential as V ₁ potential. Time t _3A
At this time, since the transfer switch TSW ₂ is turned off and the transfer switch TSW ₁ is turned on, the pulse φ _V is applied to the reference potential V ₂ supplied from the power source 12.
Is the same as At time t _4A , the transfer switch T
Since SW ₂ is turned on and the transfer switch TSW ₁ is turned off, the pulse φ _V returns to the potential V ₁ supplied from the power source 11, which has the same potential as the output V _{C of the} inverter 3.

Thereafter, the transfer switch TSW ₁ is kept off and the transfer switch TSW ₂ is kept on, so that the pulse φ _V becomes the output V of the inverter 3.
_It shows the same voltage change as _C. As described above, it is possible to generate a three-valued level with a simple circuit configuration including the inverter 3 and the transfer switches TSW ₁ and TSW ₂ . The on / off control of the transfer switches TSW ₁ and TSW ₂ can be easily performed by the three-stage inverter 4.

[0010]

As described above, the ternary level pulse generating circuit of the present invention can be easily formed by the CMOS inverter and the switching element for CMOS transfer without using a large capacity capacitor, so that it is formed in the image sensor chip. Can be realized. Also, a large-capacity CCD
When the heat generated in the inverter 3 due to charging / discharging of the transfer electrode causes the temperature of the image sensor chip to rise and the S / N of the sensor itself to decrease, only the inverter 3 is formed on the chip and the transfer switch TSW ₁
It is also possible to form only TSW ₂ and its control circuit on the chip. It goes without saying that the binary level clock generation need not be performed by the inverter 3, but may be a simple buffer (not inverted).

[Brief description of drawings]

FIG. 1A is a circuit diagram showing an embodiment of the present invention,
FIG. 1B is a circuit diagram showing a specific example.

FIG. 2 is a timing chart showing operation waveforms of various parts of the embodiment of the present invention.

FIG. 3 is a circuit diagram showing a conventional example.

FIG. 4 is a timing chart showing operation waveforms of various parts of a conventional example.

[Explanation of symbols]

Tr ₁ p, Tr ₂ p ..., Tr ₄ p, Tr ₅ p P-channel type MOS Tr Tr ₁ n, Tr ₂ n ..., Tr
₄ n, Tr ₅ n N-channel type MOS TrC ₁ ,
C _L capacity V ₁ , V ₂ , V ₃ Voltage source voltage TSW ₁ , TSW ₂ Transfer switch 11, 12 Power supply 1, 2, 3, 4 Inverter

Front page continuation (72) Inventor Junichi Yamamoto 5-7-1 Shiba, Minato-ku, Tokyo NEC Corporation

Claims (1)

[Claims] 1. A clock generating means for generating a binary level clock having first and second voltage levels in response to a first pulse, and between the output terminal and the output terminal of the clock generating means. First switch means for controlling the connection with a second pulse; a voltage source for generating a third voltage level;
A second switch that is controlled by the second pulse to perform an operation opposite to the on / off operation of the first switch means and controls a connection between the voltage source and the output terminal. A ternary level pulse generation circuit characterized by: