JPH06233122A - Image processing device - Google Patents

Abstract

(57) [Summary] (Modified) [Purpose] An image processing unit based on the dither method and an image processing unit based on the error diffusion method, or a binary error diffusion processing unit and a multilevel error diffusion processing unit in the same device. When incorporating into
To provide an image processing device that can share a common circuit portion and minimize increase in space and cost. A binary error diffusion process characterized in that an output quantization comparator 14 of a binary error diffusion process circuit is provided with a dither data input unit and a dither data / error diffusion process data selection unit 16. In addition to an image processing device capable of dithering, or a binary output quantization comparator of a binary error diffusion processing circuit, a multilevel output quantization comparator and an encoding means for the multilevel output quantization comparator output An image processing apparatus capable of performing binary error diffusion processing and multi-valued error diffusion processing, characterized in that

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention has a structure in which a simple circuit is added to a circuit having a binary error diffusion processing function.
The present invention relates to a multifunctional image processing apparatus capable of performing binary and multi-valued dither processing, multi-valued error diffusion processing, and the like in addition to value error diffusion processing.

[0002]

2. Description of the Related Art Conventionally, as a binarizing method for reproducing a halftone image in a digital printer, a digital facsimile apparatus, etc., a dither method using a dither matrix that periodically changes as a threshold and a binarizing process are used. There is a method called an error diffusion method that disperses the generated error to surrounding pixels. In the former case, the number of gradations that can be expressed is limited by the dither matrix. For example, when the number of gradations is about 16 gradations, there is a problem that a pseudo contour is generated in the output image. In the latter case, such a problem does not occur, and both resolution and gradation are superior to the dither method. However, in recent years, even in the latter technique, when the density of the original is low, dots are generated close to each other in the reproduced image,
It has been pointed out that there is a problem that they are connected linearly and the quality of the image is degraded, and measures against this have been proposed (for example, see Japanese Patent Laid-Open No. 2-11063). The technique disclosed in the above publication has a means for generating error data irrespective of an input image in addition to a normal error data calculating means, and which error data is used by discriminating the characteristics of the input image. Is selectable.

[0003]

By the way, in the conventional communication apparatus, the image processing section based on the above-mentioned dither method and the image processing section based on the error diffusion method are incorporated in the same apparatus, and these are appropriately used properly. The configuration used was common. However, assembling these two types of image processing units in the same device requires space.
There were many problems in terms of cost increase. Further, in the conventional communication device, there is also a configuration in which the image processing unit for binary error diffusion processing and the image processing unit for multi-level error diffusion processing are incorporated in the same device, and these are appropriately used properly. However, even if these two types of image processing units are incorporated in the same device, there are problems such as requiring a space and increasing costs. The present invention has been made in view of the above circumstances, and an object of the present invention is to solve the above-mentioned problems in the related art, and to use an image processing unit based on the dither method and an image processing unit based on the error diffusion method. Alternatively, when a binary error diffusion processing unit and a multi-valued error diffusion processing unit are incorporated in the same device, a common circuit portion can be shared, and an image processing device that minimizes an increase in space and cost is provided. Especially.

[0004]

The above objects of the present invention are as follows.
A binary error diffusion process and a dither process are possible, which is characterized in that the output quantization comparator of the value error diffusion process circuit is provided with a dither data input unit and a selection unit of dither data and error diffusion process data. In addition to the binary output quantization comparator of the image processing apparatus or the binary error diffusion processing circuit, a multilevel output quantization comparator and an encoding means for the multilevel output quantization comparator output are provided. This is achieved by an image processing device capable of performing a binary error diffusion process and a multi-value error diffusion process.

[0005]

First, the binary error diffusion processing circuit and dither processing circuit used in the prior art will be described. Figure 6
The binary error diffusion processing circuit used in the prior art is
FIG. 7 shows a dither processing circuit used in the prior art. The binary error diffusion processing circuit shown in FIG. 6 includes an error diffusion matrix (eg, 2 × 5) 11, an error diffusion processing operation unit 1
2, a threshold register 13, a binary output quantization comparator 14, and an error data calculator 15. Here, the error diffusion matrix (2 × 5) 11 is a block for latching error data in a matrix as shown in FIG. 8, and the error diffusion processing operation section 12 is as shown in FIG.
This is a block for adding error data to the pixel of interest. The threshold register 13 is a register for storing threshold data (threshold value) for quantization, and the binary output quantization comparator 14 is provided for the error diffusion processing operation unit 1.
2 is a block for comparing the data after the error diffusion processing which is the output of 2 and the threshold which is the output of the threshold register 13. The error data calculation unit 15 is a block that calculates an error that occurs when the pixel of interest is quantized. When the black side is (+), when the pixel of interest is further quantized to the black side, (−) There is an error. On the other hand, if you make an extra correction to the white side,
(+) Error occurs.

According to the binary error diffusion processing circuit used in the prior art configured as described above, the error diffusion data as the binarized output can be obtained from the previous line error data and the current line data. it can. On the other hand, the dither processing circuit shown in FIG. 7 is composed of threshold registers 21 and 2 and a binary output quantization comparator 22. The threshold register 21 is a register for storing threshold data (dither matrix threshold value), and is structurally the same as the threshold register 13 shown in FIG. Also,
The binary output quantization comparator 22 is a block that compares the dither data with the threshold value that is the output of the threshold register 21, and this is also structurally shown in FIG.
This is the same as the value output quantization comparator 14. According to the dither processing circuit used in the conventional technique configured as described above, it is possible to obtain the dither data as the binarized output from the dither data and the threshold data (dither matrix threshold value).

As described above (as is clear from comparing FIGS. 6 and 7), the threshold register 13 and the quantizing comparators 14 and 22 for 21,2 value output are blocks having the same function. . In the image processing apparatus according to the present invention, paying attention to this point, the binary error diffusion processing circuit used in the related art is provided with a threshold value for supplying to a threshold register and a quantizing comparator for binary output. Two types of data are used, one for binary error diffusion processing and the other for dither processing binary output quantization comparators. By introducing these switching means, the threshold register and binary output quantization comparators can be shared. It is what As a result, it is possible to realize an image processing apparatus that minimizes an increase in space and cost when the image processing section based on the dither method and the image processing section based on the error diffusion method are incorporated in the same apparatus. is there. The same applies to the dual-purpose error diffusion processing and multi-valued error diffusion processing.

[0008]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block configuration diagram of an image processing apparatus according to an embodiment of the present invention. In the figure, symbol 11,
12, 14 and 15 show the same components as shown in FIG. 6, 13A is a threshold register storing both threshold data stored in the threshold registers 13 and 21, and 16 is input data. It is a multiplexer. The input data multiplexer 16 has a function of switching the input current line data to the binary output quantization comparator 14 at the next stage between dither processing data and error diffusion processing data. It should be noted that this switching operation is based on, for example, a control bit based on an instruction from the operator. The image processing apparatus according to the present embodiment enables binary dither output by using the threshold register of the existing binary error diffusion processing circuit and the binary output quantization comparator. As described above, which output is to be obtained is determined by, for example, a control bit based on an instruction from the operator.

FIG. 2 is a block diagram of an image processing apparatus according to another embodiment of the present invention. In the figure, symbol 1
Reference numerals 1, 12, 13A, 14 and 15 represent the same constituent elements as shown in FIG. 6, 17 is a quantizing comparator for multilevel output, and 18 is an encoder. Here, the multi-value output quantization comparator 17 is a block having (n-1) threshold comparison circuits shown in FIG. 5 in the case of n gradations, and the threshold value is a fixed value (in each circuit, (Gradual value)
And the variable value (output of the threshold register 13A). The encoder 18 is a block that encodes the output (“0” or “1”) of the above-described multi-value output quantization comparator 17 into multi-value data, and is called a multi-value data generation unit. You can also FIG. 10 shows an explanatory diagram of this operation. The image processing apparatus according to the present embodiment adds a multi-value output quantization comparator and an encoder to an existing binary error diffusion processing circuit and outputs a multi-value error diffusion processing output in addition to a binary error diffusion processing output. It is possible.

The image processing apparatus according to the above-described embodiment has a peculiar effect in that the information subjected to the binary error diffusion processing is used for image communication and the information subjected to the multi-value error diffusion processing is used for copying. This is the read image information S
It is stored in an AF (Store and Forward) memory, and the image information that has undergone the binary error diffusion processing is transmitted first, and then SA
It is possible to use it again by reading from the F memory and performing multi-valued error diffusion processing to obtain a copy of excellent quality. FIG. 3 is also a block configuration diagram of an image processing apparatus according to another embodiment of the present invention. In the figure, symbols 11 to 18 are shown in FIG.
3 shows the same components as shown in FIG. The image processing apparatus according to the present embodiment enables binary error diffusion processing output and binary dither output by using the threshold register of the existing binary error diffusion processing circuit and the binary output quantization comparator. At the same time, a multilevel output quantization comparator and an encoder are added to enable multilevel error diffusion processing output and multilevel dither output.

FIG. 4 is a block diagram showing the arrangement of an image processing apparatus according to yet another embodiment of the present invention. In the figure,
The symbols 11 to 18 indicate the same constituent elements as shown in FIGS. Reference numeral 19 is an output data multiplexer for selecting multi-valued data after dither processing or error diffusion processing and current line data (raw raw data). The image processing apparatus according to the present embodiment has a multi-value output quantization comparator, an encoder, and an output data multiplexer added to an existing binary error diffusion processing circuit, in addition to multi-value error diffusion processing output and multi-value dither output. Thus, it is possible to output raw data that is not subjected to various processing. Although not particularly mentioned in the above description, there is a possibility that timing mismatch may occur between the plurality of outputs of each embodiment.
In some cases, it is necessary to insert a latch or the like in order to match the processing timing of each output.

This is the same as, for example, in a conventional image processing apparatus having a binary error diffusion processing section and a binary dither processing section separately, the timing correction caused by the different processing route is performed. However, the difference is that the number of delay lines (sub-scanning) and the number of delay pixels required for processing have traditionally been different.
Due to the difference in (main scanning), the timing was adjusted after binarization, whereas when the configuration according to the present invention is adopted, the delay of each "mode" for obtaining a plurality of outputs is reduced. It is possible to eliminate the need for CPU intervention by adjusting to the maximum. Further, it goes without saying that each of the above-mentioned embodiments shows an example of the present invention, and the present invention should not be limited to these.

[0013]

As described above in detail, according to the present invention, the image processing section based on the dither method and the image processing section based on the error diffusion method, or the binary error diffusion processing section and the multi-level error diffusion processing. When the parts and the parts are incorporated into the same device, the common circuit part can be shared, and the remarkable effect that the image processing device in which the increase in the space and the cost is suppressed to the minimum can be realized.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of an image processing apparatus according to an embodiment of the present invention.

FIG. 2 is a block configuration diagram of an image processing apparatus according to another embodiment of the present invention.

FIG. 3 is a block configuration diagram of an image processing apparatus according to another embodiment of the present invention.

FIG. 4 is a block configuration diagram of an image processing apparatus according to another embodiment of the present invention.

FIG. 5 is an explanatory diagram of a threshold comparison circuit included in the quantization comparator for multilevel output used in the embodiment.

FIG. 6 is a diagram showing a binary error diffusion processing circuit used in a conventional technique.

FIG. 7 is a diagram showing a dither processing circuit used in the prior art.

FIG. 8 is a diagram showing an example (2 × 5) of an error diffusion matrix which is a component of a conventionally used binary error diffusion processing circuit.

FIG. 9 is a diagram showing an example of an error diffusion processing operation unit which is a component of a conventionally used binary error diffusion processing circuit.

FIG. 10 is a diagram illustrating a function of an encoder (multi-value data generation unit) used in the example.

[Explanation of symbols]

11: error diffusion matrix (example: 2 × 5), 12: error diffusion processing operation unit, 13, 13A: threshold register, 1
4: Quantization comparator for binary output, 15: Error data calculator, 16: Input data multiplexer, 17: Quantization comparator for multi-value output, 18: Encoder, 19:
Output data multiplexer.

Claims (5)

[Claims] 1. An image processing apparatus capable of binary error diffusion processing and binary dither processing, wherein an output quantization comparator of a binary error diffusion processing circuit, dither data input means, dither data and an error. An image processing apparatus comprising a selection means for selecting diffusion processing data. 2. An image processing apparatus capable of performing binary error diffusion processing and multi-valued error diffusion processing, wherein in addition to a binary output quantization comparator of a binary error diffusion processing circuit, a multi-valued output quantum An image processing apparatus comprising an encoding comparator and an encoding means for outputting the output of the quantizing comparator for multi-value output. 3. An image processing device capable of performing binary error diffusion processing, multi-valued error diffusion processing, binary dither processing, and multi-valued dither processing, wherein a binary output quantization comparator of a binary error diffusion processing circuit. And a dither data input means, a selection means for selecting the dither data and the error diffusion processing data, and a multi-value output quantization comparator and an encoding means for the multi-value output quantization comparator output. Image processing device. 4. The image processing apparatus according to claim 1, further comprising output data selecting means for outputting the processing results and selecting unprocessed data. 5. The image processing apparatus according to claim 1, further comprising means for adjusting a delay time caused by each processing.