JPH06236253A - Bit computing element - Google Patents

Abstract

(57) [Abstract] [Purpose] In bit shift or bit rotation operation, the overflow of shift or rotate result is detected to reduce the error as arithmetic operation. [Structure] The output of the bit shift / rotate calculator 2 is given to the overflow detector 3, and the amplitude limiter 4 corrects the output of the bit shift / rotate calculator 2 according to the judgment output of the overflow detector 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit calculator used in computers, computers and the like.

[0002]

2. Description of the Related Art FIG. 2 shows the configuration of a conventional bit arithmetic unit. In FIG. 2, 1 is an input register, 2 is a bit shift / rotate arithmetic unit, and 3 is an ALU (alithm).
(tic logic unit, arithmetic logic unit),
Reference numeral 4 is an output register.

The data calculated by this bit calculator is
It has a structure that flows in the order of the above symbols.

The operation of the conventional bit arithmetic unit configured as described above will be described below. First, the operands stored in the input register 1 are bit-shifted
In addition to the rotate calculator 2, shift or rotate calculation is performed. Even if the operand is a signed number, overflow check is not performed. The arithmetic result of the bit shift / rotate arithmetic unit 2 is further arithmetically operated by the ALU 3 and written into the output register 4. ALU
3 is not always necessary.

As described above, also with the above-mentioned conventional bit arithmetic unit, it is possible to shift or rotate a numerical value with the bit shift / rotate arithmetic unit.

[0006]

However, in reality, the word length of the output of the bit shift / rotate arithmetic unit is often limited due to economic problems. An overflow occurs when you try to do so, and the overflowing bits are discarded. Therefore, when a shift is used as an arithmetic operation for a numeric value having a significant absolute value or a numeric value having a sign and an absolute value, there is a case where the arithmetic result has no meaning at all due to overflow. was there.

The present invention is intended to solve such a conventional problem, and to perform a left shift or a rotation on a numerical value having a significant absolute value or a numerical value having a significant sign and an absolute value. It is an object of the present invention to provide an excellent bit arithmetic unit capable of reducing an error as an arithmetic operation.

[0008]

In order to achieve the above object, the present invention provides a bit shift or bit rotate arithmetic unit with a digit corresponding to one bit or a plurality of bits corresponding to an unsigned numerical value or a signed numerical value. An overflow detector and an amplitude limiter are provided to correct and output the calculation result when a digit overflows.

[0009]

Therefore, according to the present invention, the overflow detector detects an overflow for the output of the bit shift or rotate arithmetic unit, and when the overflow occurs, the amplitude limiter sets the predetermined number of bits. By the action of substituting the maximum absolute value that can be expressed by, there is an effect that it is possible to reduce the operation error when shift or rotate is used as an arithmetic operation.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the configuration of the first embodiment of the present invention. In FIG. 1, 1 is an input register, and 2
Is a bit shift calculator connected to the input register. Reference numeral 3 is an overflow detector, and 4 is an amplitude limiter, which are respectively connected to the bit shift calculator 2. The overflow detector 3 is also connected to the amplitude limiter 4. Reference numeral 5 denotes an ALU (alithmetic l) connected to the amplitude limiter 4.
6 is an A unit, and 6 is A.
It is an output register connected to LU5.

Next, the operation of the first embodiment will be described. In the first embodiment, first, the operand to be stored in the input register 1 and represented by a signed numerical value is added to the bit shift calculator 2 to perform a 1-bit shift operation. The overflow detector 3 checks whether or not there is an overflow in the shift operation result by the following method.

Since the generality is not lost even if the signed numerical value to be handled is an integer, a signed integer will be described below as an example.

Positive overflow if sign (operand) = 0 and sign (shift operation result) = 1 Negative overflow if sign (operand) = 1 and sign (shift operation result) = 0 sign (X) is an operation for extracting the sign of the numerical value x.

[0014] In the case of positive overflow or negative overflow, the amplitude limiter 4 instead outputs the maximum absolute value that can be represented by a predetermined number of bits. That is, when the number of output bits of the bit shift calculator 2 is N bits, the operation of the following equation is performed.

[0015]

[Equation 1]

The output of the amplitude limiter is further calculated by the ALU 5 and written in the output register 6. In addition, A
LU5 is not always necessary.

As described above, according to the first embodiment,
When the result of the bit shift calculator 2 shifting the signed value overflows, the overflow detector 3 detects it,
Since the amplitude limiter 4 limits the amplitude, when the shift register is used for arithmetic operation, the sign of the operand to be calculated is not lost by any shift, and the error with respect to the original value can be reduced in case of overflow. Has the advantage. Further, according to the first embodiment described above, when the time series data is sequentially processed, the cumulative error can be reduced.

Next, a second embodiment will be described. Second
The configuration of this embodiment is the same as that of the first embodiment. The operation of the second embodiment is different in that the bit shift calculator 2 is capable of multi-bit shift and that the overflow detector 3 is multi-bit compatible.

The overflow detection unit 3 checks whether or not there is an overflow in the shift operation result of the bit shift operation unit 2 by the following method.

As in the first embodiment, the numerical values to be handled will be described as signed integers. sign (operand) = 0, and (overflow bit ≠ 0
If 0 or sign (shift operation result) = 1), it is regarded as a positive overflow.

Sign (operand) = 1, and (overflow bit ≠ 1)
If 1, or sign (shift operation result) = 0), the overflow is negative.

As described above, also in the second embodiment, the same effect as in the first embodiment can be obtained with respect to the unsigned numerical value.

Next, a third embodiment will be described. Third
The configuration of this embodiment is the same as that of the first embodiment. The operation of the third embodiment is that the numerical value handled in the calculation is an unsigned numerical value, that the overflow detector 3 and the amplitude limiter 4 are used.
Is different from the first embodiment in that it corresponds to an unsigned numerical value.

The overflow detection unit 3 checks whether or not there is an overflow in the shift operation result by the bit shift operation unit 2 by the following method.

If the overflow bit = 1, it means overflow. Similar to the first embodiment, since the generality is not lost even if the unsigned numerical value to be handled is an integer, an unsigned integer will be described below as an example.

In the case of overflow, the amplitude limiter 4 outputs the maximum number that can be represented by a predetermined number of bits as a substitute. That is, when the number of output bits of the bit shift calculator 2 is N bits, the operation of the following equation is performed.

[0027]

[Equation 2]

As described above, also in the third embodiment, the same effect as that of the first embodiment can be obtained with respect to the unsigned numerical value.

Furthermore, even if the combination of the second and third embodiments or the bit shift calculator is a bit rotate calculator, the same effect as that of the first embodiment can be obtained. Moreover, even if the configuration in which the order of the amplitude limiter and the ALU is exchanged is used,
The same effect as the first embodiment can be obtained.

[0030]

As is apparent from the above embodiment, the present invention examines the overflow of the output of the bit shift / rotate calculator and limits the range of possible values. Even if a digit overflow occurs as an arithmetic operation, the overflow detector detects it and corrects the value with the amplitude limiter. Therefore, the sign of the operation result is correct and the finite word length is limited. This has the effect of obtaining a calculation result with the smallest calculation error.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a bit arithmetic unit according to first, second and third embodiments of the present invention.

FIG. 2 is a block diagram of a conventional bit arithmetic unit

[Explanation of Codes] 1 Input register 2 Bit shift calculator 3 Overflow detector 4 Amplitude limiter 5 ALU 6 Output register

Claims (3)

[Claims] 1. A bit calculator including a bit shift calculator, an overflow detector for a signed numerical value, and an amplitude limiter. 2. The bit calculator according to claim 1, wherein the bit shift calculator is capable of multi-bit shift. 3. An overflow detector for signed numbers,
Amplitude limiter is an overflow detector for unsigned numbers,
The bit calculator according to claim 1, wherein the bit calculator is an amplitude limiter.