JPH0635670A - Floating point adder - Google Patents

Abstract

(57) [Abstract] [Purpose] A floating-point number adder circuit in which the mantissa is represented by a two's complement, and correct addition without increasing the operation time even for a floating-point number having a negative mantissa to be shifted out. The purpose is to get results. [Structure] An exponent comparison unit 1 that compares the exponents of both operands to obtain a digit shift number and a common exponent for the mantissa of one operand, a digit shift number, and a mantissa digit shift from the mantissa of the one operand. Shift-out detection unit 2 that detects the presence or absence of shift-out, shifters 3 and 4 that perform digit shift for the one mantissa by the mantissa digit shift number, and shift-out detection unit 2 detects shift-out, It has mantissa control units 5 and 6 for setting the value after one digit shift of one operand to 0, and an adder 7 for adding output data of the mantissa control units 5 and 6, and performs mantissa shift for common exponentiation. When a shift-out is detected during the operation, the mantissa in which the shift-out has occurred is set to 0, and then the mantissa addition is performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an adder circuit for floating-point numbers in which a mantissa is represented by a two's complement, and particularly, a correct operation result can be obtained even when a negative mantissa is shifted out by common exponentiation. To a floating point number adder circuit.

[0002]

2. Description of the Related Art When an operation is performed on a floating point number, binary data in which a mantissa is represented by an absolute value is usually used. However, when performing an addition operation, in order to commonly use the adder for subtraction, the absolute value expression is often converted into a two's complement expression at the input of the adder to perform the addition.

FIG. 4 shows data having a 16-bit width and mantissa data represented by 2's complement. The floating point number adder circuit to which the present invention is directed is to add such data.

FIG. 5 is a block diagram of a conventional 2's complement representation floating point number adder circuit. In the figure, 21 is an index comparison unit,
22 is an A shifter, 23 is a B shifter, and 24 is an adder. Operand A [15: 0] (This notation indicates a 16-bit wide binary number A from the least significant bit 0 to the most significant bit 15. The same applies hereinafter) and operand B [15: 0],
The exponent comparison unit 21 calculates A [15:11] -B [15:11] using the exponents A [15:11] and the exponents B [15:11] to judge the magnitude of both exponents. The index comparison unit 21 determines the difference between the indexes, that is, A
[15:11] -B [15:11] is calculated. If this value is negative, the absolute value of the difference is sent to the A shifter 22, and if it is positive, to the B shifter 23. While outputting
The larger index is output as the common index X [15,11]. The mantissa A [10: 0] and the mantissa B [10: 0] are input to the A shifter 22 and the B shifter 23, respectively, and the control signal from the exponent comparison unit 21 causes the mantissa of the smaller exponent to be the exponent. A common index is formed by shifting the difference to the right. The mantissas converted into the common exponent are added by the adder 24, and the common exponent X [15,11] is added to the result to obtain the addition result X [15,11].

[0005]

As described above, when the floating point numbers are added, the exponent is shared, and the mantissa of the operand with the smaller exponent is shifted to the right by the shifter.

This right shift is performed by shifting the bit position of the input data to the right by the shift number and compensating the vacant bit position with the value of the most significant bit of the input data. If the difference between the exponents of both operands is large and the shift number is larger than the existing bit position of the mantissa data to be shifted, the data on the shifted side goes to the right of the least significant digit, and shift-out occurs in which all bits are 0. .

However, when the mantissa on the shifted side is a negative number in the two's complement representation, an error occurs in the calculation result if shift-out occurs. This will be described with reference to the calculation example of FIG.

FIG. 6 (a) of the conventional addition example shown in FIG. 6 is an addition example in which both inputs A and B are positive numbers. When the mantissa of input A is shifted by 10 digits for common exponentiation, the mantissa is changed. "1" of the bit next to the sign bit of is shifted out to 0, and the addition result has the same value as the input B.

FIG. 6B shows a calculation example in the case where the input B has the same value as that in FIG. 6A and the input A has the same absolute value as that in FIG. In this case as well, originally, the shift-out occurs in the input A as in the case of (a), and the mantissa of the operand A after the common exponentiation needs to be 0, but in reality, due to the nature of the barrel shifter, how many bits Even if it shifts, all the bits of the mantissa become 1, and the negative minimum value remains. Therefore, the addition result is the number obtained by subtracting the minimum value from the operand A, which causes a problem that an error occurs in the addition result.

In order to eliminate this calculation error, the input may be right-shifted in the absolute value representation, converted into a two's complement representation and added. In this case, the input data is represented in the absolute value representation. It is necessary to convert the absolute value expression to the two's complement expression between the barrel shifter and the adder,
There arises a problem that the calculation time is additionally required for the conversion time.

The present invention has been made in view of the above problems, and a correct addition result can be obtained without increasing the operation time even for a floating-point number having a 2's complement representation and a negative mantissa to be shifted out. The purpose is to be able to.

[0012]

FIG. 1 is a block diagram showing the principle of the floating point number adding circuit according to the present invention. The above-mentioned problem is, as shown in FIG. 1, an addition circuit for a floating-point number having a mantissa represented by two's complement, and comparing the magnitudes of exponents of both operands with a digit shift number for the mantissa of one operand. An exponent comparison unit 1 that obtains an exponent, the digit shift number, a shift-out detection unit 2 that detects the presence or absence of shift-out at the time of mantissa digit shift from the mantissa of the one operand, and the mantissa digit shift number When the shifters 3 and 4 that shift the digits to the mantissa and the shift-out detection unit 2 detect the shift-out, the mantissa control units 5 and 6 that set the value after the digit shift of the one operand to 0, and the mantissa control And an adder 7 for adding the output data of the units 5 and 6, and when a shift-out is detected when performing the mantissa shift for common exponentiation,
The floating-point number adding circuit of the present invention is characterized in that the mantissa resulting from the shift-out is set to 0 before the mantissa addition is performed.

[0013]

When one of the mantissas of the operand is shifted out by digit shift, the operand forcibly set to 0 by the mantissa controller is input to the adder regardless of the output of the barrel shifter. Therefore, even if one of the operands is a negative mantissa that causes shift-out, a correct operation result can be obtained. Further, since it is not necessary to convert the absolute value representation to the two's complement representation in front of the adder, the data of the two's complement representation can be directly input to the adder circuit, so that the data of the two's complement representation is handled. It can be directly applied to the arithmetic device, and the arithmetic time can be shortened by the conversion time.

[0014]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 2 is a configuration diagram of an embodiment of the present invention, and FIG. 3 is a diagram showing an addition example according to the embodiment of the present invention.

The adder circuit of FIG. 2 adds operands A and B, which are 16-bit wide floating point numbers having a mantissa represented by a two's complement, and outputs an addition result X having the same format. . In the data format of the operand and the operation result, as described above with reference to FIG. 4, the upper 5 bits [15:11] represent the exponent and the lower 11 bits [10: 0] represent the mantissa in the two's complement representation. The most significant bit [10] of the mantissa is a sign bit, and takes a value of "0" for positive numbers and "1" for negative numbers.

In FIG. 2, 11 is an exponent comparison unit, 12 is a shift-out detection unit, 13 is a barrel shifter A, 14 is a barrel shifter B, 15 and 16 are AND gates corresponding to the mantissa control unit of FIG. 1, and 17 is 11 bits. It is an adder.

The exponent comparing unit 11 compares the exponents of both operands, outputs the larger exponent as the common exponent X [15:11], and outputs the shift number of the operand having the smaller exponent.

To both shifters 13 and 14, 6-bit shift number data, which is the difference between the exponents from the exponent comparing section, is added as a control signal, and the input mantissa data is right-shifted according to the shift number.

The shift-out detector 12 receives 10 bits excluding the sign bit of the mantissa of both operands, compares the shift number data from the exponent comparator 11 with the value of the mantissa on the shift side, and after shift It is detected whether or not a shift-out in which the mantissa data of is required to be 0 occurs, and when the shift-out occurs, the control signal "0" is output to the AND gate on the operand side.

The operation of each unit will be described with reference to FIG. 6B and the calculation example of FIG. 2 using the same numerical values as the input data. The exponent comparison unit 11 calculates the exponent A [15:11] and the exponent B of both operands.
Input the [15:11] exponent bit and enter A [15:11] -B [1
5:11], the magnitude of the exponent is determined, and the larger exponent is output as the common exponent X [15:11]. In this case, since the index of A is 2 and the index of B is 12, binary data of 12 is output as the common index X [15:11]. Since the difference between the exponents is -10, the shift number 10 is output to the A shifter 12 as a control signal, and 0 is output to the B shifter 13. . When the difference between the exponents is positive, the shift number is output to the B shifter, and 0 is output to the A shifter 12.

The mantissa of the operand A is shifted to the right by 10 bits by the A shifter 13. However, since the mantissa of the operand A is a negative number in the two's complement representation, the output data of the A shifter does not become 0, but all the output data. It becomes bit "1".

The shift-out detection unit 12 recognizes that the number of shifts (shiftable number) at which shift-out does not occur is 9 because the low-order bits "0" of the mantissa of the operand A are 9 bits. Number of shifts 9 and index comparison unit 11
The shift-out detection signal "0" is output to the A-side AND gate 15, and the shift-out detection signal is output to the B-side AND gate 16 that does not shift the digit by "1". The AND gate 15 on the A side sets all the shifted data input from the A shifter 13 to "0" and inputs it to the A input of the adder 17, while the AND gate 16 on the B side inputs the B shifter 14 without shifting. The mantissa B [15:11] is passed through as it is and supplied to the B input of the adder 17, respectively.

The adder 17 adds the A input and the B input, uses the addition result as a mantissa, and outputs the operation result with the common exponent added as the output X [15: 0] of the addition circuit. As described above, even if the correct shift-out result is not obtained by the 10-bit right shift of the negative mantissa of the operand A and all the bits of the A shifter output become "1", the adder 17 obtains the correct shift-out result. It is understood that the correct operation result can be obtained because the data of all bits "0" is input.

[0024]

As described above, according to the present invention, 2
In the floating-point number adder circuit using the complement expression of, when shift-out occurs due to the right shift of the mantissa for common exponentiation, the mantissa is set to 0 and the addition is performed, so that accurate addition is always performed regardless of the input data. The effect is that it can be done.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of a floating point number addition circuit of the present invention.

FIG. 2 is a configuration diagram of an embodiment of the present invention.

FIG. 3 is a diagram showing a calculation example according to an embodiment of the present invention.

[Figure 4] Input / output data format

FIG. 5 is a configuration diagram of a conventional 2's complement representation floating point number addition circuit.

FIG. 6 is a diagram showing a conventional calculation example.

[Explanation of symbols]

1,11 ... Index comparison section, 2,12 ... Shift-out detection section, 3,13 ...
A shifter, 4, 14 ... B shifter, 5, 6 ... Mantissa control unit, 15, 16
… AND gate, 7,17… Adder

Claims (1)

[Claims] 1. An adder circuit for a floating point number having a mantissa represented by two's complement, wherein exponent comparison is performed by comparing magnitudes of exponents of both operands to obtain a digit shift number and a common exponent for the mantissa of one operand. Part (1), the digit shift number, and a shift-out detection part (2) that detects the presence or absence of shift-out during mantissa digit shift from the mantissa of the one operand; A shifter (3,4) that shifts digits to the other side, and a mantissa control unit that sets the value after digit shift of one of the operands to 0 when the shift-out detection unit detects shift-out
An adder (7) for adding the output data of the mantissa control unit (5, 6) to (5, 6)
And, when a shift-out is detected when mantissa shift is performed for common exponentiation, the mantissa in which the shift-out has occurred is set to 0 before the mantissa addition is performed. Floating point adder circuit.