JPH0624347B2 - M2 modulation signal synchronization device - Google Patents

Description

BACKGROUND OF THE INVENTION Technical Field The present invention relates to M ² modulation signal synchronization apparatus for adding a synchronization signal M ² modulated information signal.

BACKGROUND ART Digital in a PCM (pulse code modulation) system in which an analog signal such as a voice signal is converted into, for example, a binary code and transmitted or recorded in a recording medium, and received or reproduced to decode the original analog signal again. Data is formed by a plurality of continuous frames, and when data for a plurality of channels is included, it is often time-division multiplexed. When receiving or reproducing such digital data, unless the decoding is started in synchronization with the arrival of the first data in one frame, the analog signal obtained by the data being misconnected to another channel and decoded is the original analog signal. It will be different from the signal. Therefore, it is usual that a sync signal having a predetermined bit pattern consisting of a plurality of bits is provided at the beginning of each frame, and the frame is synchronized by this sync signal.

On the other hand, various modulation methods have been proposed for recording or transmitting digital data at high density. These various modulation methods, especially the method capable of recording or transmitting at a higher density than other methods, divides a data string into consecutive m-bit blocks and divides the m-bit binary code in each block by n.
NRZI, which is a basic modulation method of a code conversion for converting a binary code of bits and a binary code string obtained after the code conversion
(Non-Return to Zero Inverse) or NR
It can be treated as a combination with Z modulation.

Generally, a modulation method for high density recording on a recording medium is required to satisfy the following conditions.

(1) The minimum inversion interval (hereinafter referred to as Tmin) of the write signal waveform to the recording medium obtained after the modulation is long and the maximum inversion interval (hereinafter referred to as Tmax) is short. If Tmin is long, interference between adjacent inversions is small, and high density is possible, and if Tmax is short, self-synchronization becomes easy.

(2) The detection window width (hereinafter T), which is the time that can be used to detect the recording bit from the signal reproduced from the recording medium.
Write W. ) Is wide. In magnetic recording, the recording bit is detected by detecting the peak of the reproduced signal waveform. However, the TW is a permissible value for the deviation of the peak position, and therefore a wider TW is suitable for high-density recording. Further, in the recording / reproducing apparatus using the laser light, if the TW is wide, the allowable range of the deviation of the detection position becomes wide, and the amplitude at the detection point becomes large, so that the noise margin becomes large.

(3) DC and low-frequency components do not exist in the write signal to the recording medium obtained after modulation. In a device having a transmission system that cannot transmit DC and low frequency components, the waveform of a signal containing these components will be distorted. Further, in the recording / reproducing apparatus using laser light, these components reduce the reliability of the servo system. On the contrary, if these components do not exist, low-frequency noise and drift can be removed by the high-pass filter.

The MFM (Modified Frequency Modulatio) is used as a modulation system that has been proposed so far and satisfies the condition (1).
n) method is known. The code conversion in this MFM system is performed as follows. That is, for example, each bit d ₀ in the input data bit sequence as shown in FIG. 5 (A) is converted into a 2-bit binary code a ₀ b _{0 according} to the state of the bit d _{−1 immediately} before, and the same diagram ( A code sequence as shown in B) is obtained. The obtained code sequence is modulated by NRZI to obtain a write signal S _{1 as} shown in FIG.

Here, in order to estimate the DC component in the write signal obtained as described above, the accumulated charge is obtained. The accumulated charge is +1 for the minimum positive pulse width, −1 for the minimum negative pulse width, and ± 2 for the doubled pulse width.
It is obtained by counting charges by assuming charges.
The amount of the DC component can be estimated by the magnitude of this accumulated charge. Now, in the write signal shown in FIG. 5C, the total of the high level sections in the portion corresponding to the input data series "0110" is 1T and the total of the low level sections is 3T, so the accumulated charge Becomes -2. still,
T represents the reciprocal of the data bit transfer rate (bit period). Therefore, when the input data series is a series of "0110", the accumulated charge may be negative infinity, and a direct current component may exist.

In the MFM method, the input data bit sequence can be classified into the following five types.

(a) "00" (b) "01 ... 10" (number of consecutive 1s: odd number) (c) "01 ... 10" (number of consecutive 1s: even number) (d) "1 ... 1" ( Number of consecutive 1s: odd number) (e) “1 ... 1” (Number of consecutive 1s: even number) DC signal is generated only in the write signal corresponding to the sequence (c) of the above 5 types of sequences .

Therefore, an M ² (Modified Miller) method or the like has been proposed as a modulation method that does not generate a DC component in the write signal. In the M ² system, the code conversion for the sequence (c) is improved. That is, in the M ² system, almost the same conversion as in the MFM system is performed, but when an even number of bits “1” are consecutive after the bit “0” and the accumulated charge up to the bit “0” is not zero. Is converted such that the last bit "1" corresponds to non-inversion. For example, each bit in the input data bit sequence as shown in FIG. 6 (A) is converted into a 2-bit binary code as shown in FIG. 6 (B). The obtained code sequence is NRZI
And the write signal S as shown in FIG.
₂ is obtained. As is clear from FIG. 6C, in the M ² method, the accumulated charge of the write signal becomes zero and no DC component is generated. However, in this M ² system, Tmax is 3
T, which is longer than Tmax (= 2T) in MFM.

It is desirable to add a synchronizing signal so that a direct current component is not generated when recording / reproducing or transmitting digital data by the M ² system so that synchronization can be surely achieved.

SUMMARY OF THE INVENTION It is an object of the present invention to synchronize M ² modulation signals without causing a direct current component in a write signal when recording and reproducing or transmitting digital data by the M ² system. It is to provide a device.

According to the M ² modulation signal synchronization device of the present invention, a bit having a bit value “0” in a data sequence that can be divided into a plurality of blocks containing different types of data is determined according to the bit value of the bit immediately before the bit. "00" and "1"
2 having a bit pattern of either "0"
It is converted into a binary code of bits and the bit having the bit value "1" in the data sequence has one of the bit patterns of "01" and "00" depending on the state of the bit string before the bit. M ² equipped with M ² modulation means for converting into a 2-bit binary signal and corresponding “1” of the obtained data series to inversion and “0” to non-inversion to obtain an M ² modulation signal A modulation signal synchronization device, wherein a period corresponding to a 2.5-bit width is generated when a time corresponding to the type of data has elapsed in each part of the modulation signal corresponding to each of the plurality of blocks. It is characterized by having a sync signal adding means for adding a signal which is inverted a predetermined number of times as a sync signal.

Embodiment Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS. 1 to 4.

FIG. 1 is a block diagram showing an M ² modulation signal synchronization device according to the present invention. In the figure, each bit in a data bit sequence including information such as audio information is sequentially applied to the data input terminal of the buffer memory 1 at a predetermined cycle. The address signal and the mode control signal of the buffer memory 1 are output from the control circuit 2. The control circuit 2 is supplied from the clock generation circuit 3 with a clock c _{1 which} is generated in synchronization with the data bit applied to the data input terminal of the buffer memory 1. The control circuit 2 changes the address signal and the mode control signal so that the data is sequentially written to the buffer memory 1 bit by bit in synchronization with the clock c ₁ and the written data is sequentially read bit by bit. The data generation command signal is generated immediately before the start of reading the data of a predetermined number of bytes and immediately after the end of the reading.

The data read from the buffer memory 1 is sequentially applied to one input terminal of the multiplexer 4 bit by bit. The output of the data generator 5 is applied to the other input terminal of the multiplexer 4. The data generator 5 is, for example, R
The OM is formed, and the data written in advance in the ROM is sequentially read out and output bit by bit over the existence period of the data generation command signal output from the control circuit 2. There is. A data generation command signal output from the control circuit 2 is applied to the data switching control input terminal of the multiplexer 4. One of the output data of the buffer memory 1 and the output data of the data generator 5 is selectively output from the multiplexer 4 according to the output of the control circuit 2. The output of this multiplexer 4 is M ²
It is applied to the data input terminal of the recording bit generator 6. M
² A clock is applied to the clock input terminal of the recording bit generator 6.
c ₁ is being applied. The M ² recording bit generator 6 outputs “0” when the number of adjacent “1” s between “0” and “0” in the input bit sequence is an even number, for example.
A P (A) generator that generates (A) and an output P (B) that becomes "0" when the accumulated charge up to the first "0" of "0" that surrounds "1" is zero. P (B) generator and a converter which is composed of a ROM or the like and performs signal conversion based on a conversion table as shown in the table below.

From the converter in this M ² recording bit generator 6, a ₀ ,
Data consisting of each bit of b ₀ is output and applied to the parallel input terminal of the 2-bit shift register 7. A clock is applied to the parallel set clock input terminal of the shift register 7.
and c ₁ is applied to the shift clock input terminal of the shift register 7 the clock c ₂ which is output at a 1/2 cycle of the clock c ₁ from the clock generation circuit 3 is applied. Two bits of output data of the converter in the M ² recording bit generator 6 are simultaneously set in the shift register 7 by the clock c ₁ . After that, each bit a ₀ , which forms the data set in the shift register 7,
b ₀ is sequentially output from the serial output terminal by the clock c ₂ and supplied to one input terminal of the AND (logical product) gate 8. The output of the gate signal generating circuit 9 is supplied to the other input terminal of the AND gate 8. The gate signal generation circuit 9 includes, for example, a counter whose count value changes according to the clock c ₂ over the existence period of the data generation command signal output from the control circuit 2, and the count value of this counter becomes equal to a predetermined value. When the output is low level.

The output of the AND gate 8 is applied to one input terminal of the exclusive OR gate 10. The output of the exclusive OR gate 10 is applied to the D input terminal of the D-type flip-flop 11. The clock c ₂ is applied to the clock input terminal of the D-type flip-flop 11. The Q output of the D flip-flop 11 is applied to the other input terminal of the exclusive OR gate 10. These exclusive OR gate 1
The 0 and D flip-flop 11 form an NRZI modulator, and the Q output of the D flip-flop 11 is output as a write signal.

In the above configuration, it is assumed that these data are written in advance in the ROM so that the data generator 5 sequentially outputs the following data when the control circuit 2 outputs the data generation command signal. . That is, when the data generation command signal is present, the data sequentially output from the data generator 5 is the data D ₁ for bit synchronization and the address mark 1
Data _{D 2} to form the data _{D 3} as identification data, data _{D 4} to form a gap, data _{D 5} for bit synchronization, data _D 6 to form the address mark 2,
And the data D ₈ forming a gap, the data generation command signal disappears at the end of the output of the data D _{1 to} D ₆ , and a predetermined number of bytes of data D ₇ are read from the buffer memory 1. When the data generation command signal is generated again, a write signal for writing data in each sector on the recording disk is obtained in the format as shown in FIG.

As shown in FIG. 2, the data D _{1 to} D ₃ are written in the ID field indicating the address, and the data D _{5 to} D ₇ are written in the data field. The data D ₂ forming the address mark 1 is [21] H, [FF] H, [2].
1] H and [FO] H. This 4-byte data D
[21] H in ₂ is data for generating a synchronization signal, and [FF] H is data for identifying an address mark. The 4-byte data D ₆ forming the address mark 2 includes [08] H, [AA] H, [08] H,
[A5] H. [08] H in the 4-byte data D ₇ is data for generating a synchronization signal,
A] H is data for identifying the address mark.

When the data [21] H of the synchronizing signal generator are sequentially outputted bit by bit from the most significant bit as shown in FIG. 3 (A) from the data generator 5, Figure 4 from M ² recording bit generator 6 ( The bit sequence as shown in B) is sequentially output every 2 bits. The output data of the M ² recording bit generator 6 is sequentially ANDed bit by bit by the shift register 7.
It is applied to one input terminal of the gate 8. The output of the shift register 7 corresponds to the data bit in FIG. 3 (C).
A signal obtained by synthesizing the signal as shown in FIG. 3 and the signal as shown in FIG. 3D corresponding to the clock bit. Here, the shift register 7 outputs 9th and 13th bits from the most significant bit in the output data corresponding to [21] H.
When the output of the gate signal generator 9 is set to the low level as shown in FIG. 3 (E) when the second bit is output, the output of the shift register 7 corresponding to [21] H is output from the AND gate 8. The data as shown in FIG. 3 (F) obtained by setting the clock bits corresponding to the 9th and 13th bits from the most significant bit to "0" are sequentially output bit by bit. By applying the output data of the AND gate 8 to one input terminal of the exclusive OR gate 10, after the time corresponding to 5 cycles of the clock C ₂ has elapsed from the time of generation as shown in FIG. 3 (G). 2.5
A write signal S ₃ that inverts at a cycle corresponding to the bit width is obtained.

Further, when the data [08] H for generating the synchronization signal is sequentially output from the data generator 5 bit by bit from the most significant bit as shown in FIG. 4 (A), the M ² recording bit generator 6 A bit sequence as shown in FIG. 4B is sequentially output every 2 bits. At this time, the output of the shift register 7 is a signal obtained by synthesizing the signal shown in FIG. 4 (C) corresponding to the data bit and the signal shown in FIG. 4 (D) corresponding to the clock bit. Becomes Here, when the shift register 7 outputs the 7th and 13th bits from the most significant bit in the output data corresponding to [08] H, the output of the gate signal generator 9 is shown in FIG.
If it is set to the low level as shown in, the clock bit corresponding to the seventh and thirteenth bits from the most significant bit in the output data of the shift register 7 corresponding to [08] H from the AND gate 8 is set to "0". The data obtained as shown in FIG. 4 (F) is sequentially output bit by bit. Then, as shown in FIG. 4 (G), after 2.5 cycles of the clock C ₂ have elapsed from the time of occurrence, 2.5
A write signal S ₄ that inverts at a cycle corresponding to the bit width is obtained.

These write signals S ₃ and S ₄ are written in the ID field and data field of each sector as synchronization signals when the write data S of the recording disk is reproduced.
_{If the} decoding is started when each bit pattern of S ₃ and S ₄ is detected, the write signals S ₃ and S ₄ as the synchronization signals correspond to the irregular pattern in the M ² modulation method, and thus the data and It is possible to reliably achieve synchronization without misidentifying the synchronization signal. Further, since the bit patterns of the write signals S ₃ and S ₄ are different from each other, it is possible to discriminate between the address mark of the ID field and the address mark of the data field only by the synchronizing signal, and the next identifying data [FF ], H, [AA] H can be reproduced without error even if the portion corresponding to H is dropped out due to dropout.

The case where information is recorded by alternately writing the data in each ID field of the recording disk and writing the data in each data field has been described above, but only the data of the ID field of all the sectors of the recording disk is described. ID written in advance and written in advance
The present invention can also be applied to the case where the data generation command signal is generated after the data in the field is read to write the data in each data field.

EFFECTS OF THE INVENTION As described in detail above, the M ² modulation signal synchronization device according to the present invention provides a time corresponding to the type of post-occurrence data to each part of the modulation signal corresponding to each of a plurality of blocks containing different types of data. Since a signal that is inverted a predetermined number of times in a cycle corresponding to a 2.5-bit width is added as a synchronizing signal when the time elapses, the accumulated charge in the synchronizing signal section can be made zero and the generation of a DC component can be prevented. In addition, since the bit pattern of the sync signal is an irregular pattern in the M ² system, it is possible to reliably achieve synchronization without misidentification of the sync signal and data. In addition, since the bit patterns of the sync signal added to a plurality of blocks containing different types of data are different from each other, the blocks can be identified only by the sync signal, and erroneous data processing due to dropout can be performed. Can be prevented. Further, since the inversion interval in the synchronization signal section is equal to or less than the maximum inversion interval in the M ² method, self-synchronization is not made difficult. Further, the synchronization signal can be easily generated only by adding a circuit for setting the clock bit to "0" in the encoder.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing an M ² modulation signal synchronizing device according to the present invention, FIG. 2 is a diagram showing an example of a format for writing data on a recording disk, and FIGS. 3 and 4 are FIG. 5 is a diagram showing an operation of each unit when a synchronization signal is generated in the apparatus of FIG. 1, FIG. 5 is a diagram showing an example of code conversion in the MFM system, and FIG. 6 is a diagram showing an example of code conversion in the M ² system. It is a figure.

Claims (2)

[Claims] 1. A bit value "0" in a data sequence that can be divided into a plurality of blocks containing different types of data.
Bit of the data sequence is converted into a 2-bit binary code having a bit pattern of either "00" or "10" according to the bit value of the bit immediately before the bit. Data obtained by converting a bit of value "1" into a 2-bit binary signal having a bit pattern of either "01" or "00" according to the state of the bit string before that bit An M ² modulation signal synchronization device comprising M ² modulation means for obtaining an M ² modulation signal by associating "1" of a sequence with inversion and "0" with non-inversion, wherein: A synchronization signal is added to each of the portions corresponding to each of the plurality of blocks as a synchronization signal, which is a signal that is inverted a predetermined number of times in a cycle corresponding to a 2.5-bit width when a time corresponding to the type of data has elapsed after generation. An M ² modulation signal synchronization device having means. ^2. The M ² modulation signal synchronization device according to claim 1, wherein the predetermined number of times is 2.