JPH0624355B2 - Data receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] A data receiving apparatus for sampling data at a timing according to the start-stop distortion, and an object thereof is to correctly receive a data signal even when the start-stop distortion has a skewness of more than 50%. And stores the start bit and the stop bit in the start-stop transmission received data at a speed higher than the transmission speed to obtain these sampling patterns, and the reference pattern of each of the start bit and the stop bit. Means, means for comparing the sampling pattern with each reference pattern, means for instructing a change timing of a clock according to a result of the comparison between the both, and a clock having a change timing according to the instruction. Means and the received data signal, the clock And means for obtaining data by sampling at the change timing.

[Industrial application field]

The present invention relates to a data receiving device, and more particularly to a data receiving device that samples data at a timing according to start-stop distortion.

In data transmission, signal distortion occurs due to the influence of the transmission path. In the case of start-stop transmission, this distortion is called start-stop distortion.

[Conventional technology]

In asynchronous transmission, there is generally no independent reception timing signal. Therefore, in the data receiving device, the received data signal is sampled based on only the received data signal at the timing when a predetermined time has elapsed from the signal change point.

For example, assume that data transmission of the data signal D as shown in FIG. 5 is performed. Since this transmission rate (for example, 300 bps) can be known in advance, the data receiving device uniquely forms the clock CLK having a rate (frequency) that is, for example, eight times the transmission rate.

When the data transmission of the data signal D is performed without the start-stop distortion, the received data signal RD1 has the same waveform as the data signal D. The data receiving device receives the received data signal RD.
When 1 changes from "1" to "0", the received data signal RD is 4 clocks after the changed point (signal change point).
1 is sampled and thereafter sampling is repeated every 8 clocks. Thereby, for example, serial data "01 ..." Is obtained.

By doing so, the sampling of the reception data signal RD1 can be performed at the approximate center of each bit. In addition, it is sufficiently faster than the transmission speed (8
Double, 16 times, 32 times, ...) By forming and using the clock CLK, the margin for the start-up distortion is improved.

[Problems to be Solved by the Invention]

According to the above-mentioned conventional technique, even if the clock CLK that is sufficiently higher than the transmission rate is used, the start-up distortion can be correctly received only up to less than 50%.

For example, it is assumed that when data transmission of the data signal D is performed, the received data signal becomes RD2 shown in FIG. 5 due to start-stop distortion. This start-up distortion is a distortion that widens the "1" level width (narrows the "0" level width), and its skewness exceeds 50%. In this case, the result of sampling 4 clocks after the signal change point should be "0" although "1" should be detected.

It is also assumed that the received data signal of the data signal D becomes like RD3 shown in FIG. 5 due to the start-stop distortion. This start-up distortion is a distortion that widens the "0" level width (narrows the "1" level width), and its skewness exceeds 50%. In this case, the sampling result after 12 clocks from the signal change point should be "1", but "0" is detected.

As described above, according to the conventional technique, although the skewness of the start-and-stop distortion is indefinite, the sampling position (timing) is substantially fixed at the approximate center of each bit, so that the skewness is There was a problem that it could not be received correctly when it exceeded 50%.

An object of the present invention is to provide a data receiving device capable of correctly receiving a data signal even when the skewness of the start-stop distortion exceeds 50%.

[Means for Solving the Problems]

FIG. 1 is a block diagram of the principle of the present invention, showing a data receiving apparatus according to the present invention.

In FIG. 1, 1 is a sampling circuit, 2 is a register, 3 is a pattern comparison circuit, 4 is a timing generator, 5 is a clock generator, and 6 is a conversion circuit.

The received data signal RD is transmitted in an asynchronous manner from the data transmitting device via the transmission path and received by the data receiving device. In start-stop transmission, a data signal is generally a start bit consisting of 1 bit "0",
It consists of 1.5 or 2 stop bits consisting of "1", and a start bit and an arbitrary number of data bits (n bits) surrounded by the stop bits.
Therefore, the reception data signal RD includes a start bit and a stop bit, and if start-stop distortion is present, it is "0".
The level width and the "1" level width change according to the skewness.

The sampling circuit 1 is means for sampling at least the start bit and the stop bit of the reception data signal RD at a speed higher than the transmission speed of the reception data signal RD to obtain these sampling patterns. Since the transmission rate can be known in advance, sampling is performed at a predetermined rate of 8 times, 16 times, 32 times, ... Of the transmission rate.

The register 2 is means for storing (memorizing) the reference pattern of the start bit and the stop bit. The reference pattern shows a sampling pattern when there is no start-stop distortion, and is a pattern corresponding to the sampling at the predetermined speed.

The pattern comparison circuit 3 is a means for comparing the sampling pattern and the reference pattern for each of the start bit and the stop bit, and as a result, knowing the presence / absence, the type and the skewness of the start / stop distortion.

The timing generator 4 is means for instructing a change timing of a clock CLK, which will be described later, according to the result of comparison in the pattern comparison circuit 3. The change timing is, for example, the timing at which the clock CLK changes from “1” to “0”, and is used as the sampling timing of the data bit of the reception data signal RD.

The clock generator 5 is the timing generator 4
Clock C with change timing according to instructions from
It is a means for forming LK. The clock CLK has the same speed (cycle) as the transmission speed of the received data signal RD.

The conversion circuit 6 is means for obtaining the data by sampling the received data signal RD using the clock CLK from the clock generator 5 at the change timing from "1" to "0". This sampling is performed especially for the data bits of the received data signal RD. The conversion circuit 6 converts the n-bit serial data obtained by this sampling into n-bit parallel data (serial-parallel conversion) and sends it out.

[Action]

FIG. 2 is a diagram for explaining the operation of the present invention, in which the start bit and the stop bit each consist of 1 bit of “0” and 1 bit of “1”, and the sampling in the sampling circuit 1 is performed at a speed eight times the transmission speed. It shows the case where it is performed. That is, the sampling is performed on the received data signal RD.
This is performed by using a clock having a frequency eight times as high as the clock CLK having the same transmission speed as that of (8) .times.8 CLK (FIG. 2 (D)).

(1) When there is no start-up distortion (in FIG. 2 (A)) The sampling circuit 1 clocks 8 CL for the start bit and stop bit of the received data signal RD.
Sampling patterns "00000000" and "111111" consisting of eight samples are obtained by sampling every change timing from "1" to "0" using K.
Get 11 ". On the other hand, the register 2 has a reference pattern "00" of the start bit and the stop bit consisting of eight samples so as to correspond to the sampling pattern.
"000000" and "11111111" are stored.

Therefore, the pattern comparison circuit 3 knows that there is no start-up distortion because the sampling pattern and the reference pattern match.

The timing generator 4 receiving the result of this comparison
A signal for instructing the change timing is sent. Receiving this, the clock generator 5, as shown in FIG. 2 (A), has a clock C whose change timing is approximately in the center of the cycle of the clock (duty is 50%).
Form LK.

(2) Autism distortion is present (in Fig. 2 (B) and (C))
Case In the case of FIG. 2B, the sampling patterns of the start bit and the stop bit are “00001111” and “11”, respectively.
It becomes 111111 ". Therefore, although the two patterns of the stop bit match, the start bit does not match because the sampling pattern includes "1". From this fact, the pattern comparison circuit 3 has a start-up distortion that widens the "1" level width, and the distortion degree is about 50 (4/8)% from the number of "1" s in the start bit sampling pattern. To know that. As a result, the clock CL of FIG.
Clock CLK whose change timing is faster than K by t1
Is formed.

On the other hand, in the case of FIG. 2 (C), since the pattern comparison circuit 3 does not match because the sampling pattern of the stop bit includes "0", there is an asymmetrical distortion that widens the "0" level width, and the distortion degree thereof. Find out about 25%. As a result, a clock CLK whose change timing is later than the clock CLK of FIG. 2A by t2 is formed.

The signal sent by the timing generator 4 is actually formed by referring to a table described later.

As described above, the conversion circuit 6 samples the data bits of the reception data signal RD by forming the clock CLK having the change timing according to the presence / absence of the asymmetrical distortion, the type, and the skewness, and using this as the sampling timing. Corresponding to changes in the "1" and "0" level widths due to start-stop distortion (not fixed to the center of each bit), it can always be performed in the center of the period of each level. Therefore, correct data can be obtained even when the start-stop distortion varies and exceeds 50%.

Even when the start-stop distortion is 50% or less, according to the present invention, the data can be sampled at the timing when the data is sufficiently determined, so that the correct data can be surely obtained and the data transmission can be performed. Effective for high reliability.

〔Example〕

FIG. 3 is a block diagram of an embodiment, showing a data receiving device.

In FIG. 3, 7 is a receiver, 8 is a synchronization circuit, 9 is a start detection circuit, 31 is a pattern comparison and clock timing instruction signal generation circuit (hereinafter, instruction circuit), which is used for the pattern comparison circuit 3 and the timing generator 4. Reference numeral 51 is a clock generator, reference numeral 52 is a frequency dividing circuit, which corresponds to the clock generator 5 together with the clock generator 51.

The data signal RD 'transmitted from the data transmitting device is received by the receiver 7 of the receiving device, and is synchronized with the clock x8 CLK in the synchronizing circuit 8 including a flip-flop circuit to be the received data signal RD. Where 1
Each data signal RD 'is composed of 6 bits including a start bit composed of 1 bit "0", a stop bit composed of 1 bit "1", and 4 data bits surrounded by these. Also, the clock × 8 CLK is
A clock that is uniquely formed on the data receiving device side.
The transmission rate of the data signal RD 'is eight times (frequency).

The start detection circuit 9 detects the start of the start bit of the reception data signal RD. That is, the received data signal RD is kept at "1" for 6 bit time (start bit + data bit + stop bit) (mark state)
After that, the timing of first changing from "1" to "0" is detected as the start of the start bit, and the data fetching start signal is transmitted.

A sampling circuit (hereinafter referred to as a shift register) 1 including a shift register that receives a data capture start signal captures one reception data signal RD. At this time, clock × 8
CLK is used as a clock for sampling and shifting. That is, the shift register 1 has a clock ×
The received data signal RD is sampled at each change timing of 8CLK from "1" to "0", and clock x 8CL
Shift in synchronization with K. As a result, the shift register 1
A state (bits) of 48 (= 8 × 6) is fetched in.

After the end of this sampling, the instruction circuit 31 fetches the first 8 bits and the last 8 bits of the shift register 1 as sampling patterns of the start bit and the stop bit, respectively, and fetches these reference patterns from the register 2. Then, the instruction circuit 31
Compares the two patterns to know the presence / absence of the asymmetrical distortion, the type, and the skewness, and forms a change timing instruction signal corresponding to this.

The frequency dividing circuit 52 is basically a clock × 8 CLK (second clock
(See FIG. 2D) is divided into 1/8 to form a clock CLK with a duty of 50% (see FIG. 2A). Then, the frequency dividing circuit 52 receives the change timing instruction signal,
In response to this, the change timing (duty) of the clock CLK from "1" to "0" is left unchanged or changed (see FIGS. 2B and 2C).

Here, as is clear from FIGS. 2A to 2C, there is a fixed relationship between the skewness or sampling pattern of the received data signal RD and the change timing or duty of the clock CLK. . Therefore, by preliminarily obtaining this relationship, as shown in FIG. 4, a table showing the sampling pattern and the clock CLK of the change timing corresponding thereto is created and stored in the memory (not shown). The instruction circuit 31 refers to the table using the sampling pattern, knows the clock CLK corresponding to the sampling pattern, and forms the timing change instruction signal based on this.

In this table, “∇” indicates the change timing of the clock CLK, that is, the sampling timing of the received data signal RD. As can be seen from this table, the relationship is, for example, "when there is one" 1 "in the eight samples of the start bit, the" 1 "level width of the clock CLK is" 1 "when the duty is 50%. Level width from 1/8
It will be narrowed only. "

Although not shown, this table shows all expected sampling patterns, that is, the start bits from “00000000” to “01111111” and the stop bits from “11111111” to “00000001”. The corresponding clock CLK is shown.

Upon receiving the clock CLK, the conversion circuit 6 samples the data bits of the reception data signal RD. As a result, 4-bit serial data can be obtained correctly. The conversion circuit 6 converts 4-bit serial data into 4-bit parallel data and sends it out as data.

〔The invention's effect〕

As described above, according to the present invention, in a data receiving device that receives a data signal transmitted in an asynchronous manner, by knowing the presence / absence, type, and skewness of the asymmetrical distortion, data sampling is performed at a timing corresponding to this. Since it can be performed, correct data can be obtained even when the start-up distortion exceeds 50%, and the reliability of data transmission can be improved regardless of the quality of the transmission path.

[Brief description of drawings]

FIG. 1 is a block diagram showing the principle of the present invention, FIG. 2 is a diagram explaining the operation of the present invention, FIG. 3 is a block diagram showing an embodiment, FIG. 4 is a table showing a table, and FIG. Reference numeral 1 is a sampling circuit, 2 is a register, 3 is a pattern comparison circuit, 4 is a timing generator, 5 is a clock generator, and 6 is a conversion circuit.

Claims (1)

[Claims] 1. A data receiving device used for data transmission in which start-stop transmission is performed, wherein a start bit having a predetermined bit width having a predetermined logical value in a start-transmitted reception data signal, and the reception data in the reception data. For a stop bit having a predetermined bit width having a predetermined logical value, sampling is performed with a sampling clock faster than the transmission speed,
A means (1) for obtaining these sampling patterns, a start bit reference pattern which is a pattern to be obtained when the start bit is sampled by the sampling clock when the received data is not distorted, and the received data is not distorted In this case, a means (2) for storing a stop bit reference pattern, which is a pattern to be obtained when the stop bit is sampled by the sampling clock, and a sampling pattern obtained by sampling the start bit and the start bit reference pattern are compared. And a pattern comparison circuit (3) for comparing a sampling pattern obtained by sampling the stop bit with the stop bit reference pattern, and the start bit reference pattern Means (4) for instructing the timing for determining the data bit in the received data signal based on both the comparison result for the stop bit reference pattern and the comparison result for the stop bit reference pattern, and a clock with a change timing according to the instruction. A data receiving apparatus comprising: means (5) for forming; and means (6) for determining the data bit of the received data signal by using the clock to obtain the data.