JPH06244831A - Frame synchronization establishment circuit - Google Patents

Abstract

(57) [Abstract] [Object] The present invention relates to a frame synchronization establishment circuit, and particularly, an object thereof is to prevent pseudo synchronization by monitoring an M synchronization pattern. A sync bit detection circuit 1 for detecting a sync bit that matches two sync patterns of an F sync pattern and an M sync pattern from each frame of input data and sequentially reading M sync bits from the sync bit at the same frame interval,
M sync bit counter 2 which counts M sync bits and outputs a reset signal for resetting and shifting the read timing by 1 bit when a predetermined number is exceeded
And a count stop circuit 3 for stopping the counting operation of the M sync bit counter 2 and whether or not there is "0" in a predetermined number of M sync bits. The M synchronization bit monitoring circuit 4 outputs a stop signal, determines whether or not a predetermined number of M synchronization bits read thereafter match a regular M synchronization pattern, and outputs a frame synchronization establishment signal if they match. .

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization establishing circuit mounted on a line terminating device for data communication, and more particularly to a frame for monitoring an M synchronization pattern for preventing pseudo synchronization when establishing a frame synchronization pattern. It relates to a synchronization establishment circuit.

[0002]

2. Description of the Related Art Generally, a synchronization pattern and establishment of synchronization in a frame synchronization establishment circuit of a line termination device will be described. FIG. 3 is an explanatory diagram showing a synchronization pattern and a multi-frame of input data in the long distance mode. In FIG. 3, when performing data communication in the long distance mode,
The F-sync pattern (F0, F1) and the M-sync pattern are included at the beginning of each frame of the input data that is repeated at intervals of 5 ms, and the sync-pattern establishing circuit uses the F-sync pattern (F0, F1) and the M-sync of the frame. Frame synchronization is established by detecting patterns and determining whether they are the same.

FIG. 4 is an explanatory diagram showing a synchronization pattern and a multi-frame of input data in the short distance mode.
In FIG. 4, when performing data communication in the short distance mode,
Each head of a frame of input data that repeats every 0.125 ms includes an F synchronization pattern and an M synchronization pattern, and the synchronization pattern establishment circuit detects the F synchronization pattern and the M synchronization pattern of the frame and determines whether they are the same. It is determined whether or not frame synchronization is established.

FIG. 5 is a block diagram showing the structure of a conventional frame synchronization establishing circuit. As shown in FIG. 5, the frame synchronization establishing circuit of the conventional line termination device uses the F synchronization pattern (F0, F0,
F1) and the M sync pattern are separated and the F sync establishment circuit 51
The F-sync pattern (F0, F1) is detected by to establish the frame sync with, and then the M sync establishing circuit 52 detects the M sync pattern to establish the frame sync. . For example, in the long-distance short-distance mode, the F synchronization pattern (F0, F1) = (1,
Frame synchronization is established when eight patterns of 1), (1,0), (1,1), (1,0) ... Continue, and subsequently,
After detecting M = 0, M = 0 of the eighth frame was detected to establish multiframe synchronization.

[0005]

However, in the frame synchronization establishing circuit of the conventional line termination device, for example, as shown in the explanatory diagram showing an example of the input data including the pseudo synchronization pattern shown in FIG. 0.25 ms
(1,1), (1,0), (1,1), (1,
If the same data as the F synchronization pattern such as 0) ... Is included, this is regarded as a synchronization pattern and synchronization may be established. Therefore, when starting up the terminal,
Or, at the time of switching the system of the exchange, if the pseudo F synchronization is first established, then the pseudo M synchronization is kept waiting, or even if the pseudo M synchronization is established, the line is not connected due to this pseudo synchronization pattern, There was a problem that was destroyed.

The present invention has been made in consideration of the above circumstances. The F-sync pattern and the M-sync pattern of the sync pattern are simultaneously monitored to establish the synchronization only by the regular sync pattern, and the pseudo sync pattern is generated. A frame synchronization establishment circuit capable of preventing establishment.

[0007]

FIG. 1 is a block diagram showing the configuration of the present invention. In FIG. 1, the present invention relates to a frame synchronization establishing circuit that establishes frame synchronization from an F synchronization pattern and an M synchronization pattern included at the beginning of each frame of data communication, in which an F synchronization pattern and an M synchronization pattern are input from each frame of input data. A sync bit detection circuit 1 which detects sync bits matching two sync patterns and sequentially reads M sync bits from the sync bits at the same frame intervals.
Then, the M synchronization bit counter 2 that counts the M synchronization bits and outputs a reset signal that resets when the predetermined number is exceeded and shifts the synchronization bit detection timing by 1 bit, and the counting operations of the M synchronization bit counter 2 are stopped. The count stop circuit 3 and the predetermined number of M sync bits are judged whether or not there is "0", and if there is "0", a stop signal is output to the count stop circuit 3 and a predetermined number of M read thereafter. It is characterized in that it is provided with an M sync bit monitor circuit 4 which judges whether or not the sync bit matches the regular M sync pattern, and outputs a frame sync establishment signal if it matches.

The M sync bit monitoring circuit 4 detects the "0" in the predetermined number of M sync bits from the sync bit detecting circuit 1 or a predetermined number of M sync bits after the "0" is determined. It is preferable that when the bit does not match the regular M sync pattern, it is determined as pseudo sync and a reset signal is output.

When the sync bit detecting circuit 1 receives a reset signal from the M sync bit counter 2 or the M sync bit monitoring circuit 4 while sequentially reading the M sync bits, the F sync pattern and the M sync pattern. It is preferable that the detection of the sync bit that matches the two sync patterns of 1 is sequentially detected at the timing shifted by 1 bit.

The count stop circuit 3 is preferably configured to stop the count operation of the M sync bit counter 2 and stop the output of the reset signal by a stop signal from the M sync bit monitor circuit 4.

When data communication is performed in the long distance mode, the initial sync bits (F0, F1, M) detected from the frame of the input data by the sync bit detection circuit 1 described above.
Is preferably a synchronization pattern of (1, 0, 1), (1, 1, 1), or (1, 1, 0).

In the present invention, in the frame synchronization establishment circuit for establishing frame synchronization from the F synchronization pattern and the M synchronization pattern included at the beginning of each frame of data communication, the synchronization bit detection circuit 1, the M synchronization bit counter 2,
The count stop circuit 3 and the M synchronization bit monitoring circuit 4 are configured as a frame synchronization establishment circuit mounted on the line termination LSI. This line termination LSI is TTL or C
It may be configured by a gate array such as MOS. Further, as the line termination LSI, a microcomputer including a CPU, ROM, RAM and I / O port may be used.

[0013]

According to the present invention, in the frame synchronization establishing circuit that establishes frame synchronization from the F synchronization pattern and the M synchronization pattern included at the beginning of each frame of data communication, the synchronization bit detection circuit 1 performs F from each frame of input data. When a sync bit that matches two sync patterns of the sync pattern and the M sync pattern is detected and the M sync bits are sequentially read from the sync bit at the same frame interval, the M sync bit counter 2 stops the counting operation from the counter stop circuit 3. The number of read M synchronization bits is counted until a stop signal is output, and when a predetermined number is exceeded, a reset signal is output as pseudo synchronization and the timing of reading by the synchronization bit detection circuit 1 is shifted by 1 bit. Further, the M sync bit monitoring circuit 4 judges whether or not there is "0" in a predetermined number of M sync bits after the sync bit is detected by the sync bit detection circuit 1, and if there is "0", the count is stopped. A stop signal is output to the circuit 3 to stop the reset signal output from the M sync bit counter 2, and a comparison is made as to whether or not a predetermined number of M sync bits to be read subsequently match the regular M sync pattern. It determines that frame synchronization has been established and outputs a frame synchronization establishment signal.

The M sync bit monitor circuit 4 detects the "0" in the predetermined number of M sync bits from the sync bit detection circuit 1 or the predetermined number of M sync bits after the "0" is determined. If the bit does not match the regular M sync pattern, it is determined as pseudo sync and a reset signal is output, so pseudo sync is not established.

When the sync bit detecting circuit 1 receives a reset signal from the M sync bit counter 2 or the M sync bit monitoring circuit 4 while sequentially reading the M sync bits, the F sync pattern and the M sync pattern. Since the detection of the sync bit that matches the two sync patterns of 1 is sequentially detected at the timing shifted by 1 bit, the sequential sync bit can be detected when the synchronization is not established.

Since the count stop circuit 3 stops the count operation of the M sync bit counter 2 and the output of the reset signal by the stop signal from the M sync bit monitor circuit 4, the M sync bit monitor circuit 4 is " It is possible to determine whether or not the predetermined number of M synchronization bits after determining "0" match the regular M synchronization pattern.

When data communication is performed in the long distance mode, initial sync bits (F0, F1, M) detected from the frame of the input data by the sync bit detection circuit 1
Is a synchronization pattern of (1, 0, 1), or (1, 1, 1), or (1, 1, 0), the configuration of the synchronization bit detection circuit is simplified.

[0018]

The present invention will be described in detail with reference to the examples shown in the drawings. The present invention is not limited to this.

FIG. 2 is a block diagram showing an embodiment in which the present invention is applied to a frame synchronization establishing circuit of a line termination LSI. In FIG. 2, the same components as those in FIG. 1 have the same numbers. 1 is a synchronization bit detection circuit, 2 is an M synchronization bit counter, 3 is a count stop circuit, 4 is an M synchronization bit monitoring circuit, 5 is an AND gate, and 6 is an OR gate as a frame synchronization establishment circuit mounted on a line termination LSI. Composed.

When performing data communication in the long-distance mode, the sync bit detection circuit 1 first detects an initial sync bit (F0, F0, F0, M0) that matches two sync patterns of an F sync pattern and an M sync pattern from each frame of input data. F1, M) is (1, 0, 1), or (1, 1, 1), or (1,
The sync pattern of (1, 0) is detected. When this sync bit is not detected, a reset signal is output and the sync bits are sequentially detected at the timing shifted by one bit.
When a sync bit is detected, M sync bits are sequentially read from the sync bit at the same frame interval (0.25 ms).

The M sync bit monitor circuit 4 judges whether or not there is a "0" in the eight M sync bits read after the sync bit is detected by the sync bit detection circuit 1, and the "0" is detected. If there is a stop signal (M
= 0), and if there is no "0", the detected sync bits (F0, F1, M) output a reset signal as a pseudo sync bit. The count stop circuit 3 temporarily latches the stop signal (M = 0) and inputs it to the AND gate 2 a connected to the M synchronization bit counter 2. When the input stop signal is M = 0, the M sync bit counter 2 stops the counting operation because the M sync bit is not input by the AND gate 5. Therefore, the reset signal is not output because eight or more are not counted. However, when the stop signal is M = 1, the M sync bits are sequentially counted, so that a reset signal is output every eight counts.

When the stop signal (M = 0) is output to the count stop circuit 3, the M sync bit monitor circuit 4 further outputs eight M sync bits to the regular M sync pattern (1, 1, 1,
(1, 1, 1, 1, 0), and if they match, a frame synchronization establishment signal is output. If they do not match, a reset signal is output as a pseudo sync pattern.
The reset signal output from the sync bit detection circuit 1, the M sync bit counter 2, and the M sync bit monitoring circuit 4 is input to the reset input terminal of each circuit via the OR gate 6 to reset the sync bit to 1 It is sequentially detected at the bit-shifted timing and is repeated until frame synchronization is established.

In the above embodiment, the structure in the long distance mode is shown. However, in the short distance mode, an initial sync bit (F, M) that matches two sync patterns of an F sync pattern and an M sync pattern. Is (1, 1), or (1,
0) the sync pattern is detected, the M sync bit is 16
It is possible to establish frame synchronization by determining that each pattern is "0" (see FIG. 4).

[0024]

According to the present invention, it is possible to prevent the pseudo synchronization from being established when the terminal is started up or the system of the exchange is switched. Therefore, the line is not connected or the data being communicated is not destroyed, which greatly contributes to the improvement of communication quality.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of the present invention.

FIG. 2 is a block diagram showing an embodiment in which the present invention is applied to a frame synchronization establishing circuit of a line termination LSI.

FIG. 3 is an explanatory diagram showing a synchronization pattern and a multi-frame of input data in a long distance mode.

FIG. 4 is an explanatory diagram showing a synchronization pattern and a multi-frame of input data in the short distance mode.

FIG. 5 is a block diagram showing a configuration of a conventional frame synchronization establishing circuit.

FIG. 6 is an explanatory diagram showing an example of input data including a pseudo synchronization pattern.

[Explanation of symbols]

 1 sync bit detection circuit 2 M sync bit counter 3 count stop circuit 4 M sync bit monitor circuit 5 AND gate 6 OR gate

Claims (5)

[Claims] 1. An F included at the beginning of each frame of data communication
In a frame synchronization establishing circuit that establishes frame synchronization from a sync pattern and an M sync pattern, a sync bit that matches two sync patterns of an F sync pattern and an M sync pattern is detected from each frame of input data, and the same frame is detected from the sync bit. A sync bit detection circuit (1) that sequentially reads M sync bits at intervals, and an M sync bit that counts the M sync bits and outputs a reset signal that resets and shifts the sync bit detection timing by 1 bit when a predetermined number is exceeded. A counter (2), a count stop circuit (3) for stopping the counting operation of the M synchronization bit counter (2), and whether or not "0" is present in a predetermined number of M synchronization bits, is determined to be "0". If there is, a stop signal is output to the count stop circuit (3) so that a predetermined number of M sync bits read thereafter are normal. Whether determined to match the M sync pattern, it outputs a frame synchronization establishment signal if they match M
A frame synchronization establishment circuit comprising a synchronization bit monitoring circuit (4). 2. The M sync bit monitoring circuit (4) is provided when there is no "0" in the predetermined number of M sync bits from the sync bit detection circuit (1), or after determining "0". 2. The frame synchronization establishment circuit according to claim 1, wherein when a predetermined number of M synchronization bits of the above are not coincident with a regular M synchronization pattern, it is determined as pseudo synchronization and a reset signal is output. 3. The synchronization bit detection circuit (1) receives a reset signal from the M synchronization bit counter (2) or the M synchronization bit monitoring circuit (4) while sequentially reading M synchronization bits. 2. The frame synchronization establishment circuit according to claim 1, wherein the detection of the sync bit that matches the two sync patterns of the F sync pattern and the M sync pattern is sequentially detected at a timing shifted by 1 bit. 4. The count stop circuit (3) stops the count operation of the M sync bit counter (2) and the output of the reset signal by a stop signal from the M sync bit monitor circuit (4). The frame synchronization establishing circuit according to claim 1, wherein: 5. An initial sync bit (F0, F1, F1) detected from a frame of input data by the sync bit detection circuit (1) when data communication is performed in a long distance mode.
2. The frame synchronization establishing circuit according to claim 1, wherein M) is a synchronization pattern of (1, 0, 1), (1, 1, 1), or (1, 1, 0).