JPH0625089Y2 - Image sensor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to an image sensor for reading an original using a plurality of light receiving elements.

(B) Conventional Technology In a general image sensor, particularly a contact type image sensor, a photodiode array as a plurality of light receiving elements for optically reading an original and a driver IC for driving these are formed. There is. The driving IC is connected to the photodiode in a one-to-one correspondence and is composed of an analog switch that sequentially and serially switches, a shift register, and the like. Usually, considering the yield of IC etc.,
A contact type image sensor having a desired length is configured by using a plurality of ICs of 64 channels or 128 channels.

For example, for applications such as GIII facsimile, A4 size,
An image sensor with 8 dots / mm and 10 msec / line is used, but in the future, an image sensor with higher density and higher speed will be required.

As described above, when the density and speed of the image sensor are increased, the light receiving area of the light receiving element is reduced and the charge storage time is also shortened. Therefore, since the signal component becomes small, it is necessary to reduce the noise component, that is, to reduce the switching noise of each analog switch. Conventionally, the same gate capacitance N-channel MOS has been used as a means for this.
There was an attempt to cancel the switching noise due to the capacitance between the gate and the channel by connecting the FET and the P-channel MOSFET in parallel and applying the voltage in the opposite phase [Details of the Institute of Electronics, Information and Communication Engineers ED83-64]. ]. An equivalent circuit of such an analog switch configuration is shown in FIG.

However, in the analog switch having such a configuration, as is apparent from FIG. 2, the timing of turning on the P-channel MOSFET is delayed from the timing of turning on the N-channel MOSFET by the delay time of the inverter.
Since the channel MOSFET and the P-channel MOSFET are not turned on at the same time, switching noise shown in FIG. 3 (a) occurs with respect to the drive pulse shown in FIG. 3 (a), and sufficient noise reduction cannot be achieved.

In addition, since switching noise of different magnitude appears at ON and OFF, it is not possible to adopt a method of canceling noise by integrating plus switching noise and minus switching noise in an external integrating circuit. It was

(C) Problems to be Solved by the Invention The present invention has been made to solve the above-mentioned problems, and eliminates the cause of switching noise in the complementary analog switch of the IC for driving the image sensor. An image sensor configuration is provided.

(D) Means for Solving the Problems The first image sensor of the present invention is provided with a light receiving element whose electric characteristic changes according to incident light, and a current detecting change in the electric characteristic of the light receiving element. A segment unit consisting of an analog switch connected to the light receiving element,
In a plurality of arranged image sensors, the analog switch is a complementary switch composed of a parallel connection body of an N channel FET and an F channel FET having the same gate capacitance, and the signal line connected to the gates of both FETs is , So that both FETs are turned on or off at the same time,
One FET is connected to one FET and two inverters are connected to the other FET, and the total sum of delay times of the inverters connected to each FET is the same in both FETs. .

Further, the second image sensor of the present invention comprises a complementary analog switch of the first image sensor and a complementary dummy switch which is simultaneously opened and closed by a signal having a phase opposite to the switch, is added in parallel.

(E) Operation According to the first image sensor of the present invention, the P-channel MOSFET and the N-channel MO of the complementary analog switch are used.
The timing when the SFET is turned on or off can be synchronized.

Further, according to the second image sensor of the present invention, since the analog switch and the dummy analog switch operate simultaneously in opposite phases, cancellation of switching noise can be effectively realized.

(F) Embodiment FIG. 1 shows an equivalent circuit of a segment unit of the image sensor of the present invention, that is, one bit of a pixel.

The circuit configuration of the figure is such that a photo sensor P, a sensor bias power supply E, and a load resistor R are connected in series.
An analog switch ASW including a sensor switch SSW and a dummy switch DSW is inserted between the load resistors R.

First, the sensor switch S which is the first feature of the present invention.
The SW will be described in detail below.

The sensor switch SSW shown in FIG. 2 has a P-channel MOSFET inverter INV newly added to the gate of the N-channel MOSFET of the conventional complementary analog switch shown in FIG.
Two inverters INV2, 3 having a delay time of 1 and a delay time of 1/2 are connected in series. That is, the inverter IN
The delay time of V1 and the total delay time of the two-stage inverters INV2, 3 become equal.

Therefore, the P-channel MOSFET is connected via the one inverter INV1 having the same delay time as the drive pulse for turning ON / OFF the analog switch ASW.
Of the N-channel MO through the other two-stage inverters INV2 and
Since it is applied to the SFET, both FETs turn ON and OFF at the same time.

As a result, as shown in FIG. 3 (c), the magnitude of the switching noise can be reduced to about half that of the conventional one shown in FIG. 3 (b).

Next, the Tammy switch D which is the second feature of the present invention.
The SW will be described in detail below.

The dummy switch DSW in the figure is a sensor switch SSW.
The sensor switch SSW has a complementary analog switch configuration symmetrical to that of the sensor switch SSW, but its input terminal is open.

Here, the symmetry means that the sensor switch S of FIG.
This means the relationship between SW and the dummy switch DSW. Specifically, in order to operate these switches in completely opposite phases, the sensor switch SSW, which is a complementary switch, has one inverter in the P-channel MOSFET and one N-channel MOSFET. 2 of them are connected to each other, and the sum of the delay times of the inverters in each FET is the same,
In the dummy switch DSW which is a complementary switch, two inverters are connected to the P-channel MOSFET and one inverter is connected to the N-channel MOSFET, and the sum of the delay times of the inverters in each FET is the same. A relationship that has been made.

Therefore, the dummy switch DSW generates only the switching noise of FIG. 3 (d) having the opposite polarity and the same size at the same timing as the switching noise of the sensor switch SSW of FIG. 3 (c). Noise cancellation can be performed on the switch SSW.

By adding such a dummy switch DSW, the switching noise can be reduced to about 1/5 of that of FIG. 3 (c) as shown in FIG. 3 (e).

According to the embodiment circuit of the present invention having the above-mentioned configuration,
Since the switching noise can be reduced to 1/10 of that of the conventional circuit, it is possible to guarantee 10 times higher speed operation.

Although two inverters are provided in the N-channel MOSFET and one inverter is provided in the P-channel MOSFET in the above-described embodiment, more inverters are combined and added to more strictly match the operation timings of both FETs. May be.

In the embodiment described above, the dummy switch DSW is added to each sensor switch SSW in a one-to-one manner. However, as shown in FIG.
Switching noise can also be effectively canceled by providing one dummy switch DSWn for each IC unit of channels or 128 channels.
In this case, the increase in the chip area of the IC is greatly suppressed, and the chip cost is hardly increased. Therefore, the cost of the contact image sensor does not increase.

(G) Effect of the Invention As is apparent from the above description, according to the image sensor of the present invention, the P-channel MO of the complementary analog switch is used.
The ON / OFF timings of the SFET and the N-channel MOSFET can be closely matched, which can significantly reduce the switching noise.

Further, according to the present invention, switching noise can be eliminated by the noise canceling action of the dummy switch.

[Brief description of drawings]

1 is an equivalent circuit diagram of a segment unit of the image sensor of the present invention, FIG. 2 is an equivalent circuit diagram of a segment unit of a conventional image sensor, FIGS. 3 (a) to 3 (e) are noise waveform diagrams, and FIG. The figure is an equivalent circuit diagram of another embodiment of the present invention. P ... Photo sensor, E ... Bias power supply, R ... Load resistance, ASW ... Analog switch, INV ... Inverter, SSW ... Sensor switch, DSW ... Dummy switch.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Hiroshi Iwata 2-18 Keihan Hondori, Moriguchi City, Osaka Prefecture Sanyo Electric Co., Ltd. (72) Keiichi Sano 2-18 Keihan Hondori, Moriguchi City, Osaka Prefecture Sanyo Electric Co., Ltd. (56) Reference JP 61-270971 (JP, A) JP 60-35869 (JP, A)

Claims (2)

[Scope of utility model registration request] 1. A segment unit comprising a light-receiving element whose electric characteristic changes in response to incident light, and an analog switch connected to the light-receiving element for detecting a current change in the electric characteristic of the light-receiving element. However, in a plurality of image sensors arranged, the analog switch is a complementary switch composed of a parallel connection body of an N-channel FET and a P-channel FET having the same gate capacitance.
One of the FETs is connected to the signal line connected to the gate of so that both FETs are turned on or off at the same time.
An image sensor characterized in that two inverters are connected to the other FET, respectively, and the sum of delay times of the inverters connected to each FET is the same in both FETs. 2. A segment unit consisting of a light receiving element whose electrical characteristics change in response to incident light, and an analog switch connected to the light receiving element for current detection of changes in the electrical characteristics of the light receiving element. Is an image sensor in which a plurality of the FETs are arranged, and the analog switch is a complementary switch composed of a parallel connection body of an N-channel FET and a P-channel FET having the same gate capacitance.
One of the FETs is connected to the signal line connected to the gate of so that both FETs are turned on or off at the same time.
Two inverters are connected to the other FET, and the total sum of the delay times of the inverters connected to each FET is the same in both FETs, and the analog switches are simultaneously opened and closed by signals of opposite phase. A dummy switch composed of a complementary switch that operates is added in parallel, and a signal line connected to the gates of both FETs of the dummy switch has two FETs of the same conductivity type as the one FET.
One inverter is connected to each FET of the same conductivity type as the other FET, and the sum of delay times of the inverters connected to each FET is the same in both FETs. Image sensor.