JPH06252077A - Method of diffusing impurity - Google Patents

Method of diffusing impurity

Info

Publication number
JPH06252077A
JPH06252077A JP3508193A JP3508193A JPH06252077A JP H06252077 A JPH06252077 A JP H06252077A JP 3508193 A JP3508193 A JP 3508193A JP 3508193 A JP3508193 A JP 3508193A JP H06252077 A JPH06252077 A JP H06252077A
Authority
JP
Japan
Prior art keywords
impurities
substrate
voltage
indium
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3508193A
Other languages
Japanese (ja)
Inventor
Akio Tanigawa
明男 谷川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3508193A priority Critical patent/JPH06252077A/en
Publication of JPH06252077A publication Critical patent/JPH06252077A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To control a special distribution of impurities within a semiconductor or an insulator into which the impurities have beforehand been introduced at a comparatively low temperature by a method wherein X-rays are emitted to the semiconductor or insulator and also an electric field is applied thereto. CONSTITUTION:Indium 2 is introduced into a silicon substrate 1 by an ion implantation. Successively, an insulation film 3 and an element 4 are provided so that an electric field can be applied to the surface of the silicon substrate 1. In such a condition that the substrate 1 is used as an earth and a voltage of 0 or -2 or +2V is applied to an electrode 4, powerfull X-rays 5 are emitted for two hours. After emitting, the insulation film 3 and the electrode 4 are removed and a distribution of indium in the depth direction is measured by secondary ion mass analysis. As compared with the case where a voltage is not applied after the ion implantation, in the case where a voltage of -2V is applied, indium is transferred to the surface side of the substrate, and in the case where a voltage of +2V is applied, indium is transferred to the depth side of the substrate.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、不純物の拡散方法、特
に不純物の空間的分布を低温で制御することのできる不
純物の拡散方法を提供することにある。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention provides a method for diffusing impurities, and more particularly, a method for diffusing impurities which can control the spatial distribution of impurities at low temperatures.

【0002】[0002]

【従来の技術】従来、半導体や絶縁体に局所的に不純物
を導入し拡散させる方法は、イオン注入とこれに引き続
いて行われる高温熱処理が典型的な方法として行われて
いる。
2. Description of the Related Art Conventionally, as a method of locally introducing and diffusing impurities into a semiconductor or an insulator, ion implantation and subsequent high temperature heat treatment are typically performed.

【0003】[0003]

【発明が解決しようとする課題】上記のようなイオン注
入および高温熱処理による不純物の拡散方法は、不純物
の導入時の空間的分布を拡大させる方向の作用しか持っ
ていない。すなわち、半導体や絶縁体中の局所的な不純
物の空間的分布を制御することはできなかった。
The above-mentioned method of diffusing impurities by ion implantation and high-temperature heat treatment has only the effect of expanding the spatial distribution when introducing the impurities. That is, it was not possible to control the local spatial distribution of impurities in the semiconductor or insulator.

【0004】また従来の不純物の拡散方法は、高温処理
を伴うので、高温熱処理のための設備を必要とする。
Further, the conventional method of diffusing impurities involves high temperature treatment, and therefore requires equipment for high temperature heat treatment.

【0005】本発明の目的は、半導体もしくは絶縁体中
の不純物の空間的分布を比較的低温で制御することがで
きる不純物の拡散方法を提供することにある。
An object of the present invention is to provide an impurity diffusion method capable of controlling the spatial distribution of impurities in a semiconductor or an insulator at a relatively low temperature.

【0006】[0006]

【課題を解決するための手段】本発明の不純物の拡散方
法は、予め不純物を導入した半導体もしくは絶縁体に、
X線を照射し、且つ電界をかけることによって不純物の
空間的分布を制御することを特徴とする。
A method for diffusing impurities according to the present invention is a method for diffusing impurities in a semiconductor or an insulator into which impurities have been introduced in advance.
It is characterized in that the spatial distribution of impurities is controlled by irradiating X-rays and applying an electric field.

【0007】[0007]

【作用】不純物を導入された絶縁体や半導体にX線を照
射すると、元素毎の吸収係数に応じた率で固体内に正電
荷を持つイオンが発生する。このイオンの動く方向を電
界によって制御することで不純物の空間的分布を制御す
ることができる。
When an insulator or semiconductor having impurities introduced therein is irradiated with X-rays, ions having a positive charge are generated in the solid at a rate according to the absorption coefficient of each element. The spatial distribution of impurities can be controlled by controlling the moving direction of the ions by the electric field.

【0008】[0008]

【実施例】本発明の実施例を図を用いて説明する。Embodiments of the present invention will be described with reference to the drawings.

【0009】図1は、本発明の一実施例を説明する断面
模式図である。
FIG. 1 is a schematic sectional view for explaining an embodiment of the present invention.

【0010】まず、シリコン基板1に、イオン注入(加
速エネルギ100keV,注入量2×1014atoms
/cm2 )によってインジウム2を導入する。続いて、
シリコン基板1の表面に電界を印加するための絶縁膜3
と電極4を設ける。基板1をアースとして電極4に0ま
たは−2または+2Vの電圧を印加した状態で、強力な
X線5(5×1018photons・cm-2・s-1)を
2時間照射した。
First, ion implantation (acceleration energy 100 keV, implantation amount 2 × 10 14 atoms) is performed on the silicon substrate 1.
/ Cm 2 ) is used to introduce indium 2. continue,
Insulating film 3 for applying an electric field to the surface of the silicon substrate 1.
And electrode 4 are provided. The substrate 1 was grounded, and a strong X-ray 5 (5 × 10 18 photons · cm −2 · s −1 ) was irradiated for 2 hours while a voltage of 0, −2, or +2 V was applied to the electrode 4.

【0011】照射後、絶縁膜3と電極4を除去し、イン
ジウムの深さ方向分布を二次イオン質量分析によって測
定すると、図2のようになった。縦軸はインジウムの濃
度(atoms/cc)を、横軸は基板表面からの深さ
(nm)である。曲線6は電極4に電圧を印加しない。
すなわちイオン注入のままの場合の分布を、曲線7は電
極4に−2Vの電圧を印加した場合の分布を、曲線8は
電極4に+2Vの電圧を印加した場合の分布を、それぞ
れ示している。
After the irradiation, the insulating film 3 and the electrode 4 were removed, and the distribution of indium in the depth direction was measured by secondary ion mass spectrometry. The vertical axis represents the concentration of indium (atoms / cc), and the horizontal axis represents the depth (nm) from the substrate surface. Curve 6 applies no voltage to electrode 4.
That is, curve 7 shows the distribution when ion implantation is performed, curve 7 shows the distribution when a voltage of −2 V is applied to the electrode 4, and curve 8 shows the distribution when a voltage of +2 V is applied to the electrode 4. .

【0012】図2から、イオン注入のままの場合に比し
て、−2Vの電圧を印加した場合は表面側に、+2Vの
電圧を印加した場合は基板奥側にインジウムが移動して
いたことがわかる。
From FIG. 2, it was found that indium was moved to the surface side when a voltage of −2 V was applied and to the back side of the substrate when a voltage of +2 V was applied, as compared with the case of ion implantation as it is. I understand.

【0013】上記のような効果は、あらゆる半導体と絶
縁体中のあらゆる不純物に対して程度の差はあるものの
同様に見られる。
The above-mentioned effects are similarly observed to some extent with respect to all semiconductors and all impurities in the insulator.

【0014】[0014]

【発明の効果】本発明によれば、半導体もしくは絶縁体
中の不純物の空間的分布を比較的低温で制御することが
できる。
According to the present invention, the spatial distribution of impurities in a semiconductor or an insulator can be controlled at a relatively low temperature.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を説明する断面模式図であ
る。
FIG. 1 is a schematic sectional view illustrating an embodiment of the present invention.

【図2】本発明の一実施例の結果を示す、二次イオン質
量分析によるインジウムの深さ方向分布図である。
FIG. 2 is a distribution diagram of indium in the depth direction by secondary ion mass spectrometry showing the results of one example of the present invention.

【符号の説明】[Explanation of symbols]

1 シリコン基板 2 インジウム導入層 3 絶縁膜 4 電極 5 X線 6 イオン注入のままでの分布曲線 7 電極に−2Vの電圧を印加した場合の分布曲線 8 電極に+2Vの電圧を印加した場合の分布曲線 1 Silicon Substrate 2 Indium Introduced Layer 3 Insulating Film 4 Electrode 5 X-ray 6 Ion Implanted Distribution Curve 7 Distribution Curve when a Voltage of -2V is Applied to the Electrode 8 Distribution when a Voltage of + 2V is Applied to the Electrode curve

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】予め不純物を導入した半導体もしくは絶縁
体に、X線を照射し、且つ電界をかけることによって不
純物の空間的分布を制御することを特徴とする不純物の
拡散方法。
1. A method of diffusing impurities, which comprises irradiating a semiconductor or an insulator into which impurities have been introduced in advance with X-rays and applying an electric field to control the spatial distribution of the impurities.
【請求項2】半導体もしくは絶縁体より成る基板に不純
物を導入する工程と、 前記基板に絶縁膜を介して電極を形成する工程と、 前記基板にX線を照射し、且つ、前記電極に電圧を印加
し、前記不純物の空間的分布を制御することを特徴とす
る不純物の拡散方法。
2. A step of introducing impurities into a substrate made of a semiconductor or an insulator, a step of forming an electrode on the substrate through an insulating film, irradiating the substrate with X-rays, and applying a voltage to the electrode. Is applied to control the spatial distribution of the impurities, and a method of diffusing the impurities.
【請求項3】半導体もしくは絶縁体より成る基板に不純
物を導入する工程と、 前記基板の表面に絶縁膜を介して電極を形成する工程
と、 前記基板の表面側からX線を照射し、且つ、前記基板を
アースに接続し、前記電極に電圧を印加し、前記不純物
の空間的分布を制御することを特徴とする不純物の拡散
方法。
3. A step of introducing impurities into a substrate made of a semiconductor or an insulator, a step of forming an electrode on the surface of the substrate via an insulating film, and irradiating X-rays from the surface side of the substrate, A method of diffusing impurities, characterized in that the substrate is connected to ground and a voltage is applied to the electrodes to control the spatial distribution of the impurities.
JP3508193A 1993-02-24 1993-02-24 Method of diffusing impurity Pending JPH06252077A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3508193A JPH06252077A (en) 1993-02-24 1993-02-24 Method of diffusing impurity

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3508193A JPH06252077A (en) 1993-02-24 1993-02-24 Method of diffusing impurity

Publications (1)

Publication Number Publication Date
JPH06252077A true JPH06252077A (en) 1994-09-09

Family

ID=12432037

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3508193A Pending JPH06252077A (en) 1993-02-24 1993-02-24 Method of diffusing impurity

Country Status (1)

Country Link
JP (1) JPH06252077A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0479215A (en) * 1990-07-20 1992-03-12 Fujitsu Ltd Manufacture of semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0479215A (en) * 1990-07-20 1992-03-12 Fujitsu Ltd Manufacture of semiconductor device

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