JP2000077350A - Power semiconductor device and method of manufacturing the same - Google Patents

Abstract

(57) Abstract: An N-type region is formed at a deeper position in a semiconductor substrate. SOLUTION: This GTO is formed on an N-type layer 1 formed in a silicon substrate, a P-type base layer 2 formed on a surface 1S1 of the N-type layer 1, and a surface 2S2 of the P-type base layer 2. The N-type emitter layer 3 formed, the P-type emitter layer 4 formed at a predetermined position on the surface 1S2 of the N-type layer 1, and the surface 4S2 and the side surface 4W of the P-type emitter layer 4 are formed. An N-type layer 5. The N-type layer 5 is irradiated on the entire surface of the main surface 1S3 of the silicon substrate with protons at an acceleration energy of, for example, 4.5 MeV and a dose of 5 × 10 ¹² cm ^−2. 350 °
It is formed by performing a heat treatment at a temperature of C. By the heat treatment, crystal defects caused by the irradiation of the protons are recovered, and the protons which are irradiated and exist in the crystal are turned into donors.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power semiconductor device, and more particularly, to a power semiconductor device.
The present invention relates to a method for forming a mold region.

[0002]

2. Description of the Related Art FIGS. 4 and 5 are schematic longitudinal sectional views of a power semiconductor device in a step of forming an active region in a semiconductor substrate in a conventional method for manufacturing a power semiconductor device. In the following description, the “activation region” refers to a region having carriers of a predetermined conductivity type, such as a diffusion layer forming an emitter region in a power semiconductor device.

An insulating film 12 formed on a surface 11S of a silicon substrate 11 having a relatively low concentration of N-type impurities
A resist film 13 formed on the insulating film 12 and then patterned by a photolithography process.
Is used as a mask to form window or opening 12W by, for example, anisotropic etching (see FIG. 4).

After removing the resist film 13, N-type impurities are ion-implanted into the surface 11S of the silicon substrate 11 using the insulating film 12 as a mask. Thereafter, the silicon substrate 11 is subjected to a heat treatment at a temperature of, for example, 800 ° C. to diffuse the ion-implanted N-type impurities, thereby forming a region having a predetermined depth from the surface 11S of the N-type silicon substrate 11. Then, an N-type activation region 14 is formed (see FIG. 5).

[0005]

FIG. 6 shows the carrier concentration distribution in the depth direction from the surface 11S in the power semiconductor device of FIG. As shown in FIG. 6, in the activation region 14 formed by the conventional manufacturing method (ion implantation method), the carrier concentration in the vicinity of the surface 11S of the silicon substrate 11 is highest, and the depth from the surface 11S is deep. As the carrier concentration decreases, the carrier concentration decreases. As described above, in the conventional method of manufacturing a semiconductor device, it is difficult to (i) form the activation region at a deeper position from the surface of the semiconductor substrate or to a deeper position.

Further, in the conventional manufacturing method, in order to diffuse and activate the impurity after ion implantation of the impurity, (ii) heat treatment (annealing) at a high temperature of about 800 ° C. is required. It is.

In order to solve the above-mentioned problem (i), in order to diffuse the ion-implanted impurity to a predetermined deeper position, a temperature higher than the above-mentioned temperature of about 800 ° C. Therefore, it is necessary to perform heat treatment for a longer time. However, (iii) such a long-time heat treatment at a high temperature induces crystal defects in the silicon substrate 11, so that the completed power semiconductor device suffers from defects in characteristics such as leak current due to the crystal defects. Another problem that it becomes easier is raised.

[0008] In addition, in the case of performing the above-described long-time heat treatment at a high temperature, (iv) manufacturing equipment for realizing such a high-temperature condition is required, and furthermore, such a process is required. Is a problem in the manufacturing process that the time spent in the process becomes longer.

The present invention has the above problems (i) to (iv).
It is made in view of, compared to the conventional ion implantation method, at a deeper position from the surface of the semiconductor substrate, or
A first object is to provide a power semiconductor device including a region where the carrier concentration is controlled to a deeper position.

It is a second object of the present invention to provide a method of manufacturing a power semiconductor device which can achieve the first object.

[0011]

According to a first aspect of the present invention, there is provided a power semiconductor device including a semiconductor substrate having an N-type region formed therein. The mold region is formed by performing a heat treatment at a predetermined temperature lower than the annealing temperature in the ion implantation method after the irradiation of the predetermined charged particles.

(2) A power semiconductor device according to a second aspect of the present invention is the power semiconductor device according to the first aspect, wherein the predetermined charged particles are light element ions. And

(3) A power semiconductor device according to a third aspect of the present invention is the power semiconductor device according to the second aspect, wherein the ions of the light element are in a predetermined position on a main surface of the semiconductor substrate. It is characterized in that only an area is selectively irradiated.

(4) In the method for manufacturing a power semiconductor device according to the present invention, after irradiating a semiconductor substrate with predetermined charged particles, the semiconductor substrate is heated at a predetermined temperature lower than an annealing temperature in an ion implantation method. An N-type region is formed inside the semiconductor substrate by performing a heat treatment.

(5) The method for manufacturing a power semiconductor device according to the invention described in claim 5 is the method for manufacturing a power semiconductor device according to claim 4, wherein the predetermined charged particles are light elements. It is an ion.

(6) The method for manufacturing a power semiconductor device according to the invention of claim 6 is the power semiconductor device according to claim 5, wherein the ions of the light element are formed on the main surface of the semiconductor substrate. Is selectively illuminated only to a predetermined area.

[0017]

(Embodiment 1) FIG. 1 is a schematic longitudinal sectional view of a gate turn-off thyristor (hereinafter abbreviated as "GTO") as a power semiconductor device according to Embodiment 1 of the present invention. is there.

As shown in FIG. 1, the present GTO includes an N-type semiconductor layer 1 having a relatively low impurity concentration (hereinafter, also referred to as "N-type layer 1"). Then, a P-type base layer 2 (hereinafter also referred to as “PB layer 2”) is formed on the surface 1S1 of the N-type layer 1, and the surface 1S1 and the PB layer 2 are formed.
And one surface 2S1 forms an interface. Furthermore, PB
An N-type emitter layer 3 (hereinafter also referred to as "NE layer 3") is formed at a predetermined position on the surface 2S2 of the layer 2 opposite to the surface 2S1, and the surface 2S2 and the NE layer 3 The surface 3S2 forms an interface.

On the other hand, a plurality of P-type emitter layers 4 (hereinafter, also referred to as "PE layers 4") are provided at predetermined positions on a surface 1S2 of the N-type layer 1 opposite to the surface 1S1 at a predetermined distance. The surface 1S2 and P
The surface 4S2 of the E layer 4 forms an interface. Further, an N-type semiconductor layer (N-type region) 5 manufactured by a manufacturing method described later is formed so as to be in contact with the surface 1S2 and the side surface 4W of the PE layer 4 perpendicular to the surface 4S2.
The N-type semiconductor layer 5 has a higher concentration than the impurity concentration of the N-type layer 1. Hereinafter, the N-type semiconductor layer 5 is also referred to as “N-type layer 5”.

Next, a method of forming the above-described layers of the present GTO will be described.

First, a silicon substrate (semiconductor substrate) having a relatively low impurity concentration is prepared. Since a part of the silicon substrate later forms the N-type layer 1, the silicon substrate is also referred to as "silicon substrate 1" in the following description.

The PB layer 2 is formed, for example, by boron (B) with respect to a main surface of the silicon substrate 1 (hereinafter, also referred to as “main surface 3S1”) corresponding to a surface 3S1 of the NE layer 3 opposite to the surface 3S2. Implanted, followed by heat treatment (annealing)
To diffuse boron from the main surface 3S1 to a region of a predetermined depth.

After the formation of the PB layer 2, the main surface 3S
For example, phosphorus (P) is thermally diffused from the first surface 3S1.
An N-type diffusion layer is formed in a region having a predetermined depth from PB and shallower than the PB layer 2. Thereafter, the NE layer 3 shown in FIG. 1 is formed by removing a part of the diffusion layer by etching.

On the other hand, the method for forming the N-type layer 5 is as follows.

First, the entire surface of the main surface 1S3 of the silicon substrate 1 opposite to the main surface 3S1 is, for example, 4.5M.
With an acceleration energy of eV and a dose of 5 × 10 ¹² cm ⁻² , for example, protons (charged particles) as hydrogen ions
Is irradiated. Thereafter, the silicon substrate 1 is, for example, 350 °
When a heat treatment at a temperature of C is performed, the crystal defects caused by the irradiation of the protons are recovered, and the protons introduced (present) into the crystal by the irradiation become donors. By such a forming method, an N-type semiconductor layer which will later become the N-type layer 5 is formed.

At this time, the temperature of the heat treatment is about 200
A temperature range of about 700 ° C. to about 700 ° C. is selected. In particular, in such a temperature range, about 200 ° C. or more, which is a temperature necessary for converting protons into donors, and the temperature of the N-type layer 5 A temperature range of about 500 ° C. or less, which is a temperature at which impurities in the diffusion layer formed before the formation is not unnecessarily diffused, is desirable.

The main surface 1S3 of the silicon substrate 1
By selectively ion-implanting, for example, boron into the predetermined region, and then performing heat treatment (annealing), the PE layer 4 is formed in a region at a predetermined depth from the main surface 1S3. By the formation of the PE layer 4, the N-type layer 5 of the above-described embodiment is formed.

Here, a method of manufacturing the N-type layer 5, which is a characteristic part of the first embodiment, will be described with reference to FIG. 2, which is a carrier concentration distribution of an evaluation sample. Such an evaluation sample has a P-type layer in a region at a predetermined depth from one surface, and has an acceleration energy of 4.5 MeV and a dose of 5 × 10 ¹² cm ^{−2 over} the entire surface of the one surface. After irradiating the protons in an amount, heat treatment was performed at a temperature of 350 ° C. The carrier concentration in the depth direction of this evaluation sample was measured by the SR (Sprending Resistance) method.

As shown in FIG. 2, according to the present manufacturing method,
It can be seen that the carrier concentration is high in a region of about 190 μm to 230 μm from the one surface.
As in the case of the above-described N-type layer 5, this region is a portion in which the carrier concentration is controlled by turning the irradiated protons introduced into the sample into donors. As described above, according to the present manufacturing method, the N-type region can be formed in a region deeper from the surface of the semiconductor substrate.

In particular, in the present production method, a light element hydrogen ion, that is, a proton, is used, so that a heavy (large mass) element such as phosphorus or arsenic (As) is used as N-type impurity ions or charged particles. The acceleration energy (acceleration voltage) of the charged particles to be irradiated can be increased as compared with the conventional ion implantation method. For this reason, according to this manufacturing method, protons can be introduced from the surface of the semiconductor substrate to a deeper region as compared with the ion implantation method, and as a result, an N-type region is formed up to such a deep region. It becomes possible to do. Of course, the aforementioned acceleration energy is 4.5.
When it is made larger than MeV, an N-type region can be formed in a deeper region, and by controlling the acceleration energy, the main surface 1 can be formed as shown in the N-type layer 5 in FIG.
An N-type layer can be formed in a wide range from S3 to a region having a predetermined depth.

Therefore, in the conventional ion implantation method, about 80 nm is required to diffuse the implanted impurity to a predetermined depth.
In contrast to the need for heat treatment at a high temperature of 0 ° C. or higher, according to the present manufacturing method, there is no need for a heat treatment step at such a high temperature. In addition, since the heat treatment for turning the charged particles present in the semiconductor by irradiation into a donor is performed at a relatively low temperature of about 350 ° C., the generation of crystal defects induced by the heat treatment at a high temperature is reduced. It can be greatly suppressed.

In addition, as described above, the present manufacturing method does not require a long-time heat treatment step at a high temperature in the conventional manufacturing method, so that there is an advantage that the time of the manufacturing step can be reduced as compared with the conventional manufacturing method. .

Further, in the present manufacturing method, even when another layer (a P-type layer in the case of the above sample) is formed in advance as in the above-described sample for evaluation, it is more effective than the other layer. There is an advantage that an N-type region can be formed in a deeper region. In view of this point, the GTO of FIG.
With regard to the manufacturing method described above, after the PB layer 2 or the NE layer 3 is formed, the main surface 3S1 may be irradiated with protons to form the N-type layer 5.

Further, the N-type layer 5 of FIG. 1 is formed in the N-type layer formed in a region from the main surface 1S3 to a predetermined depth by a conventional ion implantation method, and in the present embodiment, in a region deeper than such a region. It is also possible to manufacture with an N-type layer selectively formed by using the manufacturing method according to the first embodiment.

In particular, when proton irradiation is selectively performed through a mask (for example, a metal mask) formed in a predetermined pattern, as shown in FIG. 3, such selective irradiation in the main surface 1S3 is performed. An N-type layer 5A (corresponding to the N-type layer 5 in FIG. 1) can be formed in a predetermined region from the region toward the inside of the silicon substrate 1. Further, the N-type layer 5B shown in FIG.
May be separately manufactured by such a selective formation method, or may be manufactured in advance by a conventional ion implantation method before forming the N-type layer 5A.
Note that among the components in FIG. 3, the same components as those in FIG. 1 are denoted by the same reference numerals, and descriptions thereof will be used.

As the charged particles, ions such as deuteron, 3 helium, alpha and the like may be used instead of protons. These light element ions are required to have characteristics and the like required for a power semiconductor device to be manufactured. Can be selected according to In addition, the method of manufacturing the N-type region according to the first embodiment can be applied to a semiconductor material other than silicon (of course, to a P-type semiconductor substrate). It is needless to say that the present invention can be applied to a semiconductor device for use.

Here, as a method of controlling the carrier concentration in a deep region in a semiconductor by irradiating charged particles such as protons, there is a prior art proposed in Japanese Patent Application Laid-Open No. 6-349768. However, the prior art only irradiates a given semiconductor with charged particles,
Embodiment 1 in that no heat treatment is performed thereafter.
Is different from the manufacturing method according to the above. The difference is that the prior art controls the concentration of carriers caused by crystal defects generated by the irradiation of charged particles, whereas the manufacturing method according to the first embodiment does not allow the irradiation to be performed in a semiconductor. This is a technique for forming an N-type region by forming charged particles (light elements) existing in the substrate into donors by heat treatment (at the same time, by recovering crystal defects by irradiation).

[0038]

(1) According to the first aspect of the present invention, since the heat treatment is performed at a predetermined temperature lower than the annealing temperature in the ion implantation method, the annealing is performed at a high temperature in the ion implantation method. The generation of induced crystal defects can be greatly suppressed. Therefore, it is possible to obtain an effect that defects of characteristics such as leak current caused by the crystal defects can be remarkably reduced.

(2) According to the second aspect of the present invention, since the charged particles are light element ions, a heavy (large mass) element such as phosphorus or arsenic is used as N-type impurity ions or charged particles. The acceleration energy (acceleration voltage) of the charged particle species to be irradiated can be increased as compared with the ion implantation method. For this reason, the light element ions can be introduced into a region deeper than in the case of the ion implantation method. Moreover, since the acceleration energy can be controlled within a wider energy range, only such control can be performed from the surface irradiated with the charged particles to a region of a predetermined depth or a predetermined depth not in contact with the surface. N in the area
A mold region can be formed.

Further, when the diffusion layer is formed to a deeper position in the ion implantation method, it is necessary to spend a long time for the high-temperature annealing treatment. Since there is no need for a long heat treatment step, there is an advantage that the time of the manufacturing step can be reduced.

(3) According to the third aspect of the present invention, the light element ions are selectively irradiated only to a predetermined region of the main surface of the semiconductor substrate. The N-type region can be selectively formed in the semiconductor substrate.

(4) According to the invention of claim 4, it is possible to manufacture a power semiconductor device capable of exhibiting the effect (1).

(5) According to the invention of claim 5, it is possible to manufacture a power semiconductor device capable of exhibiting the effect (2).

(6) According to the invention of claim 6, it is possible to manufacture a power semiconductor device capable of exhibiting the effect (3).

[Brief description of the drawings]

FIG. 1 is a schematic longitudinal sectional view of a power semiconductor device according to a first embodiment.

FIG. 2 is a carrier concentration distribution diagram showing an N-type region manufactured by the method for manufacturing a power semiconductor device according to the first embodiment.

FIG. 3 is a schematic longitudinal sectional view of the power semiconductor device according to the first embodiment;

FIG. 4 is a schematic longitudinal sectional view of a power semiconductor device in a manufacturing process in a conventional manufacturing method.

FIG. 5 is a schematic longitudinal sectional view of a power semiconductor device in a manufacturing process in a conventional manufacturing method.

FIG. 6 is a carrier concentration distribution diagram from a surface to a depth direction in a power semiconductor device manufactured by a conventional manufacturing method.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 1S3, 3S1 main surface, 2P type base layer, 3N type emitter layer, 4P type emitter layer, 5,
5A N-type layer (N-type region).

Claims (6)

[Claims] 1. A power semiconductor device including a semiconductor substrate having an N-type region formed therein, wherein the N-type region is irradiated with predetermined charged particles and then exposed to an annealing temperature in an ion implantation method. Characterized by being subjected to a heat treatment at a low predetermined temperature,
Power semiconductor device. 2. The power semiconductor device according to claim 1, wherein the predetermined charged particles are ions of a light element. 3. The power semiconductor device according to claim 2, wherein the ions of the light element are selectively irradiated only to a predetermined region on a main surface of the semiconductor substrate. Power semiconductor device. 4. An N-type region is formed inside the semiconductor substrate by irradiating the semiconductor substrate with predetermined charged particles and then performing a heat treatment at a predetermined temperature lower than an annealing temperature in the ion implantation method. A method for manufacturing a power semiconductor device, comprising: 5. The method for manufacturing a power semiconductor device according to claim 4, wherein the predetermined charged particles are light element ions. 6. The power semiconductor device according to claim 5, wherein the ions of the light element are selectively applied only to a predetermined region of a main surface of the semiconductor substrate. To manufacture a power semiconductor device.