JPH06252329A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH06252329A
JPH06252329A JP5040099A JP4009993A JPH06252329A JP H06252329 A JPH06252329 A JP H06252329A JP 5040099 A JP5040099 A JP 5040099A JP 4009993 A JP4009993 A JP 4009993A JP H06252329 A JPH06252329 A JP H06252329A
Authority
JP
Japan
Prior art keywords
semiconductor chip
conductive film
inner lead
insulating tape
bonding wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5040099A
Other languages
Japanese (ja)
Inventor
Masahiko Hori
将彦 堀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP5040099A priority Critical patent/JPH06252329A/en
Publication of JPH06252329A publication Critical patent/JPH06252329A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/547—Dispositions of multiple bond wires
    • H10W72/5473—Dispositions of multiple bond wires multiple bond wires connected to a common bond pad
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/853—On the same surface
    • H10W72/865—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/944—Dispositions of multiple bond pads
    • H10W72/9445—Top-view layouts, e.g. mirror arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】 【目的】インナリードと半導体チップの電極パッドとの
間を通る絶縁性テープ上の配線層を薄い導電膜にするこ
とによってインナリードと半導体チップとを接続するボ
ンディングワイヤのループ高さを低く制御し変形に強く
する。 【構成】ＬＯＣ構造であり、各インナリード13の端部は
半導体チップ11主表面上に絶縁テープ24により固着され
ている。絶縁テープ24において各インナリード13が固着
されない電極パッド12寄りの領域に導電性膜25が露出し
ている。電源ピンでない各インナリード13と半導体チッ
プ11の電極パッド12とは例えばボンディングワイヤ26に
より導電性膜25に接触せずに接続されている。半導体チ
ップ11の電極パッド12中、電源パッドに相当するパッド
と上記導電性膜25がボンディングワイヤ27により接続さ
れている。さらに、導電性膜25は各インナリード13中の
電源ピンに相当するリードにボンディングワイヤ28によ
り接続されている。 (57) [Abstract] [Purpose] A loop of a bonding wire that connects an inner lead and a semiconductor chip by forming a thin conductive film on a wiring layer on an insulating tape that passes between the inner lead and an electrode pad of the semiconductor chip. The height is controlled to be low and strong against deformation. [Structure] It has a LOC structure, and the end portions of each inner lead 13 are fixed onto the main surface of the semiconductor chip 11 with an insulating tape 24. In the insulating tape 24, the conductive film 25 is exposed in a region near the electrode pad 12 where the inner leads 13 are not fixed. The inner leads 13 that are not power pins and the electrode pads 12 of the semiconductor chip 11 are connected by, for example, bonding wires 26 without contacting the conductive film 25. In the electrode pad 12 of the semiconductor chip 11, a pad corresponding to a power supply pad and the conductive film 25 are connected by a bonding wire 27. Further, the conductive film 25 is connected to a lead corresponding to a power supply pin in each inner lead 13 by a bonding wire 28.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】この発明は特にＬＯＣ（lead on
chip）構造の半導体装置に関する。BACKGROUND OF THE INVENTION The present invention is particularly applicable to LOC (lead on
chip) structure semiconductor device.

【０００２】[0002]

【従来の技術】図４は従来のＬＯＣ構造の半導体装置の
構成を示す斜視図である。ＬＯＣ構造は半導体チップ11
主表面上の電極パッド12を半導体チップの中央部に配置
し、各インナリード13の端部を半導体チップ11主表面上
に絶縁テープ14により固着させる。これによりパッケー
ジ15の縮小化を図っている。2. Description of the Related Art FIG. 4 is a perspective view showing the structure of a conventional semiconductor device having a LOC structure. LOC structure is semiconductor chip 11
The electrode pad (12) on the main surface is arranged in the center of the semiconductor chip, and the ends of the inner leads (13) are fixed on the main surface of the semiconductor chip (11) with an insulating tape (14). In this way, the package 15 is downsized.

【０００３】素子の微細化が進む一方、電源の安定化は
不可欠であり、ＬＯＣ構造では電源用リード16を設けて
いる。電源用リード16は各インナリード13の一部から延
在し各インナリード13の端部と半導体チップの電極パッ
ド12の間を横切るように絶縁テープ14上に形成されてい
る。電源用リード16は半導体チップの電極パッド12のう
ちの所定のパッドにワイヤボンディングされる。While miniaturization of the device progresses, it is indispensable to stabilize the power supply. In the LOC structure, the power supply lead 16 is provided. The power supply lead 16 is formed on the insulating tape 14 so as to extend from a part of each inner lead 13 and to cross between the end portion of each inner lead 13 and the electrode pad 12 of the semiconductor chip. The power supply lead 16 is wire-bonded to a predetermined pad of the electrode pads 12 of the semiconductor chip.

【０００４】図５は図４の構成の一部を示す断面図であ
る。絶縁テープ14はその絶縁部材17表裏面に絶縁性の接
着剤18が塗布されており半導体チップと各インナリード
13及び電源用リード16を固定している。FIG. 5 is a sectional view showing a part of the configuration of FIG. The insulating tape 14 has its insulating member 17 coated with an insulating adhesive 18 on the front and back surfaces of the semiconductor chip and each inner lead.
13 and the power supply lead 16 are fixed.

【０００５】上記電源用リード16はインナリード13から
の延在であるのでその厚さはインナリード13と同等で１
２５〜２００μｍある。従って、各インナリード13と電
極パッド12とを接続するボンディングワイヤ19は高いル
ープをもって電源用リード16を飛び越えなければならな
い。Since the power supply lead 16 extends from the inner lead 13, its thickness is the same as that of the inner lead 13.
It is 25 to 200 μm. Therefore, the bonding wire 19 connecting each inner lead 13 and the electrode pad 12 must jump over the power supply lead 16 with a high loop.

【０００６】上記構成によれば、ボンディングワイヤ19
は電源用リード16と接触しないように一定の高さにルー
プ形成されるが、ループ高さが大きく、そのバラツキも
大きい。このため、薄型パッケージに対してはボンディ
ングワイヤ19のループ高さの制御が非常に困難である。
さらに、ボンディングワイヤ19はモールド時、ワイヤ流
れ等、ボンディングワイヤどうし、または電源用リード
16との接触の可能性は一層高くなる。According to the above configuration, the bonding wire 19
The loop is formed at a constant height so as not to come into contact with the power supply lead 16, but the loop height is large and its variation is large. Therefore, it is very difficult to control the loop height of the bonding wire 19 for a thin package.
In addition, the bonding wire 19 may be used for bonding wires, power supply leads, etc.
The chances of contact with 16 are even higher.

【０００７】[0007]

【発明が解決しようとする課題】このように、従来では
電源用リードの存在によりボンディングワイヤのループ
高さが高くなり、制御困難という問題があり、半導体装
置の不良が発生しやすいという欠点がある。As described above, conventionally, there is a problem in that the loop height of the bonding wire is increased due to the presence of the power supply lead, which makes it difficult to control, and a defect of the semiconductor device is likely to occur. .

【０００８】この発明は上記事情を考慮してなされたも
のであり、その目的は、ＬＯＣ構造をとる半導体パッケ
ージ内のボンディングワイヤのループ高さまたは形状を
できるだけ制御しやすいようにした半導体装置を提供す
ることにある。The present invention has been made in consideration of the above circumstances, and an object thereof is to provide a semiconductor device in which the loop height or shape of a bonding wire in a semiconductor package having a LOC structure can be controlled as easily as possible. To do.

【０００９】[0009]

【課題を解決するための手段】この発明の半導体装置
は、半導体チップの主表面上所定の位置に張付けられた
絶縁性テープと、前記絶縁性テープの一表面上もしくは
内部に形成された薄膜の配線層と、前記絶縁性テープに
端部が固着されたインナリードと、前記インナリードと
半導体チップが前記薄膜の配線層を介さずに電気的接続
される第１の接続手段と、前記薄膜の配線層を介して前
記インナリードと前記半導体チップが電気的接続される
第２の接続手段とを具備したことを特徴とする。A semiconductor device according to the present invention comprises an insulating tape attached at a predetermined position on a main surface of a semiconductor chip, and a thin film formed on or inside one surface of the insulating tape. A wiring layer; inner leads whose ends are fixed to the insulating tape; first connecting means for electrically connecting the inner leads and the semiconductor chip without using the wiring layer of the thin film; It is characterized by comprising a second connecting means for electrically connecting the inner lead and the semiconductor chip via a wiring layer.

【００１０】[0010]

【作用】この発明では、薄膜の配線層によってインナリ
ードと半導体チップが電気的接続される第１の接続手段
ではループ高さが低い形状のボンディングワイヤが構成
される。第２の接続手段により半導体チップ表面の任意
の箇所に接続可能となりインナリードの縮小に有利な構
成を得る。According to the present invention, the first connecting means for electrically connecting the inner lead and the semiconductor chip by the thin wiring layer forms a bonding wire having a shape with a low loop height. The second connecting means enables connection to an arbitrary position on the surface of the semiconductor chip, thereby obtaining a structure advantageous for reducing the inner lead.

【００１１】[0011]

【実施例】以下、図面を参照してこの発明を実施例によ
り説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the accompanying drawings.

【００１２】図１はこの発明の一実施例による半導体装
置の要部の構成を示す平面図である。ＬＯＣ構造であ
り、半導体チップ11主表面上の電極パッド12は半導体チ
ップの中央部に配置されている。各インナリード13の一
端部は半導体チップ11主表面上に例えばポリイミドから
なる絶縁テープ24により固着されている。FIG. 1 is a plan view showing a structure of a main part of a semiconductor device according to an embodiment of the present invention. It has the LOC structure, and the electrode pad 12 on the main surface of the semiconductor chip 11 is arranged in the central portion of the semiconductor chip. One end of each inner lead 13 is fixed on the main surface of the semiconductor chip 11 with an insulating tape 24 made of, for example, polyimide.

【００１３】この実施例では絶縁テープ24において各イ
ンナリード13が固着されない電極パッド12寄りのボンデ
ィング領域にＣｕ等からなる導電性膜25が露出してい
る。ここで、電源ピンでない各インナリード13と半導体
チップ11の電極パッド12とは例えばボンディングワイヤ
26により導電性膜25に接触せずに接続されている。In this embodiment, the conductive film 25 made of Cu or the like is exposed in the bonding region of the insulating tape 24 near the electrode pad 12 where the inner leads 13 are not fixed. Here, the inner leads 13 that are not power pins and the electrode pads 12 of the semiconductor chip 11 are, for example, bonding wires.
The conductive film 25 is connected by 26 without coming into contact with it.

【００１４】一方、半導体チップ11の電極パッド12中、
電源パッドに相当するパッドと上記導電性膜25がボンデ
ィングワイヤ27により接続されている。さらに、導電性
膜25は各インナリード13中の電源ピンに相当するリード
にボンディングワイヤ28により接続されている。On the other hand, in the electrode pad 12 of the semiconductor chip 11,
A pad corresponding to a power supply pad and the conductive film 25 are connected by a bonding wire 27. Further, the conductive film 25 is connected to a lead corresponding to a power supply pin in each inner lead 13 by a bonding wire 28.

【００１５】図２は図１の構成の一部を示す断面図であ
る。半導体チップ11と各インナリード13を固定させる絶
縁テープ24はその構造内において絶縁部材31の一表面に
導電性膜25が形成され、その上下に絶縁性の接着剤32が
塗布され、ワイヤボンディングされる領域は露出してい
る。インナリード13が１２５〜２００μｍとすると、絶
縁部材31は４０μｍ、接着剤32は２０μｍ、導電性膜25
は１０μｍ程度で構成される。FIG. 2 is a sectional view showing a part of the configuration of FIG. In the structure of the insulating tape 24 for fixing the semiconductor chip 11 and each inner lead 13, the conductive film 25 is formed on one surface of the insulating member 31, and the insulating adhesive 32 is applied on the upper and lower sides of the conductive film 25 and wire-bonded. Areas are exposed. If the inner lead 13 is 125 to 200 μm, the insulating member 31 is 40 μm, the adhesive 32 is 20 μm, and the conductive film 25 is used.
Is about 10 μm.

【００１６】上記構成によれば、各インナリード13と電
極パッド12とを直接接続するボンディングワイヤ26のル
ープ高さはあまり必要なく、前記図５に比べて各ボンデ
ィングワイヤ26の距離も短く設定できる。また、ボンデ
ィングワイヤ27，28も無理なく任意の場所で接続関係を
構成できる。これにより、従来に比べパッケージ15に薄
型のものを採用できる。According to the above structure, the loop height of the bonding wire 26 for directly connecting the inner leads 13 and the electrode pads 12 is not required so much, and the distance between the bonding wires 26 can be set shorter than that in FIG. . Further, the bonding wires 27 and 28 can be configured to have a connection relationship at any place without difficulty. As a result, a thinner package 15 can be adopted as compared with the conventional one.

【００１７】図３はこの発明の他の実施例を示す図２に
対応する断面図である。前記図５と同様な絶縁性テープ
35を用いる。ボンディング領域部分の接着剤36が除去さ
れ、露出した絶縁部材37上に導電性膜25が形成されてい
る。絶縁性テープ35がより薄くなり各ボンディングワイ
ヤのループ制御はさらに容易になる。FIG. 3 is a sectional view corresponding to FIG. 2 showing another embodiment of the present invention. Insulating tape similar to FIG.
Use 35. The adhesive 36 in the bonding area portion is removed, and the conductive film 25 is formed on the exposed insulating member 37. The insulating tape 35 becomes thinner, and loop control of each bonding wire becomes easier.

【００１８】[0018]

【発明の効果】以上説明したようにこの発明によれば、
ボンディングワイヤのループ高さの制御が容易になり、
ＬＯＣ構造の薄型パッケージに容易に対応できる高信頼
性の半導体装置を提供することができる。As described above, according to the present invention,
It is easy to control the loop height of the bonding wire,
It is possible to provide a highly reliable semiconductor device that can be easily applied to a thin package having an LOC structure.

【図面の簡単な説明】[Brief description of drawings]

【図１】この発明の一実施例による半導体装置の要部の
構成を示す平面図。FIG. 1 is a plan view showing a configuration of a main part of a semiconductor device according to an embodiment of the present invention.

【図２】図１の構成の一部を示す断面図。FIG. 2 is a sectional view showing a part of the configuration of FIG.

【図３】この発明の他の実施例を示す図２に対応する断
面図。FIG. 3 is a sectional view corresponding to FIG. 2 showing another embodiment of the present invention.

【図４】従来のＬＯＣ構造の半導体装置の構成を示す斜
視図。FIG. 4 is a perspective view showing a configuration of a conventional semiconductor device having a LOC structure.

【図５】図４の構成の一部を示す断面図。5 is a cross-sectional view showing a part of the configuration of FIG.

【符号の説明】[Explanation of symbols]

11…半導体チップ、12…電極パッド、13…インナリー
ド、24，35…絶縁テープ、25…導電性膜、26，27，28…
ボンディングワイヤ、31，37…絶縁部材、32，36…接着
剤。11 ... Semiconductor chip, 12 ... Electrode pad, 13 ... Inner lead, 24, 35 ... Insulating tape, 25 ... Conductive film, 26, 27, 28 ...
Bonding wire, 31, 37 ... Insulating member, 32, 36 ... Adhesive.

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】 半導体チップの主表面上所定の位置に張
付けられた絶縁性テープと、 前記絶縁性テープの一表面上もしくは内部に形成された
薄膜の配線層と、 前記絶縁性テープに端部が固着されたインナリードと、 前記インナリードと半導体チップが前記薄膜の配線層を
介さずに電気的接続される第１の接続手段と、 前記薄膜の配線層を介して前記インナリードと前記半導
体チップが電気的接続される第２の接続手段とを具備し
たことを特徴とする半導体装置。1. An insulating tape attached at a predetermined position on a main surface of a semiconductor chip, a thin film wiring layer formed on or inside one surface of the insulating tape, and an end portion of the insulating tape. An inner lead fixed thereto, first connecting means for electrically connecting the inner lead and the semiconductor chip without using the thin film wiring layer, and the inner lead and the semiconductor through the thin film wiring layer. A semiconductor device, comprising: a second connection means to which the chip is electrically connected. 【請求項２】 前記薄膜の配線層を電源用配線に用いる
ことを特徴とする請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the thin film wiring layer is used as a power supply wiring.
JP5040099A 1993-03-01 1993-03-01 Semiconductor device Pending JPH06252329A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5040099A JPH06252329A (en) 1993-03-01 1993-03-01 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5040099A JPH06252329A (en) 1993-03-01 1993-03-01 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH06252329A true JPH06252329A (en) 1994-09-09

Family

ID=12571422

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5040099A Pending JPH06252329A (en) 1993-03-01 1993-03-01 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH06252329A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1050749A (en) * 1996-08-05 1998-02-20 Nec Corp Semiconductor device and manufacturing method thereof
US6303948B1 (en) 1996-02-29 2001-10-16 Kabushiki Kaisha Toshiba Pad layout and lead layout in semiconductor device
US6949824B1 (en) * 2000-04-12 2005-09-27 Micron Technology, Inc. Internal package heat dissipator
KR100523914B1 (en) * 1999-03-03 2005-10-25 주식회사 하이닉스반도체 gold ribbon pre-designed wirc bonding tape tape for bonding wire and method for bonding wire with such wire bonding tape

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6303948B1 (en) 1996-02-29 2001-10-16 Kabushiki Kaisha Toshiba Pad layout and lead layout in semiconductor device
US6617622B2 (en) 1996-02-29 2003-09-09 Kabushiki Kaisha Toshiba Pad layout and lead layout in semiconductor device having a center circuit
JPH1050749A (en) * 1996-08-05 1998-02-20 Nec Corp Semiconductor device and manufacturing method thereof
KR100523914B1 (en) * 1999-03-03 2005-10-25 주식회사 하이닉스반도체 gold ribbon pre-designed wirc bonding tape tape for bonding wire and method for bonding wire with such wire bonding tape
US6949824B1 (en) * 2000-04-12 2005-09-27 Micron Technology, Inc. Internal package heat dissipator
US7163845B2 (en) 2000-04-12 2007-01-16 Micron Technology, Inc. Internal package heat dissipator

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