JPH0625785B2 - Measuring device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a measuring device which measures a deviation amount of a frequency or a phase of an input signal from a reference value, converts the measured value into an analog value, and outputs the analog value. The present invention relates to a measuring device useful as a frequency / voltage converter or a phase / voltage converter of a servo circuit such as an audio device.

Configuration of conventional example and its problems Compared to a measurement device using an analog method, a measurement device using a digital method is more accurate, does not change over time, and has less variation in characteristics during mass production, and adjustment is easy. The advantage is that the utilization rate is rapidly increasing. FIG. 1 is a block diagram showing the configuration of a conventional measuring device using a digital method. In the figure, 1 is an N-stage counter that measures the deviation amount of the frequency or phase of the input signal from the reference value, and this counter has preset data that determines the initial state of the counter.
(d) and the reset signal (PR) that sets the preset data to the counter are applied, and the clock signal (CL) that advances the counting operation and the clock control signal (C ₁ ) that inhibits the clock input are applied to the AND gate 2. Is applied through. The output data (e) and (f) of the counter 1 are supplied to the gate row 3 and the decoder 4, respectively, and the decoder 4 outputs the data.
The gate control signals (C ₂ ) and (C ₃ ) depending on the value of (f) are generated and applied to the gate rows 3 and 5, and the output data (e) supplied to the gate row 3 is the gate row 3 and the gate row 3. After passing through the column 5, the output data (h) is supplied to the M-stage register 6. M
A latch signal (LA) created from the signal under measurement is applied to the register 6 of the stage, and the measured value is stored for a certain period. This stored content is digital as output data (i).
It is supplied to the analog converter 7 and output as an analog value. The outline of FIG. 1 has been described above, and the operation of the measuring device will be described in detail with reference to FIG. 2 showing the signal waveforms and timings of the respective parts of the measuring device shown in FIG.

First, a preset signal (PR) is applied to determine the initial state of the counter 1, and the preset value (NP) is set in the counter 1. At this time, the clock control signal (C ₁ ) prohibits input of the clock signal (CL) to the counter 1 in order to prevent malfunction of the counter 1. When the preset is completed, the prohibition of clock input by the clock control signal (C ₁ ) is released,
The counter 1 counts the clock signal (CL), and the output data of the N-bit counter 1 changes in time series as shown in (f). The downwardly sloping slope portion of (f) represents the digital change amount of the output of the counter 1 in an analog manner. The count data (e) is lower M-bit data of the count data (f), and repeats the same value every 2 ^N counts of the clock signal (CL). The gate control signal (C ₂ ) is
This signal is low level "L" for a period longer than (NH),
On the other hand, the gate control signal (C ₃ ) is a signal which is at the low level “L” while the value of the counter is smaller than (NL). These gate control signals (C ₂ ) and (C ₃ ) are the output data of counter 1.
It can be easily obtained by decoding (f) with a coincidence gate or the like. The output data (h) of the gate row 5 is the gate control signal
Gate control signal to (NH) while (C ₂ ) is "L".
It is fixed to (NL) while (C ₃ ) is "L", and the output data of the counter is as it is as output data (h) only when both (C ₁ ) and (C ₂ ) are at high level "H". Is output. Latch signal
(LA) is an impulsive signal created from the signal under measurement, and the output data at that point in time with each arrival of this impulse
The value of (h) is stored in the register 6 and output as an analog value via the D / A converter 7. This output value measures the time from the application of the preset signal (PR) to the arrival of the latch signal (LA).
The method of clipping and converting the count value with (C ₂ ) and (C ₃ ) is as follows.
(C ₂ ) and (C ₃ ) are both "H" period],
The "M" bit DA converter 7, which has a smaller number of bits than the number "N" of the counter 1 for measurement, is
It is possible to convert up to the accuracy of LSB. By the way, when realizing the measuring device having the configuration shown in FIG.
It can be considered to use an ND gate or a NOR gate. However, since this gate array forcibly changes the data of each bit, each bit requires a gate. For example, in the measuring device of FIG. 1, 2 × M gates are required to form the gate rows 3 and 5. Therefore, it is unavoidable that the circuit configuration becomes complicated, and particularly when the whole is integrated into a circuit, disadvantages such as an increase in chip size due to an increase in the number of gates and a decrease in yield occur. Further, in terms of electrical performance, the increase in the number of gates causes a disadvantage that power consumption increases.

OBJECT OF THE INVENTION It is an object of the present invention to provide a measuring device that can obtain stable D / A conversion characteristics without providing an input gate unit for fixing an input signal of a register.

SUMMARY OF THE INVENTION In summary, the present invention relates to an N-stage counter (1) which performs a counting operation according to an input clock signal after initial setting.
And a latch terminal (Lφ), a set terminal (Sφ), and a reset terminal (Rφ). The output value of the counter is read by the input from the latch terminal and the value is stored at any time.
A register (60) having M stages less than the number of stages, a D / A converter (7) for converting a digital output value of the register into an analog value, and an output of the counter are decoded to maintain the initial state. And outputs a first decode output signal (C2) which is inverted by the first count value of the counter and which is inverted by the second count value while maintaining the state at the time of initialization. The input timing of the measured impulse signal with respect to the input of the decoder (4) that outputs C3) and the first and second decoded output signals (C2, C3) is before the first count value. , A controller for switching and applying the impulse signal to the set terminal, the latch terminal, and the reset terminal between the first and second count values and after the second count value. With this configuration, an impulse signal is applied to the latch terminal Lφ during a predetermined period (from the first count value to the second count value of the counter) to cause the register 60 to perform a latching operation. , D / A conversion is performed according to the count amount of the counter 1, and the register 60 is set or reset outside the predetermined period. Therefore, the register 60
Does not have to worry about reading a false count value outside the predetermined period, and stable D / A conversion having a linear saturation characteristic can be performed. Further, since it is not necessary to fix the input of the register 60, the gate arrays 3 and 5 used in the conventional example are unnecessary.

Description of Embodiments One embodiment of the present invention will be described below with reference to the drawings. FIG. 3 is a block diagram showing the configuration of a measuring device according to an embodiment of the present invention, which is shown by the same numbers and symbols as in FIG. 1, and is a counter 1 for measuring the deviation amount of an input signal, a preset. Data (d), preset signal (PR), clock signal (CL), clock control signal (C ₁ ), AND gate 2, counter output data (e, (f)), decoder 4 and DA converter 7 Is the same as that of FIG. In addition, M
The register 60 of the stage has control signals (Sφ), (Lφ) and (R
φ) can be applied, which is different from the M-stage register 6 in the conventional measuring device in this respect.

The measuring apparatus of the present invention further includes an impulse latch signal (LA) created from the signal under measurement and a decoder 4
From the signals (C ₂ ) and (C ₃ ) output by the register 6
A controller 8 for generating 0 control signals (Sφ), (Rφ) and (Lφ) is applied. FIG. 4 shows the third
It is a figure which shows the signal waveform and timing of each part of the measuring device shown in the figure, but the preset signal (PR), the clock signal (CL) and the clock control signal (C ₁ ) are the same as those in FIG. 2 and are omitted. ing. In FIG. 4, the output (C ₂ ) of the decoder 4 is a signal which becomes “L” until the counter value reaches (NH) after the count operation proceeds after the preset data (NP) is preset in the counter 1. In addition, the decoder output (C ₃ ) is a signal that becomes “L” from when the count operation further progresses and the counter value reaches NL until the preset operation is performed again. Both signals are the signals (C ₂ ) and (C ₃ ) shown in FIG.
Is the same as. The controller output (Sφ) is a latch signal (L) while the decoder output (C ₂ ) is "L".
A control signal generated when A) arrives,
Is set to a fixed value (NH) irrelevant to the output data (e) supplied from the counter 1. In FIG. 4, the period a corresponds to this case, and when the impulse of the latch signal (LA) arrives, only the control signal (Sφ) generates an impulse, and (Rφ) and (Lφ) do not change. Next, in the period of b, the value of the counter 1 is between (NH) and (NL), that is, the decoder outputs (C ₂ ) and (C ₃ ) are both “H”, and the latch signal is It is the coming period. Within this period, the register 60 stores the output data (e) of the counter 1 as it is. During the period of c, the decoder output (C ₃ ) becomes "L" and the latch signal (LA)
The control signal (Rφ) only responds to the impulse of the latch signal (LA), and the register 60
Is set to a fixed value (NL) that is unrelated to the output data (e) of the counter 1. By the way, the value of the register 60 is fixed to a fixed value (N) by the impulses of the control signals (Sφ) and (Rφ).
To set H) and (NL), the memory circuits forming each bit of the register 60 may be set or reset according to fixed values. The D / A converter 7 is for converting the digital value set in the register 60 into an analog value, and the waveform of (OUT) shown in FIG. 4 is D.
-Indicates a change in the analog value of the A converter 7.

FIG. 5 is an embodiment showing a logical configuration of the controller 8 and the M-bit register 60, which are block-displayed in FIG. For example, the register 60 has a 6-bit configuration and includes one inverter 16 and NAND gates 17 to 34.
The whole is composed by. The controller 8 includes inverters 11, 12 and NAND gates 13, 14 and 1
It is composed of 5. The operation of the circuit block shown in FIG. 5 is almost the same as the operation described with reference to FIG. 4, but the output signal of the controller 8 is a negative logic, and the control signals are ( Sφ ) and ( Rφ respectively). ), ( Lφ )
Is written. The operation of the register 60 will be described in the order of the periods a, b, and c described in FIG. First, in the period of a in FIG. 4, only the register control signal (Sφ) generates an impulse and (Rφ) and (Lφ) do not change. Applying this operation to FIG. 5, the control signals ( Lφ ) and ( R
Since φ ) is “H”, the output logic level of the inverter 16 to which ( Lφ ) is applied becomes “L”, and the inverter 1
NAND gates 17, 20, 23, 26, 2 connected to 6
The outputs of 9 and 32 are from the register input data (e ₀ ).
All become "H" regardless of the value of (e ₅ ). by the way,
Each bit of the register is composed of an RS flip-flop and one NAND gate (for example, register 6
If the MSB is 0, it is composed of the RS flip-flop formed by the NAND gates 18 and 19 and the NAND gate 17), and the input signal of the RS flip-flop of each bit is ( Sφ ) It is always "H" ( Sφ )
With the arrival of the impulse, the register outputs (i ₀ ) to (i ₅ ) all become “H”. Similarly in the period of c in FIG. 4, when the impulse of ( Rφ ) arrives, the register outputs (i ₀ ) to (i ₅ ) all become “L”. In the period of FIG. 4b, when the input data (e ₀ ) of the register 60 to the impulse of which the value of (e ₅ ) is (Lφ) arrives, it is set in each RS flip-flop,
Register outputs (i ₀ ) to (i ₅ ) have the same values as (e ₀ ) to (e ₅ ).

As described above, in the measuring device of the present invention, by directly controlling the register for storing the measured value by the control signal, the two-stage gate array which has been conventionally required is not required, and the number of gates is significantly reduced. It will be possible. Further, as is apparent from FIG. 5, the register 60 has the same basic configuration as a known register, and it suffices to add a set terminal and a reset terminal to each bit of the register, which does not increase the number of gates. . Further, the controller 8 also registers 60
The same configuration may be used regardless of the number of stages, and the greater the number of stages of registers, the better the gate reduction efficiency.

Effects of the Invention As described above, when the impulse signal for measurement is input outside the predetermined period, the register is forcibly set or reset, so that the register does not have to worry about reading a false count value. DA that has a linear saturation characteristic
The conversion can be performed stably. Further, since the two-stage gate array used in the conventional example is not necessary for fixing the input signal of the register, it is possible to significantly reduce the number of gates in the entire device.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a conventional measuring device, FIG. 2 is a signal waveform diagram of each part for explaining the operation of the measuring device shown in FIG. 1, and FIG. 3 is a measuring device of the present invention. FIG. 4 is a block diagram showing an embodiment, FIG. 4 is a signal waveform diagram for explaining the operation of the measuring apparatus shown in FIG. 3, and FIG. 5 is a concrete configuration example of a register and a controller of the measuring apparatus of the present invention. It is a logical block diagram shown. 1 ... Counter, 2 ... AND gate, 3,5 ... Gate sequence, 4 ... Decoder, 6,60 ... Register, 7 ...
D / A converter, 8 ... Controller, 11, 12, 16
...... Inverter, 13-15, 17-34 …… NAND
Gate.

Claims (1)

[Claims] 1. An N-stage counter that counts according to an input clock signal after initialization and has a latch terminal, a set terminal, and a reset terminal, and the output value of the counter upon input from the latch terminal. Of M stages, which has less than N stages to read the value of the register, stores the value at any time, a D / A converter that converts the digital output value of the register into an analog value, the output of the counter, and the state at the time of initial setting. And outputs a first decode output signal that is inverted by the first count value of the counter while maintaining a state at the time of initial setting and outputs a second decode output signal that is inverted by the second count value. The output timing of the decoder and the input timing of the measured impulse signal with respect to the input of the first and second decoded output signals are before the first count value, A measuring device, comprising: a controller that switches and applies the impulse signal to the set terminal, the latch terminal, and the reset terminal between the first and second count values and after the second count value.