JPH06260607A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [Abstract] It is an object of the present invention to provide a process for simplifying a lithographic process for forming regions having different conductivity types, which is peculiar to a CMOS structure, and a semiconductor using this process. To provide a device. [Structure] In terms of process, an ion implantation through a photoresist mask or a method of reversing a photoresist pattern is used so that a region having a different conductivity type can be formed by only one lithography step. Further, as a result, in terms of devices, substrates having different well region depths are formed. [Effect] Since the lithography process is simplified, L
The number of manufacturing steps of the SI chip is reduced and the cost is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a metal-oxide film-semiconductor type field effect semiconductor device (metal oxide semiconductor) capable of simplifying the manufacturing process.
miconductorfield effect transistor; hereinafter MOSF
(Abbreviated as ET) and its manufacturing method.

[0002]

2. Description of the Related Art A dynamic random access memory, which is a typical example of an integrated circuit using a MOSFET, is currently mass-produced at 4 megabits using a 0.8-micron technology. In addition, mass production of 16-megabit, which uses the next-generation 0.5 micron technology, has started even though it is small. There is no doubt that semiconductor devices will be reduced in size and the degree of integration will be improved in combination with advances in miniaturization technology. By the way, miniaturization of semiconductor elements such as MOSFET has not been achieved simply by reducing the size, but an undesirable phenomenon such as a short channel effect and a punch-through phenomenon which becomes remarkable as the size is reduced. It is also the result of effective suppression. The guideline in this case is the proportional reduction rule, and according to this, along with the size reduction, the substrate concentration is increased, the gate oxide film is thinned,
In addition, the source / drain diffusion layers have been made shallow. In the future, in order to miniaturize semiconductor elements, especially MOSFETs, it is unavoidable to follow this guideline.
The number of man-hours for manufacturing the OSFET is increasing, which causes a big problem of increasing manufacturing cost.

MOS with a gate electrode size of 0.5 μm or less
The cross-sectional shape of the FET is as shown in FIG. A CMOS structure is adopted in order to suppress an increase in power consumption, and in particular, an impurity layer inside the substrate is complicatedly formed in order to cope with miniaturization. For example, (5) and (6) are impurity layers formed to improve element isolation characteristics. Since these impurity layers have a CMOS substrate structure, as will be described later, one region is covered with a mask such as a photoresist, and the impurities are ion-implanted only in the open portions. , Repeat once again to form a different region.
Thus, the photoresist process for forming different impurity regions includes a well forming process, an element isolation forming process, a channel ion implantation process for controlling the threshold voltage, a low concentration diffusion layer forming process, as described later. It is an indispensable step in the CMOS structure such as a high-concentration diffusion layer forming step.

A conventional manufacturing process of a semiconductor device will be described in detail with reference to FIGS. First, as shown in FIG. 3A, on the surface of the p-type 10 Ω · cm semiconductor substrate (1),
An oxide film (20) is grown to a thickness of about 20 nm by using a known thermal oxidation method. Further, a silicon nitride film (21) having a thickness of 100 nm is formed on this surface by using a known vapor deposition method.
Deposit to a degree. Next, as shown in FIG. 3B, the nitride film (21) is processed into a desired shape using the photoresist mask (22) to expose the surface of the oxide film (20). The processing of the nitride film (21) is stopped at the oxide film (20). Further, as shown in FIG. 3C, the nitride film (2
Using 1) as a mask, phosphorus is ion-implanted. The implantation amount is about 10 ¹² to 10 ¹³ / cm ² . The implantation energy was 60 KeV. After that, FIG.
As shown in (d), when the surface is oxidized, the nitride film (2
Since the region covered in 1) is not oxidized, the oxide film (20 ') selectively grows on the substrate surface.

Then, as shown in FIG. 3E, the nitride film (22) is removed and the selectively grown oxide film (2) is formed.
Boron is ion-implanted using 0 ') as a mask. The implantation amount is 10 ¹² to 10 ¹³ / cm ² . Here, B
Boron was introduced using F ₂ ions. The implantation energy is 60 KeV.

Next, as shown in FIG.
A heat treatment is performed at 0 ° C. to thermally diffuse phosphorus (2) and boron (3) implanted in the substrate (1) to form a well region having a depth of about 3 μm. This completes the step of forming well regions having different conductivity types in the same substrate (1). Since the selective oxidation method is used in the well formation, the photoresist pattern forming step may be performed only once. Next, an element isolation region is formed. Also in this step, the selective oxidation method as described above is used. As shown in FIG. 4B, the surface of the substrate (1) is covered with an oxide film (20) and a nitride film (21).
The oxide film and the nitride film have film thicknesses of 15 nm and 100, respectively.
nm. As shown in FIG. 4C, the nitride film (21) is used as a mask with the photoresist (22) as a mask.
A pattern is formed in the active region of the FET (region where the source / drain and channel of the MOSFET are formed). Then, as shown in FIG.
When oxidized at about ℃, the oxidation proceeds selectively,
The oxide film (4) grows only in the region not covered with the nitride film (21). The film thickness is about 400 nm. As it is, the element isolation characteristics are insufficient, so that the impurity concentration at the interface between the oxide film (4) and the substrate is increased to improve the isolation characteristics. Therefore, ion implantation is performed through the oxide film (4). For this purpose, a photoresist mask (22) covering the p-well region (3) is formed, and phosphorus is ion-implanted into the opened n-well region (2). Oxide film (4)
Phosphorus was implanted at 200 KeV in order to bring the peak concentration position of the impurity layer to the interface between the substrate and the substrate. The implantation amount is about 10 ¹³ / cm ² .

Next, as shown in FIG. 5 (a), the n-well region (2) is covered with a photoresist mask (22), and a boron concentration peak position exists at the interface of the oxide film (4). Ion implantation is performed with. Driving energy is 1
50 KeV, the implantation amount is about 10 ¹³ / cm ² .
Usually, after this ion implantation, a mask process is applied to each of the n-well and p-well to improve the short channel characteristics of the MOSFET and to adjust the threshold voltage, and appropriate impurities are ion-implanted. To do. However, this step is omitted here for the sake of simplicity. This completes the formation of the element isolation region, and the MOS
The process shifts to the production of the FET. Therefore, first, the surface of the substrate (2) is cleaned to expose the substrate surface in the active region, and then a gate oxide film (7) of about 10 nm is grown, and further, as shown in FIG. A gate electrode (8) is formed. Polycrystalline silicon containing 10 ²⁰ / cm ³ or more of phosphorus was used for the gate electrode. Next, MOSFET
A diffusion layer to be the source and drain of is formed. Therefore, first, as shown in FIG. 5C, a MOSF to be a pMOSFET is formed by using a photoresist mask (22).
ET is exposed and BF ₂ is added here at ₂₀ KeV, 5x1
Ion implantation is performed under the condition of 0 ¹³ / cm ² . here,
The process is described using a so-called electric field relaxation type MOSFET structure, and this step is for forming a low-concentration p-type diffusion layer (9). Similarly, in order to form an n-type diffusion layer, the MOSFET to be an nMOSFET is exposed and phosphorus is ion-implanted under the conditions of ²⁰ KeV and 5 × 10 ¹³ / cm ² . As a result, the low concentration n
A mold diffusion layer (10) is formed (FIG. 5 (d)).

Next, a high-concentration diffusion layer is formed. Before that, a sidewall insulating film (11) is formed only on the sidewall of the gate electrode (8) as shown in FIG. 5 (e). . this is,
By removing the insulating film deposited on the entire surface of the substrate by a known anisotropic dry etching method, it can be formed in a self-aligned manner.

Then, as shown in FIG. 6 (a), the region to be the pMOSFET is exposed again, and BF ₂ is added to 30.
Ion implantation is performed under the conditions of KeV and 5 × 10 ¹⁵ / cm ² . Since the side wall insulating film (11) is provided on the side wall of the gate electrode (8), the low concentration diffusion layer (9) and the high concentration diffusion layer (12) are formed.
And are displaced according to the film thickness of the sidewall insulating film, and are effective in alleviating the electric field. Similarly, as shown in FIG.
Arsenic is exposed to 30K by exposing the region that will be the nMOSFET.
Ion implantation was performed under the conditions of eV and 5 × 10 ¹⁵ / cm ² (13). 6C and 6D show a process of forming an interlayer insulating film and a wiring, wherein (14) is an interlayer insulating film, (15) is tungsten filling a contact hole, ( 16) is a metal whose main component is aluminum, which serves as wiring.

[0010]

As described in detail above, in the conventional method for manufacturing an LSI having a CMOS structure, it is necessary to form MOSFETs having different conductivity types on the same substrate, and therefore impurities are introduced. Each time, one M
A step of covering the OSFET with a photoresist mask is required. This step includes the steps of coating a resist film, exposing with an exposure machine, developing with a developing solution, and baking for hardening the resist. As described above, in the CMOS structure, it is repeated several times. It is a process that is performed. Further, after the ion implantation, there is a cleaning step such as removing the resist used as a mask. Since oxygen plasma is usually used for removing the resist, there is a risk of destroying the gate oxide film in a situation where the gate oxide film is exposed. In addition, when removing the resist, there is a problem that heavy metal contamination or the like, which is implanted in the resist and is caused by ion implantation, remains on the substrate surface, which is one of the causes of a decrease in the yield of LSI.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor device capable of simplifying a lithography process for forming regions having different conductivity types, which is peculiar to a CMOS structure, and a manufacturing method thereof.

[0012]

SUMMARY OF THE INVENTION In order to solve these problems and simplify the impurity introduction process for forming a CMOS structure and reduce the manufacturing cost of LSI, the present invention is as described below. Devised a process. The details will be described in the embodiment, but the main point is to implant different types of impurity ions using only a mask covering one MOSFET. One way is
Ion implantation through a mask. Impurities are, of course, implanted into the region not covered with the mask, but by adjusting the implantation energy and the film thickness of the mask, as shown in the sectional view of the semiconductor device of the present invention in FIG. It is possible to form an impurity layer in a deep region of the substrate that does not affect. In FIG. 1, since the boron implantation is performed through the mask, the impurity layer made of boron (p well of 3 and 6) is located deeper than the impurity layer made of phosphorus shown in the n wells (2) and (5). Existing. Further, for the ion implantation of impurities through such a mask, high-energy ion implantation capable of obtaining an acceleration voltage of megavolt was used. Another way is
As described in the second embodiment, it is a method of transferring a mask pattern. By using photoresists having different photosensitivity to light, a method capable of easily forming an inverted pattern of one pattern was used.

[0013]

In the method of introducing impurities according to the present invention, when high energy ion implantation is used, double well formation,
It can also be used for introducing impurities into the interface of the element isolation oxide film. In addition to this, in the CMOS structure, there is a possibility that this method can be used for setting the threshold voltage. However, regarding the formation of a diffusion layer such as a source / drain that requires a relatively shallow junction, it is difficult to use this method when the high-energy ion implantation is used because the impurity distribution spreads according to the energy. However, in an LSI which does not require much miniaturization, the present invention can be applied to the step of forming the diffusion layer by appropriately selecting the film thickness of the mask.

If a mask pattern transfer method is used, the present invention can be applied to any of the above steps. By using the present invention, the number of steps in the step of introducing impurities is reduced, the number of times an expensive apparatus such as an exposure apparatus is used is reduced, and the exposure apparatus can be used more efficiently. As a result, the manufacturing cost of the LSI chip can be reduced. It is difficult to make a simple trial calculation, but it is thought that the maximum man-hours can be reduced by about 20%.

[0015]

Embodiments of the present invention will now be described in detail with reference to the drawings. First, in the conventional method of manufacturing a semiconductor device having a CMOS structure, as shown in FIG. 3D, by using the selective oxidation method, the n well region (2) and the p well region (3) are formed. Can make a step. This step is formed when the photoresist pattern (22) in the active region is formed (see FIG.
(C)) It serves as a reference for alignment and is indispensable for performing accurate alignment. On the other hand, in the embodiment of the present invention, since the selective oxidation method is not used, the step as a reference for mask alignment is not formed. Therefore, it is possible to previously form another alignment pattern on the substrate surface by using another pattern, but this is not suitable for the purpose of the present invention aiming at simplification of the process. Therefore, in the present invention,
The method of detecting the pattern on the back surface of the substrate, which is disclosed in Japanese Patent Laid-Open No. 62-115164, is adopted. In this method, in addition to the conventional detection pattern formed on the front surface of the substrate, a pattern is also formed on the back surface to improve the alignment accuracy. In the embodiment of the present invention, as shown in the schematic diagram of the substrate of FIG. 7A, when the substrate manufacturer puts the serial number on the back surface with the laser processing device, the detection pattern is also formed. Is. Lithography was performed using an exposure apparatus modified so that the back surface could also be irradiated with detection light. Only the step of forming the well pattern and the element isolation region pattern needs to be detected by the back surface, and after that, the step formed by the element isolation pattern can be used for detection. As shown in FIG. 7A, an oxide film (20) is grown to a thickness of about 20 nm on the surface of the semiconductor substrate (1) (p-type 10 Ω · cm) having the detection pattern on the back surface as described above.

A photoresist pattern (22) is formed on this surface.
Are formed, and phosphorus is ion-implanted for the n-well region as shown in FIG. In the present embodiment, unlike the above-described conventional CMOS structure, the impurity distribution is set by using high energy ion implantation in order to omit the step of well diffusion requiring a long heat treatment. Therefore, phosphorus was added at 2 MeV, 1 MeV, 0.5 M
It was driven in 3 times with the acceleration energy of eV. The implantation amount is 5 × 10 ¹² to 1 × 10 ¹³ / cm ² .
FIG. 12 shows the impurity distribution of phosphorus. As a characteristic of high energy ion implantation, an asymmetric shape with a smooth distribution in the surface direction has been obtained. The concentration after heat treatment is about 3 × 10 ¹⁶ / cm ³ , and the depth is about 3
μm. Also, in order to prevent this phosphorus from being implanted into the p well region, a photoresist mask (22)
Had a thickness of 3 to 4 μm. Next, as shown in FIG. 7C, boron is ion-implanted in order to form a p-well while leaving the photoresist mask (22). In order to implant boron into the substrate through the photoresist mask, the implanting energy was set to a maximum of 5 MeV, and the implanting was performed in three steps of 4 MeV and 3 MeV. The driving amount is from 5x10 ¹² to 1x1
It is 0 ¹³ / cm ² . The impurity distribution at this time is shown in FIG. Almost the same distribution as that of phosphorus was obtained, and the depth was about 2.5 μm. On the other hand, boron is also implanted into the n-well region not covered with the photoresist mask, and a boron layer is formed below the phosphorus impurity layer. This is shown in FIG. 12, which has a depth of 4 μm.
It was found that boron was present in the range of 6 μm.
No defect was observed inside the substrate due to the small implantation amount. This substrate was heat-treated at 1000 ° C. for about 60 minutes to obtain a substrate having a well distribution as shown in FIG. 7 (d). It is a feature of the substrate according to the invention that there is a p-type region (3) having a higher concentration than the substrate (1) under the n-well region (2). Further, in order to realize the conventional well structure, heat treatment at a high temperature of about 1100 ° C. for several tens of hours is required.
Only heat treatment at 0 ° C. for 60 minutes is performed. This leads to shorter processing time and energy savings. On the surface of this substrate, as shown in FIG. 7E, an oxide film (4) is deposited to a thickness of about 400 nm. This oxide film (4) becomes an oxide film forming an element isolation region. In the conventional MOSFET, the element isolation region is formed by using the selective oxidation method as described above, but this step requires long-time oxidation.
Further, since the element isolation characteristics are determined by the distribution of the impurities implanted in the oxide film interface as described above, it is not always necessary to adopt the conventional selective oxidation method.
In this example, the deposited oxide film was used for the element isolation region in consideration of shortening the process time.

Next, as shown in FIG.
A pattern is formed to expose the active region of the FET. A mask alignment method using a backside alignment pattern was also used for patterning the element isolation region. Then, the same mask (2
2) is used to implant impurity ions having different conductivity types into the oxide film interface. First, as shown in FIG. 8B, an oxide film (20) for preventing contamination due to ion implantation is grown on the substrate surface. Further, a mask (22) for protecting the p well region (3) is formed, and phosphorus is ion-implanted. In order to bring the peak concentration position to the oxide film interface, phosphorus ions were implanted with an energy of 200 KeV. Phosphorus (5) is also implanted into the substrate not covered with the oxide film. The driving amount is 1 × 10 ¹³ /
cm ² . Next, with the photoresist mask (22) left as it is, as shown in FIG. 8C, boron is ion-implanted into the p-type region. The thickness of the mask (22) is 1
Since the oxide film (4) has a thickness of 400 μm and a thickness of 400 nm, the implantation energy of boron is set to about 1.5 MeV. Since the resist mask has an ion blocking ability (a parameter indicating the ability to stop the progress of ions) of about half that of an oxide film, the depth of boron in the well region not covered with the oxide film (4) is about 0. N-type MOSF that is 5 μm and is formed on the surface
It does not affect the characteristics of ET. Further, boron is also implanted into the p-well region not covered by the mask (22), but since this is about 2 μm deep,
It does not affect the characteristics of the p-type MOSFET. Next, FIG.
As shown in (d), the photoresist mask is removed, and heat treatment is applied to activate the implanted impurities.
The heat treatment time is 900 ° C. and 10 minutes. Furthermore, FIG.
As shown in (e), a sidewall oxide film (4 ') is formed on the sidewall of the oxide film (4), and the step formed by the oxide film is inclined. This is to facilitate pattern formation in the subsequent steps.

The subsequent steps are exactly the same as the conventional CMOSFET manufacturing steps. First, as shown in FIG. 9A, a gate oxide film (7) is grown to form a gate electrode (8) into a desired shape. Next, a photoresist mask (22) is formed as shown in FIG.
A p-type layer (9) to be a low concentration diffusion layer of SFET is formed by BF ₂ implantation. Further, as shown in FIG. 9C, nM
Photoresist mask (22) with the OSFET region opened
Are formed, and phosphorus is ion-implanted. Then, in FIG.
After forming the sidewall insulating film (11) on the sidewall of the gate electrode (8) as shown in (d), a region of the pMOSFET is opened to form a high-concentration p-type diffusion layer (12). Similarly, a high concentration n-type diffusion layer (13) is formed as shown in FIG. Finally, as shown in FIGS. 10A and 10B, the deposition of the interlayer insulating film (14), the formation of the contact hole, the filling (15) thereof, and the formation of the wiring (16) are completed, and the The semiconductor device of the invention is completed.

In the above-described first embodiment of the present invention, the example in which the high-energy ion implantation technique is used to implant impurities in different well regions by only one mask pattern formation is described. However, in high-energy ion implantation, it is very difficult to control the distribution, and it is necessary to find optimal conditions in advance. In order to simplify the process by performing the photoresist mask formation process accompanying the introduction of impurities, which is frequently performed to realize the CMOS structure, in one mask process, as a second embodiment, high energy ion implantation is performed. I devised a method that does not use. For this purpose, a method of applying another photoresist on the patterned photoresist and forming a reverse pattern of the existing pattern was adopted. The second embodiment will be described with reference to FIG. Note that this embodiment is different from the first embodiment using high-energy ion implantation, and can be used for steps requiring high-concentration ion implantation, such as the formation of a MOSFET diffusion layer, but the procedure is the same for all steps. Since the steps are common, the well formation will be described here as an example, and the others will be omitted. First, as shown in FIG.
An oxide film (20) of about 20 nm is grown on the surface of the p-type 10 Ω · cm substrate (1). Next, as shown in FIG. 13B, after forming a photoresist pattern (22), phosphorus is ion-implanted. The implantation conditions are the same as the conditions used when forming a conventional CMOS structure. The photoresist is a positive type resist in which a region irradiated with light remains. Next, as shown in FIG. 13C, a negative photoresist (22 ') is applied on the entire surface. The negative photoresist is also formed on the positive resist as shown in the figure. Therefore, as shown in FIG. 13D, the surface of the negative resist (22 ′) is exposed by removing the vicinity of the surface of the positive resist (22) in oxygen plasma. Then, when the entire surface is irradiated with light, the positive resist (22) is exposed to the light and can be removed by the developing solution. As a result, as shown in FIG.
The negative resist (22 ') with the pattern reversed is left. Using this as a mask, boron is ion-implanted to form a p-well as shown in FIG. Further, as shown in FIG. 14C, heat treatment is performed to realize a double well structure.

[0020]

According to the present invention described above, it is not necessary to perform two lithographic steps to form regions having different conductivity types. In the first embodiment, since a special device called high-energy ion implantation is used, it is not possible to form a high-concentration impurity layer due to problems such as crystal defects, but in the second embodiment, an inversion pattern is used. Therefore, any ion implantation process can be applied.

In the CMOS structure, the lithography process for forming such an impurity layer includes a well forming process, an element isolation forming process, a channel ion implantation process, a low concentration diffusion layer forming process, a high concentration diffusion layer forming process, and the like. It is necessary and occupies about 20% of the CMOS process. In these steps, if the present invention is carried out, not only the steps can be shortened, but also the high temperature heat treatment step can be eliminated as described in the first embodiment, so that the maintenance cost of the manufacturing line can be reduced. It also contributes to the reduction of chip costs, etc., and the chip cost can be reduced.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of a conventional semiconductor device.

FIG. 3 is a diagram showing a manufacturing process of a conventional semiconductor device.

FIG. 4 is a diagram showing a manufacturing process of a conventional semiconductor device.

FIG. 5 is a diagram showing a manufacturing process of a conventional semiconductor device.

FIG. 6 is a diagram showing a manufacturing process of a conventional semiconductor device.

FIG. 7 is a view showing a manufacturing process of the semiconductor device according to the first embodiment of the invention.

FIG. 8 is a diagram showing a manufacturing process of the semiconductor device according to the first embodiment of the invention.

FIG. 9 is a diagram showing a manufacturing process of the semiconductor device according to the first embodiment of the invention.

FIG. 10 is a diagram showing a manufacturing process of the semiconductor device according to the first embodiment of the invention.

FIG. 11 is a boron concentration distribution in the p-well region.

FIG. 12 is a phosphorus and boron concentration distribution in an n-well region.

FIG. 13 is a view showing a manufacturing process of the semiconductor device according to the second embodiment of the invention.

FIG. 14 is a diagram showing a manufacturing process of the semiconductor device according to the second embodiment of the invention.

[Explanation of symbols]

1 ... P-type semiconductor substrate, 2 ... N-well region, 3 ... P-well region, 4, 4 '... Element isolation region, 5 ... Phosphorus impurity layer, 6
... Boron impurity layer, 7 ... Gate oxide film, 8 ... Gate electrode, 9 ... Boron low concentration diffusion layer, 10 ... Phosphorus low concentration diffusion layer, 11 ... Side wall oxide film, 12 ... Boron high concentration diffusion layer, 13 ... Arsenic high-concentration diffusion layer, 14 ... Interlayer insulating film, 1
5 ... Metal filling contact holes, 16 ... Wiring metal, 20
... oxide film, 21 ... nitride film, 22, 22 '... photoresist.

Front page continuation (72) Inventor Shizuka Oyu 1-280 Higashi Koigokubo, Kokubunji, Tokyo Inside Hitachi Central Research Laboratory

Claims (5)

[Claims] 1. A first-conductivity-type semiconductor substrate is provided with a first-conductivity-type semiconductor region and a second-conductivity-type semiconductor region having a concentration higher than that of the semiconductor substrate, and the first-conductivity-type semiconductor region is provided below the first-conductivity-type semiconductor region. A semiconductor device, wherein a semiconductor region of two-conductivity type is present, or a semiconductor region of the first-conductivity type is present under the semiconductor region of the second-conductivity type. 2. The first and second semiconductor regions are provided with third and fourth semiconductor regions having the same conductivity type as the respective regions and having a high concentration, and the third and fourth semiconductor regions are provided under the third semiconductor region. Either there is a semiconductor region whose conductivity type and concentration are substantially the same as those of the fourth semiconductor region, or there is a semiconductor region whose conductivity type and concentration are substantially the same as that of the third semiconductor region below the fourth semiconductor region. The semiconductor device according to claim 1, wherein 3. The semiconductor device according to claim 1, further comprising a MOS transistor having a gate insulating film and a gate electrode formed on the surface of the semiconductor substrate. 4. A first desired portion of the surface of the semiconductor substrate is first formed.
And a second step of ion-implanting impurities into the semiconductor region not covered with the first organic film several times by using the first organic film as a mask. A third step of implanting impurities through the first organic film several times to form a region having a conductivity type different from that of the semiconductor region formed in the second step; A fourth step of applying a heat treatment, a fifth step of forming an oxide film on a second desired portion of the surface of the semiconductor substrate, and a second organic film on the first desired portion of the surface of the semiconductor substrate. Is formed, and using this as a mask, a sixth step of ion-implanting impurities into the semiconductor region not covered with the second organic film; and the impurity and conductivity that are ion-implanted in the sixth step. Form areas of different molds To do so, a seventh step of implanting impurities into the surface of the semiconductor substrate through the second organic film, an eighth step of removing the second organic film, and a gate oxidation on the surface of the semiconductor substrate. And a ninth step of forming a MOS transistor having a film, a gate electrode, and a source / drain region. 5. A first step of forming a positive type first photosensitive organic film on a first desired portion of the surface of a semiconductor substrate, and using the first photosensitive organic film as a mask, A second step of ion-implanting an impurity into a semiconductor region not covered with the first photosensitive organic film, and thereafter forming a negative second photosensitive organic film on the surface of the semiconductor substrate; And a surface of the first photosensitive organic film formed in the first step by removing the vicinity of the surface of the second photosensitive organic film formed in the third step. Exposing the entire surface of the first and second light-sensitive organic films, and then exposing the positive-type first light-sensitive layer formed in the first step. Fifth step of exposing the photosensitive organic film to light and selectively removing the first photosensitive organic film, and thereafter, the semiconductor A sixth step of ion-implanting an impurity having a different conductivity type from the impurity ion-implanted in the second step using the second photosensitive organic film remaining on the surface of the plate as a mask. A method for manufacturing a characteristic semiconductor device.