JPH06260618A - Nonvolatile semiconductor storage - Google Patents

Abstract

(57) [Abstract] [Purpose] It is possible to perform programming after the bit line is formed, even though the miniaturization is possible and the processing of the memory cell is easy. [Structure] The bit line 22 and the word line 12 are orthogonal to each other, and the gate electrode 15 is branched from the word line 12 between the bit lines 22 in a direction along these bit lines 22. Therefore, the gate electrode 15 is not located under the bit line 22, and after the bit line 22 is formed, programming by ion implantation under the gate electrode 15 can be performed. Moreover, no alignment margin is required between the bit line 22 and the gate electrode 15 in the extending direction of the gate electrode 15, and it is not necessary to avoid the gate electrode 15 and extend the bit line 22.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device in which a program is written and information is written before use.

[0002]

2. Description of the Related Art FIG. 3 shows an ion implantation program type NOR mask RO which is a kind of nonvolatile semiconductor memory device.
The 1st prior art example of M is shown. In the first conventional example, the field oxide film 11 selectively formed on the surface of the semiconductor substrate and the gate oxide film formed on the surface of the active region sandwiched by the field oxide film 11 are A word line 12 made of a polycrystalline Si film extends, and a portion of the word line 12 on the active region serves as the gate electrode 15 of the transistor 14 in each memory cell 13.

One side of the word line 12 in the active region is a source region, that is, a source line 16 common to a plurality of memory cells 13 arranged along the word line 12. The other side of the word line 12 in the active region is
The drain region 17 is common to the two memory cells 13 arranged in the direction orthogonal to the word line 12.

A contact hole 21 reaching the drain region 17 is provided in the interlayer insulating film covering the word line 12 and the like. The bit line 2 formed of an Al film extends above the active region in the direction orthogonal to the word line 12.
2 is in contact with the drain region 17 via the contact hole 21.

FIG. 4 shows an ion implantation program type NO.
The 2nd prior art example of R type mask ROM is shown. This second
In the conventional example, the bit line 22 extends above the field oxide film 11, and the contact hole 2 of the bit line 22 is formed.
The drain region 1 has a wide portion 22a only in the vicinity of 1
7 and has a configuration substantially similar to that of the first conventional example shown in FIG. 3 except that the wide portion 22a contacts the drain region 17 through the contact hole 21. is doing.

In both the first and second conventional examples described above, the gate electrode 1 is doped with impurities of the same conductivity type as the semiconductor substrate, that is, the conductivity type opposite to the source line 16 and the drain region 17.
5 and the gate oxide film are ion-implanted into the channel region, and the threshold voltage of the transistor 14 is increased to such an extent that the transistor 14 does not conduct at the voltage applied to the gate electrode 15 for programming. .

[0007]

However, in the first conventional example shown in FIG. 3, since the bit line 22 made of an Al film extends above the active region in the direction orthogonal to the word line 12, The gate electrode 15 is located below the bit line 22. Therefore, it is necessary to perform ion implantation for programming before forming the bit line 22, and the TAT from receiving the code data from the user to delivering the product is long, resulting in low product competitiveness.

On the other hand, in the second conventional example shown in FIG. 4, since the bit line 22 extends above the field oxide film 11, the gate electrode 15 is located below the bit line 22. Absent. Therefore, the ion implantation for programming can be performed after the bit line 22 is formed.
TAT is shorter than the conventional example.

However, in the second conventional example, in order to prevent the gate electrode 15 from being located below the bit line 22,
It is necessary to make the width of the field oxide film 11 wider than the width of the bit line 22 by A ₁ + A ₂ as a margin.
It was difficult to reduce the area of the memory cell 13 and miniaturize it.

Moreover, the bit line 22 has a contact hole 2
While contacting the drain region 17 via 1,
In order to extend in a state where the gate electrode 15 is avoided, it has a wide portion 22a. For this reason, the bit line 22 that is located above the word line 12 and is not easily patterned cannot be linearly patterned, and the processing of the memory cell 13 is not easy.

[0011]

According to another aspect of the non-volatile semiconductor memory device of the present invention, a bit line 22 and a word line 12 extend in a direction intersecting with each other, and a gate electrode 15 of a memory cell 13 has the bit line. It is characterized by branching from the word line 12 in the direction along these bit lines 22 between the two.

A nonvolatile semiconductor memory device according to a second aspect is the nonvolatile semiconductor memory device according to the first aspect, characterized in that the memory cell 13 has a floating gate.

A nonvolatile semiconductor memory device according to a third aspect is the nonvolatile semiconductor memory device according to the first or second aspect, characterized in that the source line 16 has a shunt.

A non-volatile semiconductor memory device according to a fourth aspect is the non-volatile semiconductor memory device according to the third aspect, wherein the shunt is formed of a conductive film in the same layer as the bit line 22.

[0015]

In the nonvolatile semiconductor memory device according to the present invention, since the gate electrode 15 is not located below the bit line 22, it is possible to carry out programming by ion implantation below the gate electrode 15 after forming the bit line 22. it can. Moreover, since the gate electrode 15 is branched from the word line 12 in the direction along the bit line 22, there is no need for a margin for alignment between the bit line 22 and the gate electrode 15 in the extending direction of the gate electrode 15, and the memory cell 13 is not necessary. The area of the bit line 22 can be reduced, and the bit line 22 can be linearly patterned without having to avoid the gate electrode 15 and extend the bit line 22.

Since the gate electrode 15 is arranged between the bit lines 22 along the bit line 22, the source line 16 is also arranged between the bit lines 22 along the bit line 22. Therefore, the shunt of the source line 16 can be formed by the conductive film in the same layer as the bit line 22, and the shunt of the source line 16 can be formed by a simple process and a high yield.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention applied to a NOR mask ROM of an ion implantation programming system will be described below with reference to FIGS.
Will be described with reference to. The first shown in FIGS.
The same reference numerals are given to the components corresponding to those of the second conventional example.

In order to manufacture this embodiment, FIG.
As shown in, the field oxide film 11 is formed on the surface of the semiconductor substrate 23 by the LOCOS method, and the gate oxide film 24 is formed on the surface of the active region sandwiched by the field oxide film 11. The field oxide film 11 has a plane pattern as shown in FIG. After that, although not shown, impurities are ion-implanted in advance in a portion of the active region, which is to be the source line 16 later and in which the word line 12 extends.

Next, polycrystalline Si having a film thickness of about 300 nm
The film is deposited on the entire surface by the CVD method, and impurities are introduced into the polycrystalline Si film by the predeposition method at 950 ° C. for about 30 minutes. After that, a photoresist (not shown) is patterned on the polycrystalline Si film, and RIE is performed on the polycrystalline Si film using this photoresist as a mask, as shown in FIG.
The word line 12 and the gate electrode 15 are completed as shown in FIG. The photoresist is then removed.

As shown in FIG. 1, the word lines 12 are provided with branch portions which alternately project toward the adjacent word lines 12 which are arranged with the active region sandwiched therebetween. Of the branch portions, the active regions are provided. The upper portion is used as the gate electrode 15. As described above, the word line 12 and the gate electrode 15 are not linear as a whole, but since they are located below the bit line 22,
Similarly, the bit line 22 in the second conventional example which is not linear
In comparison with the above, the word line 12 and the gate electrode 15 of this embodiment are
Is easy to pattern.

Then, using the gate electrode 15 and the field oxide film 11 as a mask, impurities are ion-implanted into the semiconductor substrate 23. As described above, since the impurity is ion-implanted in advance in the portion of the active region, which is to be the source line 16 later and the word line 12 extends, the above-described ion implantation for the semiconductor substrate 23 is performed. Due to the implantation, one side of the gate electrode 15 in the active region is
5 becomes a source region, that is, a source line 16 common to the plurality of memory cells 13 arranged in the extending direction of 5. Further, the other side of the gate electrode 15 in the active region becomes the drain region 17 common to the two memory cells 13 arranged in the extending direction of the word line 12.

Next, a SiO ₂ film or the like having a film thickness of about 500 nm is deposited on the entire surface to form an interlayer insulating film 25 for covering the word lines 12, the gate electrodes 15, etc., as shown in FIG. 2C. . Then, a photoresist (not shown) is patterned on the interlayer insulating film 25, and RIE is performed using this photoresist as a mask to form a contact hole 21 reaching the drain region 17 in the interlayer insulating film 25 and the like. The photoresist is then removed.

Next, an Al film having a film thickness of about 1 μm is deposited on the entire surface, a photoresist (not shown) is patterned on the Al film, and this photoresist is used as a mask to form an Al film.
Perform RIE on the membrane. Accordingly, FIG. 1 and FIG.
As shown in (d), the bit line 22 that contacts the drain region 17 through the contact hole 21 and extends between the gate electrodes 15 in a direction orthogonal to the extending direction of the word line 12 is completed. . The photoresist is then removed. The NOR type mask ROM of this embodiment is made and stored in this state.

After that, when code data is received from the user, impurities 26 are selectively ion-implanted into the channel region from above the gate electrode 15 of the transistor 14 to be made non-conductive according to the code data, and programming is performed. For this program, for example, B ⁺ ions are ion-implanted at an acceleration energy of 500 keV and a dose amount of 1 × 10 ¹⁵ cm ⁻² .

After that, a P-SiN film or the like having a film thickness of about 1 μm is deposited on the entire surface to form an overcoat film 27 which covers the bit lines 22 and the like. Then, a photoresist (not shown) is patterned on the overcoat film 27, and RIE is performed on the overcoat film 27 using this photoresist as a mask to form an opening (not shown) for the electrode pad. The photoresist is then removed.

In the present embodiment manufactured as described above, as is apparent from FIG. 1, the gate electrode 15 is the bit line 22.
Since it is not located below, bit line 2 made of Al film 2
2 does not hinder ion implantation for programming.

Since the gate electrode 15 branches off from the word line 12 in the direction along the bit line 22, the bit line 22 extends in the extending direction of the gate electrode 15 as in the second conventional example shown in FIG. Between the gate electrode 15 and the gate electrode A ₁ +
The bit line 22 can also be linearly patterned without the need for A ₂ . In the direction orthogonal to the extending direction of the gate electrode 15, the bit line 22 and the gate electrode 15
It is necessary to have a margin B between the line and
The same applies to the second conventional example shown in FIG.

As is clear from the above description of the manufacturing method, this embodiment can be manufactured by substantially the same steps as those of the first and second conventional examples shown in FIGS. The risk of is extremely small, and this embodiment can be manufactured efficiently.

In the above embodiment, all word lines 1 are
2 is formed of a polycrystalline Si film of the same layer, but if the adjacent word lines 12 are formed of polycrystalline Si films of different layers, these word lines 12 can be overlapped, so that the memory cell 13 The area of can be further reduced. In this case, after forming one of the adjacent word lines 12 and the interlayer insulating film 25 in the above process, the semiconductor substrate 23 in the region where the gate electrode 15 is to be formed is exposed, and the gate oxide film 24 is formed again. Then, the other of the adjacent word lines 12 is formed.

As is clear from FIG. 1, the source line 1
Since the bit line 22 does not extend above 6 the shunt of the source line 16 can be formed above the source line 16 with an Al film in the same layer as the bit line 22. Further, the above-mentioned embodiments are the NOR masks R of the ion implantation program system.
Although the present invention is applied to the OM, the present invention can also be applied to an EPROM having a floating gate.

[0031]

In the non-volatile semiconductor memory device according to the present invention, the area of the memory cell can be reduced, so that miniaturization is possible, and the bit line can be linearly patterned, so that the memory cell is processed. Although it is easy to perform, the TAT is short because the programming can be performed after the bit line is formed. Further, since the shunt of the source line can be formed by a simple process and a high yield, high speed operation can be realized at low cost.

[Brief description of drawings]

FIG. 1 is a plan view of an embodiment of the present invention.

FIG. 2 is a side cross-sectional view showing the manufacturing method of the embodiment in the order of steps and taken along a line II-II in FIG. 1.

FIG. 3 is a plan view of a first conventional example of the present invention.

FIG. 4 is a plan view of a second conventional example of the present invention.

[Explanation of symbols]

 12 word line 13 memory cell 15 gate electrode 16 source line 22 bit line

Claims (4)

[Claims] 1. A bit line and a word line extend in a direction intersecting with each other, and a gate electrode of a memory cell is branched from the word line in a direction along the bit line between the bit lines. And a nonvolatile semiconductor memory device. 2. The non-volatile semiconductor memory device according to claim 1, wherein the memory cell has a floating gate. 3. The non-volatile semiconductor memory device according to claim 1, wherein the source line has a shunt. 4. The non-volatile semiconductor memory device according to claim 3, wherein the shunt is made of a conductive film in the same layer as the bit line.