JPH06260655A - Planar superlattice transistor - Google Patents

Abstract

PURPOSE:To provide a planar superlattice transistor wherein electron waves are perpendicularly applied to a superlattice having a cyclic potential. CONSTITUTION:A GaAs layer 2 of 8000Angstrom is deposited on a semi-insulating GaAs substrate 1 by MBE, and an n-Al0.22Ga0.28As layer 3 of 300Angstrom is deposited thereon; the n-AlGaAs layer has almost at the center a vertical superlattice obtained by alternately forming an AlAs layer 3a and an AlGaAs layer 3b, 100Angstrom each, approx. 10 cycles. A source electrode S and a drain electrode D are formed in the source/drain region. The vertical superlattice is located between the source and drain electrodes S and D, and is parallel therewith. Two gate electrodes G are formed in the center of the area between the source and drain electrodes S and D; the gate electrodes are separated by a split distance d of 1000Angstrom in the direction perpendicular to the source and drain to form a split gate electrode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a planar superlattice transistor used as an element for ultra high speed digital.

[0002]

2. Description of the Related Art Planar superlattice transistors (washboar
(also referred to as d transistor) has a periodic potential utilizing a superlattice in the electron traveling direction, and when the wavelength of the electron wave with a long elastic scattering length and the period of the potential coincide with each other, the electron wave causes Bragg reflection. Is a transistor that utilizes the fact that it does not conduct. The potential of the superlattice structure alternates different values, and the change is periodic. FIG. 2 shows a wave function when twice the period (L) of this potential matches the wavelength (λ) of the electron wave. In the upper and lower parts of the figure, the incident electron wave (Φ) and the standing wave (Ψ) are shown by broken lines, respectively, and the squares of the incident electron wave and the standing wave are shown by solid lines, respectively. As shown in FIG. 2, when λ = 2L is satisfied, a standing wave appears and the electron wave does not propagate.

The operation principle of the transistor will be described below by taking a planar superlattice transistor using a two-dimensional electron gas (2DEG) at the AlGaAs / GaAs hetero interface as an example. The planar superlattice transistor utilizes that the Fermi wavelength λ _F of the electron wave is inversely proportional to the square root of the sheet carrier concentration N _S of the electron as shown in the following formula (1).

[0004]

[Equation 1]

Here, assuming that the unit charge of electrons is e, the gate capacitance is C, and the threshold voltage is V _th , the sheet carrier concentration N _S when the voltage V is applied to the gate is expressed by the following equation (2). Represented by. eN _S = C (V−V _th ) ... (2)

Therefore, when the Fermi wavelength λ _F of the electron wave is changed by controlling the voltage V applied to the gate so that the following equation (3) is satisfied, the electrons traveling from the source to the drain through the gate undergo Bragg reflection. It awakens and does not conduct, and the transistor is turned off. On the other hand, when a voltage which does not satisfy the following expression (3) is applied to the gate, the transistor is turned on. 2L = n · λ _F (where n: integer) (3)

For example, when the potential period L is 200Å, when a gate voltage is applied so that N _S = 4 × 10 ¹¹ cm ^-2 , λ _F becomes about 400Å, at which time electrons are Bragg-reflected. And the transistor is turned off. Since the coherence of the electron waves is used, it is necessary that the elastic scattering length (le) of the electron waves is long, that is, the electron mobility (μ) is large, in order to cause Bragg reflection. In AlGaAs / GaAs 2DEG,
le needs to be about 10 μm (in this case, μ = 10 ⁶ cm ⁻² / secV).

The time until the Bragg reflection occurs and the conduction stops after the wavelength of the electron changes, or vice versa, depends on the change in the carrier concentration expressed by the above equation (2). It is limited by the time required. Therefore, in such a planar superlattice transistor,
High-speed switching operation on the order of sec. is possible. Further, since a negative resistance appears with respect to the gate voltage, there is also an advantage that an XOR circuit can be configured with one element.

[0009]

The condition for operating the above-described planar superlattice transistor is that the wavelength λ of the electron and the period L of the formed potential match. In order to satisfy this condition, it is necessary that electrons having a wavelength represented by the equation (3) are incident perpendicularly on the superlattice having a periodic potential. Figure 3
(a) shows the periodic potential of the superlattice with the energy taken on the vertical axis, and Fig. 3 (b) shows the superlattice with the periodic potential shown in Fig. 3 (a) where the electron wave It is a top view which shows the state which conducts. Even if the electron wave has a wavelength satisfying the expression (3), when it is obliquely incident on the superlattice as shown by A, Bragg reflection does not occur.
On the other hand, when an electron wave having the same wavelength as A enters perpendicularly to the superlattice as shown by B, Bragg reflection occurs.

Even with an electron wave having a wavelength that does not satisfy the expression (3), Bragg reflection may occur when it is obliquely incident on the superlattice. Such a phenomenon reduces the negative resistance with respect to the gate voltage and reduces the difference in output current during on / off. As a result, there is a problem in that the on / off is undefined.

Therefore, in a transistor having a superlattice between a source and a drain, an attempt has been made to process a channel between the source and the drain into a fine line in order to make electrons enter the superlattice perpendicularly. The size is limited to about 1000Å. However, in order to vertically inject electrons, it is necessary to make the effective channel width 1000 Å or less, and thus it is extremely difficult to realize vertical incidence by microfabrication technology. The present invention has been made in view of such circumstances, and provides a planar superlattice transistor capable of vertically injecting an electron wave into a superlattice by including a split gate having a predetermined interval. The purpose is to

[0012]

A planar superlattice transistor according to the present invention is a planar superlattice transistor having a vertical superlattice in a semiconductor layer between a source electrode and a drain electrode, and a direction orthogonal to the source / drain direction is predetermined. It is characterized in that it is provided with split gate electrodes divided at intervals.

[0013]

In the present invention, since the split gate electrode is provided, when a voltage is applied to the split gate electrode, the region directly under the gate electrode is depleted, so that the electron injected from the source electrode does not have a depletion layer. Through the semiconductor layer under the split. At this time, the depletion layer under each gate electrode also extends in the lateral direction and also extends to the semiconductor layer under the split, so that the effective channel width can be made smaller than the split interval. By thus forming the channel layer having a fine width perpendicularly to the superlattice, it is possible to make the electron wave incident perpendicularly to the superlattice.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to the drawings showing the embodiments. FIG. 1 is a schematic view showing a planar superlattice transistor according to the present invention, FIG. 1 (a) shows this plan view, and FIG. 1 (b) shows this sectional view. A GaAs layer 2 is deposited on the semi-insulating GaAs substrate 1 by 8000 Å by MBE (Molecular Beam Epitaxy) method. On top of that, an AlAs layer 3a and an AlGaAs layer 3b 1
A vertical superlattice having approximately 10 cycles alternately for every 00 Å is formed by laminating 300 Å layers of N-Al _0.22 Ga _0.78 As layer 3 (silicon concentration 2 × 10 ¹⁸ cm ^-3 ) formed in the substantially central portion thereof. A source electrode S and a drain electrode D are formed in the source / drain regions, respectively, and the vertical superlattice is located between the source electrode S and the drain electrode D. It is parallel to D. Further, in the central portion between the source electrode S and the drain electrode D, two gate electrodes G, G are arranged in a direction orthogonal to the source / drain direction.
The split gate electrodes are formed side by side with a split distance d of 1000Å.

In the planar superlattice transistor having the above structure, the vertical superlattice forms a periodic potential as shown in FIG. 3 (a). And N-Al
_The electrons supplied from the _0.22 Ga _0.78 As layer 3 are GaAs
When a sheet carrier concentration of about 5 × 10 ¹¹ cm ^{-2 is} accumulated in the layer 2 and a voltage of about 0.1 V is applied between the source electrode S and the drain electrode D, the drain electrode passes from the source electrode S to under the split gate electrode. The electron wave progresses toward D. At this time, if a negative bias of about -1 to -2 V is applied to the split gate electrode, the gate electrodes G and G are completely depleted and electrons cannot flow, and pass through under the split. Here, since the depletion layer spreads in the lateral direction by several hundred Å, the effective channel width becomes 1000 Å or less even if the split distance d is 1000 Å, and the electron wave is incident perpendicularly on the superlattice having the periodic potential. And proceeds toward the drain electrode D.

In this embodiment, the number of splits is one, but the number of splits is not limited to one. Further, in this embodiment, AlAs is used as a material for the superlattice.
Although AlGaAs and AlGaAs were used, other materials may be used as long as they form a periodic potential as shown in FIG.

[0017]

As described above, the planar superlattice transistor according to the present invention has the split gate electrodes divided at a predetermined interval. Therefore, when a voltage is applied to the split gate electrodes, the portions directly under each gate electrode are depleted, The electrons injected from the source electrode pass through the semiconductor layer below the split. In this way, by limiting the channel width in which the electrons move and making it fine, it becomes possible to make the electron wave incident perpendicularly to the superlattice, and to efficiently interfere the electron wave with the periodic potential. In addition, the present invention has excellent effects such that the ON / OFF ratio of the element output can be increased.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a planar superlattice transistor according to the present invention.

FIG. 2 is a diagram showing a wave relationship when twice the potential period and the Fermi wavelength of an electron match.

FIG. 3 is a diagram showing a periodic potential of a superlattice and a state in which an electron wave is conducted through the superlattice.

[Explanation of symbols]

1 GaAs substrate 2 GaAs layer 3 N-Al _0.22 Ga _0.78 As layer 3a AlAs layer 3b AlGaAs layer G gate electrode S source electrode D drain electrode

Claims (1)

[Claims] 1. A planar superlattice transistor having a vertical superlattice in a semiconductor layer between a source / drain electrode, comprising a split gate electrode in which a direction orthogonal to the source / drain direction is divided at predetermined intervals. Planar superlattice transistor.