JPH0626370B2 - Transmission / reception method - Google Patents

Description

The present invention relates to a transmission / reception method for receiving data returned in response to a transmission command.

[Conventional technology]

Conventionally, as shown in FIG. 5, each of the communication interfaces 2 _-1 to 2- _n is connected to a transmission line L extending from the master station 1, and data at these communication interfaces 2 _-1 to 2- _n is connected. There is known a communication system in which a master station 1 returns a transmission command in response to the transmission command.

Communication interface 2 _-1 to 2 _-n includes a temperature sensor, a humidity sensor, a sensor section 2 _-11 to 2 _-n1 and the driver receiver unit 2 _-12 to 2 _-n2 such smoke sensor, the sensor unit 2 _{- 11} ~
The data detected by 2- _n1 is the driver / receiver unit _{2-12
Set to} digital input data (DI) at ~ 2- _n2, and respond to the send command with this digital input data, master station 1
Return to.

FIG. 6 shows an outline of the internal configuration of the master station 1, which is the CP.
It includes U1 _-1 and master LSI 1 _-2 . That is,
At the point t ₁ shown in FIG. 7, the CPU _1-1 is the master LSI 1
_-2 is accessed and transmission of the transmission command TX is started.
Then, the transmission end signal TX _END of this transmission command TX
It was confirmed by CPU 1 _{-1 (t 2} points), the master LSI 1 _-2
The control for is switched from the previous transmission sequence to the reception sequence. That is, after confirming the transmission end signal TX _{END in} the CPU _1-1 , reception of the reception data RX in response to the transmission command TX is started (t ₃ point), and the reception end signal RX _END of the reception data RX is obtained ( t ₄ points),
Processing takes in the received data RX into CPU 1 _-1.

[Problems to be Solved by the Invention]

However, according to such a transmission and reception method, each time receiving a transmission end signal TX _END, is interrupted processing sequence of the CPU 1 _-1, the performance was to decrease.

[Means for Solving the Problems]

The present invention has been made to solve such a problem, and writes the number of received bytes, which is determined according to the type of the transmission command, in the first storage means, and the reception data returned in response to the transmission command. To the second storage means, and after writing the received data by the number of received bytes, after confirming the stop code at the end of the received data, the reception end of the received data is stored in the third storage means. Writing and interrupting the CPU, the interrupted CPU reads the contents of the third storage means, confirms the reception end of the reception data, and then reads the reception data written in the second storage means. It's something that you do.

[Action]

Therefore, according to the present invention, after the transmission command is transmitted, the reception data corresponding to the number of reception bytes (the number of reception bytes written in the first storage means) determined according to the type of the transmission command are received and the stop is performed. After confirming the mark, the CPU is interrupted for the first time, and the interrupted CPU confirms the reception end of the reception data from the content of the third confirmation storage means and then writes it to the second storage means. The received data is read.

〔Example〕

 Hereinafter, the transmission / reception method according to the present invention will be described in detail.

FIG. 2 is a diagram showing the outline of the internal configuration of a controller (master station) to which this transmission / reception method is applied. In the figure, 3 _-1 is a CPU, 3 _-2 is a master LSI, and master LSI 3 _-2 is a transmission side fifo (TX FIFO).
3 _-21 , reception side fifo (RXFIFO) 3 _-22 , control register 3 _-23 and status register 3 _-24
Is equipped with.

FIG. 1 is a flow chart showing the processing operation of the CPU 3 _{-1 in} this controller 3. To explain the operation in accordance with the flow chart, CPU 3 _-1, first writes transmission data to the transmitting side Faifo 3 _-21 (step 101). That is, in the transmission command TX shown in FIG. 3, the type indicating the number of bits of the digital input data (DI) to be received and the address designating the communication interface that provides this transmission command TX are used as transmission data. 3 write to _-21. After the writing of the transmission data, the transmission start instruction and the number of received bytes are written in the control register _3-23 (step 102). That is, in the reception data RX shown in FIG. 3, the number of bytes is uniquely determined corresponding to the type defined in the transmission command TX, and the reception data RX is uniquely determined.
_Is written in the control register _3-23 as the number of received bytes (the number of received bytes determined according to the type of the transmission command TX). Control register _3-23
Transmission start command and the number of received bytes are written to the transmission side Faifo 3 _-21 and status register 3 _-24,
It is given to the receiving Faifo 3 _-22.

And Thus, CPU 3 _-1 starts the transmission sequence of the master LSI 3 _-2 (step 103). That is,
The master LSI 3 _-2 starts transmitting the transmission command TX from the transmission side fifo 3 _-21, and the transmission command TX
The received data RX which sent back from the communication interface on which it was received, and writes to the receiving side Faifo 3 _-22.
Then, after completion of writing of the received data RX of the only few minutes receiving bytes determined corresponding to the transmission command TX, with informing the receiving end of the received data RX to status register 3 _-24, an interrupt to the CPU 3 _-1. CP
In U3 _-1, while "other process" (step 105), and checks for an interrupt from the master LSI 3 _-2 (step 104), an interrupt is applied,
The "other processing" in step 105 is interrupted, the contents of the status register _3-24 are read, and the received data R
Check the reception end of X (step 106), performs the reading of the received data Rx written to the receiving Faifo 3 _-22 (step 107).

In addition, in the reading of the contents of the status register _3-24 in step 106, if it is not confirmed that the reception of the reception data RX is completed, the master LSI is processed by another processing operation.
It is judged that an interrupt has occurred from 3 _-2 to the CPU 3 _-1 , or that some abnormality has occurred and the processing operation in the master LSI 3 _-2 has failed, and so on.
_{Take measures} such as not reading the received data RX from _-22 .

Further, in the present embodiment, the received data is received by the number of received bytes determined in correspondence with the transmission command TX,
For the first time, it was to interrupt the CPU3 _-1,
If a stop code is inserted at the end of the received data RX as shown in FIG.
It is also possible to interrupt U3 _-1 , and if this method is used in combination with the method of receiving the reception data of the number of reception bytes and interrupting it, it becomes more reliable.

〔The invention's effect〕

As is apparent from the above description, according to the transmission / reception method of the present invention, after the transmission command is transmitted, the number of reception bytes determined according to the type of the transmission command (the number of reception bytes written in the first storage means). Only after receiving the received data for only minutes and confirming the stop mark, CP
Since U is interrupted, the processing operation of the CPU is not frequently interrupted and its performance is improved.

Further, the interrupted CPU confirms the reception end of the reception data from the contents of the third storage means, and then the second CPU
Since the reception data written in the storage means is read, if it is not confirmed that the reception of the reception data has been completed, it is determined that some kind of abnormality has occurred and the processing operation is not successful. It is possible to deal with it by not reading the received data from the storage means.

[Brief description of drawings]

FIG. 1 shows the CP in the controller shown in FIG.
FIG. 2 is a flow chart showing the processing operation performed by U, FIG. 2 is a diagram showing the outline of the internal configuration of the controller to which the transmitting / receiving method according to the present invention is applied, and FIG. 3 is the input / output of transmission commands and reception data in this controller. Figure showing the state,
FIG. 4 is a diagram showing another embodiment of input / output states of transmission commands and reception data in this controller, and FIG. 5 returns data in the communication interface connected to each unit in response to a transmission command from the master station. FIG. 6 is a diagram showing a communication system configured to do so, FIG. 6 is a diagram showing an outline of an internal configuration of the master station in this communication system, and FIG. 7 is an input / output state of a transmission command and reception data in the master station. It is a figure. 3 ... Controller, 3 _-1 ...... CPU, 3 _-2 ...... Master LSI, 3 _-21 ...... Transmit side phifo, 3 _-22 ...... Receive side phifo, 3 _-23 ...... Control register, 3 _-24 ...
... Status register, TX ... Send command, RX ...
…received data.

Front Page Continuation (72) Inventor Atsushi Katsunori 1-12-2 Kawana, Fujisawa-shi, Kanagawa Yamatake Honeywell Co., Ltd. Fujisawa Plant (72) Inventor Tetsuo Kimura 1-11-6 Hatagaya, Shibuya-ku, Tokyo Nittan stock In-house (72) Inventor Katsuhiro Kishimura 1-11-6 Hatagaya, Shibuya-ku, Tokyo Nitsutan Co., Ltd. (72) Inventor Koji Ouchi 1-1-11 Hatagaya, Shibuya-ku, Tokyo Nitsutan Co., Ltd. (72) Hideto Amamiya Hideto Amamiya 1-11-6 Hatagaya, Shibuya-ku, Tokyo Within Nittan Co., Ltd. (56) Reference JP-A-1-123551 (JP, A) JP-A-61-88635 (JP, A) ) JP-A-62-94042 (JP, A)

Claims (1)

[Claims] 1. The number of received bytes determined according to the type of transmission command is written in a first storage means, the reception data returned in response to the transmission command is written in a second storage means, and this reception data is written. After the end of writing for the number of the received bytes, the stop code at the end of the received data is confirmed, the reception end of the received data is written to the third storage means, and the CPU is interrupted and interrupted. The transmitting / receiving method, wherein the CPU reads the contents of the third storage means, confirms the reception end of the reception data, and then reads the reception data written in the second storage means. .