JPH06266576A - Semiconductor ic - Google Patents

Abstract

(57) [Summary] [Object] To provide a semiconductor integrated circuit capable of performing a functional test of a central processing unit and a memory circuit at a high speed and having a low manufacturing cost. [Structure] External instruction input signals B and R
The OM expected value input signal C is input in a time-sharing manner in each half cycle of the instruction cycle via the test-purpose terminal 37. The external instruction input signal B is synchronized with the clock signal φ2 by the latch circuit 51,
Latched during the instruction cycle, the expected ROM value input signal C is latched during the instruction cycle by the latch circuit 51 in synchronization with the clock φ1. By giving an address signal from the counter 35 to the ROM 34, the output value output from the ROM 34 is compared with the above-mentioned expected value in the comparison circuit 45, and the determination result is output as the ROM determination output signal F.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit including a central processing unit and a memory circuit and incorporating circuits necessary for functional testing of these circuits.

[0002]

2. Description of the Related Art Generally, a semiconductor integrated circuit is subjected to various functional tests before being shipped as a product in order to confirm whether or not the functions described in the specifications are satisfied.

FIG. 5 is a block diagram showing an electrical configuration of a conventional semiconductor integrated circuit 1 and a test apparatus 2 for performing a functional test thereof. The semiconductor integrated circuit 1 includes a central processing unit (hereinafter abbreviated as “CPU”) 3, a read-only memory (hereinafter abbreviated as “ROM”) 4, and the like, and a method of functional testing thereof will be described below.

The function test of the CPU 2 includes a CPU function test using an external instruction signal (hereinafter abbreviated as "external instruction test") and the like. When performing this test, first, an external instruction signal, that is, an instruction code is given to the CPU 3 from the test input circuit 6 to the CPU 3 via the external instruction input terminals TI1 to TIn (reference numeral 7 is used for generic name). Since the test input circuit 6 gives the instruction code in synchronization with the instruction cycle of the CPU 3 (a unit cycle of processing based on the instruction code), the oscillation circuit 8
The clock signals φ1 and φ2 from are input from the clock output terminals for synchronization.

Next, when an instruction code is given to the CPU 3, an output value corresponding to the instruction code is given from the CPU 3 to the comparison circuit 11 via the data bus 9b. Random access memory (hereinafter abbreviated as "RAM") 12
Stores, in advance, output values corresponding to a plurality of instruction codes as expected values.
3 is read out and output to the comparison circuit 11. Therefore, the comparison circuit 11 latches the expected value in advance, compares it with the output value output from the CPU 3, determines whether or not both values match, and outputs the determination result to the CPU determination signal. As the test device 2 via the output terminal 19 as
Output to. In this way, the test apparatus 2 repeats the above-mentioned external instruction test for a plurality of predetermined instruction codes, and based on the judgment result, the CPU 3
The function of is judged.

A ROM-D is used for the functional test of the ROM4.
There is a UMP test etc. When performing this test, the counter 15 sequentially increments the count value for each cycle of the instruction cycle in synchronization with the clock signal φ2 output from the oscillation circuit 8, and uses the count value as a sequential address signal on the address bus 10a. Through ROM
Give to 4.

When the address signal is applied to the ROM 4, the test device 2 outputs the output value corresponding to the address signal via the data bus 9c and the output terminals TRD1 to TRDn (reference numeral 16 is used for generic name). Comparing circuit 17
Output to. An expected value corresponding to the output value of the ROM 4 described above is stored in advance in the comparison circuit 17, and the output value of the ROM 4 is compared with the expected value to determine whether or not both values match. To do. In this way, the test apparatus 2 operates on the above-mentioned ROM for the addresses in the predetermined range.
-The DUMP test is repeated, and based on the judgment result, R
The function of OM4 is judged.

As described above, the external instruction test of the CPU 3 and the DUMP test of the ROM 4 are simultaneously performed within the same instruction cycle.

FIG. 6 is a diagram showing details of the external instruction input terminal 7 and the ROM output terminal 16 shown in FIG. The external instruction input terminal 7 and the ROM output terminal 16 have n terminals TI1 to T, respectively.
It is formed of In and terminals TRD1 to TRDn.

FIG. 7 shows the external instruction signals I1 to In and the ROM output data RD1 to RD shown in FIG.
FIG. 7 is a circuit diagram of test terminals T1 to Tn capable of inputting and outputting both of n and n. If the test terminals are also used in this way, the number of test terminals shown in FIG. 7 can be reduced to 1/2 as compared with the number of test terminals shown in FIG.

FIG. 8 shows the test terminals T1 to T1 shown in FIG.
6 is a time chart when Tn is applied to the semiconductor integrated circuit 1 shown in FIG. 5 and a functional test is performed. In this case, since the input terminal for the external instruction signal and the output terminal for the ROM output data signal are also used, the CPU function test by the external instruction signal and the ROM function test by the ROM output data cannot be performed at the same time. Therefore, the external instruction signal and the ROM output data are alternately input / output at each of the instruction cycles (two cycles of the original oscillation clock X1) at the test terminals T1 to Tn in synchronization with the clock signal φ2 to perform the external instruction test. The ROM-DUMP test is alternately performed.

[0012]

In the conventional semiconductor integrated circuit, when the external instruction test by the external instruction signal and the ROM-DUMP test by the output data of the ROM are simultaneously performed as described above, the tests are alternately performed. Compared with the case, the number of test input / output terminals is significantly increased. Therefore, the manufacturing cost of the semiconductor integrated circuit increases.

If the external instruction test and the ROM-DUMP test are alternately performed with the input / output terminals also used in order to reduce the input / output terminals for the test, the test time is significantly increased.

An object of the present invention is to enable functional tests of the built-in central processing circuit and storage circuit to be performed quickly.
Another object of the present invention is to provide a semiconductor integrated circuit with low manufacturing cost.

[0015]

According to the present invention, there is provided a central processing circuit for executing an operation in a predetermined cycle based on an instruction code given from the outside, and a memory circuit for reading data in the predetermined cycle. And a first comparison circuit for judging suitability by comparing the arithmetic processing result output from the central arithmetic processing circuit with the data stored in advance during the functional test, and the storage circuit during the functional test. A second comparison circuit for comparing the data read from the external test device with expected value data given from an external test device to determine suitability; and alternately from the external test device at a cycle shorter than the predetermined cycle. An input circuit which holds a given instruction code and expected value data for the predetermined period and gives them to the central processing unit and the memory circuit, respectively. It is a body integrated circuit.

[0016]

As described above, according to the present invention, the central processing unit executes the operation at a predetermined cycle based on the instruction code given from the outside, and the memory circuit reads the data at the predetermined cycle. Is done. When performing a functional test, the first comparison circuit compares the arithmetic processing result output from the central arithmetic processing circuit with prestored data to determine suitability, and the second comparison circuit The suitability is judged by comparing the data read from the memory with the expected value data given from the external test apparatus. At this time, the input circuit holds the instruction code and the expected value data, which are alternately given from the external test device in a cycle shorter than the predetermined cycle, for the predetermined cycle and stores the central processing circuit and the memory. Give to the circuit. Therefore, the function test of the central processing unit and the function test of the memory circuit can be simultaneously input with a signal by using the same input terminal, and the function test can be simultaneously performed, and the number of input terminals does not increase.

Further, by providing the second comparison circuit, the signal output from the second comparison circuit to the outside may be only the signal of the determination result, so that the number of output terminals can be greatly reduced.

[0018]

1 is a block diagram showing an electrical configuration of a semiconductor integrated circuit 31 and a test apparatus 32 for performing a functional test of the semiconductor integrated circuit 31 according to an embodiment of the present invention. Semiconductor integrated circuit 31
Is a central processing unit (hereinafter abbreviated as “CPU”) 3
3, read-only memory (hereinafter abbreviated as "ROM") 3
4, etc., and the functional test thereof will be described below.

The function test of the CPU 32 includes a CPU function test by an external instruction signal (hereinafter abbreviated as "external instruction test") and the like. ROM
The functional test of 34 includes a ROM-DUMP test and the like.
In this embodiment, the external instruction test and the ROM-DUMP test described above are simultaneously performed based on the time chart shown in FIG.

From the test input device 36 of the test device 32,
The external test input signal A is the test dual-purpose terminals TP1 to TPn.
(Reference numeral 37 is used for generic name).
In the external test input signal A, as shown in FIG. 2, the external instruction input signal B and the ROM expected value input signal C are time-divided in each half cycle. At every instruction cycle (unit time in which the CPU or the like performs processing based on the instruction code) t1, the external instruction signal A1 is output at time t3 in synchronization with the rise of the clock signal φ2, and in synchronization with the rise of the clock signal φ1. The ROM expected value input signal A2 is output at time t4. The clock signal φ1 and the clock signal φ2 are generated based on the clock original signal X and output from the oscillation circuit 38. Clock signals φ1 and φ2 are output from the oscillator circuit 38 to the test input circuit 36, and the test input circuit 36 outputs the clock signals φ1 and φ2.
An external test input signal A is generated based on 1, φ2.

As shown in FIG. 3, the test combined terminal TP1
.About.TPn can be input / output by also using the external test input signal A and the normal input / output signal P. Since the instruction code of the external instruction signal and the data of the ROM expected value input signal are composed of n bits, the number of the test combined terminals 37 to which the signal is input and output is n.

The external instruction signal A1 included in the test input signal A input to the dual-purpose test terminals TP1 to TPn is latched by the clock signal φ2 in the latch circuit 51, and the external instruction input signal B is output.
Is generated. In addition, RO included in the test input signal A
The M expected value input signal A2 is latched by the clock signal φ1 in the latch circuit 52, and the ROM expected value input signal C is generated. This external instruction signal B
And the ROM expected value input signal C, as shown in FIG.
The signals are output in every cycle t1 of the instruction cycle in synchronization with the clock signal φ2 and the clock signal φ1, respectively.

Next, the external instruction signal B is
It is input to the CPU 33 via the data bus 39a, that is, an instruction code is given to the CPU 33. CPU33
When the instruction code is applied to the comparator, an output value corresponding to the instruction code is applied to the comparison circuit 41 via the data bus 39b. A random access memory (hereinafter abbreviated as “RAM”) 42 stores output values corresponding to a plurality of instruction codes in advance as expected values, and the expected values corresponding thereto are read out by the CPU 33, and the comparison circuit 41. Is output to. Therefore, the comparison circuit 41 latches the output expected value, compares it with the output value output from the CPU 33, determines whether or not both values match, and determines the determination result by the CPU. The output signal is output to the test apparatus 32 via the output terminal 46. In this way, the test apparatus 32 repeats the above-described external instruction test for a plurality of predetermined instruction codes, and determines the function of the CPU 33 based on the result of the determination.

Next, the ROM expected value input signal C is output to the comparison circuit 45. In addition, the counter 35 includes the oscillation circuit 3
In synchronization with the clock signal φ2 output from the ROM 8, the count value is sequentially incremented, and the count value is used as a sequential address signal via the address bus 10a in the ROM 3
Give to 4. When the address signal is applied to the ROM 34, the internal ROM data D corresponding to the address signal is output to the comparison circuit 45 via the data bus 39c.
Therefore, the comparison circuit 45 outputs the ROM expected value input signal C
Value is compared with the value of the internal ROM data D to determine whether or not both values match, and the determination result is output as a ROM determination output signal to the test apparatus 32 via the output terminal 47. To do.

In this way, the test apparatus 2 repeats the above-mentioned function test with respect to the address in the predetermined range, and judges the function of the ROM 43 based on the judgment result.

Although the ROM expected value input signal C and the internal ROM data D have the same cycle (instruction cycle t1) as shown in FIG. 2, the phase of the ROM expected value input signal is the phase of the internal ROM data D. Time t3, that is, 1 / of the instruction cycle t1
Two cycles behind. Therefore, the value of the ROM expected value input signal C and the value of the internal ROM data D can be compared only at the time t4 for each instruction cycle t1. In the comparison circuit 45, the comparison circuit 45
If the data values match as a result of the comparison, the ROM determination output signal F is output at a high level, and if they do not match, the ROM determination output signal F is output at a low level. Also, ROM test strobe signal G
Is output at the timing when the ROM determination output signal stabilizes, and when the level of the determination circuit output signal F is determined in synchronization with the ROM data strobe signal G, the accurate comparison circuit 4
The determination result of 5 can be obtained.

FIG. 4 is an electric circuit diagram of the comparison circuit 45. The comparison circuit 45 uses the EX. It is composed of NOR gates 61 to 6n and an AND gate 70. n EX. N
The OR gates 61 to 6n are n-bit internal ROMs.
The data D and the ROM expected value input signal C are compared for each corresponding bit. When the values in the corresponding bits of the internal ROM data D and the expected ROM value input C are equal,
That is, when both signals are low level or high level, the output E of the comparison circuit 45 becomes high level.

Therefore, the internal ROM data D and the ROM
When the values of all corresponding bits of the expected value input signal C are equal, the inputs of the AND gate 70 are all at the high level, so that the output of the AND gate 70, that is, RO
The M determination output signal F becomes high level. Also, internal RO
If even one of the corresponding bit values of the M data D and the ROM expected value input signal C differs, the output of the AND gate 70 becomes low level, and the ROM determination output signal F becomes low level.

[0029]

As described above, according to the present invention, the expected value input of the memory circuit and the instruction code to the central processing unit are time-divided, and the same input terminal is cycled with a cycle shorter than a predetermined cycle. By alternately inputting and latching at each predetermined cycle, it is possible to simultaneously perform the functional tests of the memory circuit and the central processing unit. Therefore, the time required for this functional test can be significantly reduced. In addition, the number of input terminals does not increase by also using the terminals for inputting the expected value and the instruction code.

Further, in the functional test of the memory circuit, the second comparison circuit for comparing the output value from the memory circuit with the expected value is provided inside, so that only the judgment result is output to the outside. Output terminals can also be significantly reduced.

Therefore, by using the semiconductor integrated circuit of the present invention, it is possible to quickly perform a functional test of the central processing unit and the memory circuit incorporated therein and to reduce the manufacturing cost of the semiconductor integrated circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing an electrical configuration of a semiconductor integrated circuit 31 and a test apparatus 2 for performing a functional test thereof according to an embodiment of the present invention.

FIG. 2 is a time chart in a functional test of the semiconductor integrated circuit 31 shown in FIG.

3 is a circuit diagram of an input circuit including a test-purpose terminal 37 shown in FIG.

FIG. 4 is an electric circuit diagram of a comparison circuit 45 shown in FIG.

FIG. 5 is a block diagram showing an electrical configuration of a conventional semiconductor integrated circuit 1 and a test apparatus 2 for performing a functional test thereof.

6 is a circuit diagram showing an external instruction input terminal 7 and a ROM output terminal 16 shown in FIG.

FIG. 7 is a circuit diagram of an input circuit including conventional test terminals T1 to Tn.

8 is a time chart in the functional test of the conventional semiconductor integrated circuit including the test terminal of FIG.

[Explanation of symbols]

 31 semiconductor integrated circuit 32 test device 33 CPU 34 ROM 35 counter 36 test input circuit 37 test shared terminal 38 oscillator circuit 39 data bus 40 address bus 42 RAM 41, 45 comparison circuit

Claims (1)

[Claims] 1. A central arithmetic processing circuit for executing an operation at a predetermined cycle based on an instruction code given from the outside, a memory circuit for reading data at the predetermined cycle, and a central circuit at the time of a functional test. A first comparison circuit that compares the operation processing result output from the operation processing circuit with prestored data to determine suitability; and data read from the storage circuit during a functional test.
A second comparison circuit for comparing the expected value data given from an external test device to determine suitability, and an instruction code and an expected value alternately given from the external test device in a cycle shorter than the predetermined cycle. A semiconductor integrated circuit, comprising: an input circuit that holds data and data for the predetermined period and supplies the data to the central processing unit and the storage circuit.