JPH06268506A - External output buffer - Google Patents

Abstract

(57) [Summary] [Objective] To obtain a low power consumption external output buffer that selects a signal in a low noise output mode or a high speed output mode and outputs it to the outside of the circuit. [Structure] A C-MOS circuit consisting of transistors 3 and 6 is used for the output stage, and signals are sent to the transistors 1 and 2.
Control with 4 and 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an external output buffer that outputs a binary signal to the outside of the circuit.

[0002]

2. Description of the Related Art FIG. 4 is a circuit diagram showing a conventional external output buffer. In the figure, reference numeral 41 is a terminal to which a binary signal to be output generated by a circuit (not shown) is input. Terminal 41
The enable signal for controlling whether or not the signal input to the external output is externally input is input to the terminal 42. Signals at terminals 41 and 42 are NAND
The signal input to the gate 43 and output from the NAND gate 43 is input to the parallel circuit of the resistor 45 and the switch 44 for selecting the low noise output mode or the high speed output mode, and the output of the parallel circuit is the P-channel transistor 46. Is input to the gate. The drain of the transistor 46 is the circuit power supply voltage V _CC.
The source of the transistor 46 is connected to the power supply voltage V _{SS of the} circuit through the current limiting resistor 47. The connection point between this source and the current limiting resistor 27 is used as the external output terminal 12.

Next, the operation of the circuit diagram of FIG. 4 will be described. Terminal
When the enable signal input to 42 is 0 ", the signal output from the NAND gate 43 is 1" regardless of whether the signal input to the terminal 41 is 0 "or 1".
1 ". Therefore, the gate of transistor 46 is 1"
Therefore, the gate of transistor 46 becomes 1 ”,
The transistor 46 is turned off. As a result, the signal at the terminal 41 is not output to the external output terminal 48.

If the enable signal input to the terminal 42 is "1", the signal input to the terminal 41 is "0".
(Or ■ 1 "), the output of NAND gate 43 is
It becomes 1 "(or ■ 0"). Therefore, the gate of the transistor 46 becomes (1) (or (0)) so that the transistor 46 is turned off (or turned on). As a result, the external output terminal
48 is the same as the signal input to terminal 48 ■ 0 "(or ■
1 "), the signal input to the terminal 41 ■ 0"
(Or (1) ") is sent to the external output terminal 48.

Next, the low noise output mode and the high speed output mode will be described. Figures 5 and 6 are rising waveform diagrams in low-noise output mode and high-speed output mode, respectively, with the horizontal axis representing time (seconds).
The vertical axis represents the voltage at the external output terminal 48. When the switch 44 is off, the signal {circle over (1)} output from the NAND gate 43 passes through the resistor 45 as a signal delay means and is input to the gate of the transistor 46, so that the transistor 46 is turned on. Therefore, as shown in FIG. The signal output from the NAND gate 43 at this time shows a gentle rising waveform.
(2) The noise signal superimposed on 0 "is divided by the resistors 45 and 47 and output to the external output terminal 48, so that the noise signal is reduced. This is the operation in the low noise output mode.

On the other hand, when the switch 45 is on, the NA
The signal {circle around (1)} output from the ND gate 43 does not pass through the resistor 45 but passes through the switch 44 and is input to the gate of the transistor 46, so that the transistor 46 is turned on, and thus the rising waveform having a steep slope as shown in FIG. Is obtained.

[0007]

The conventional external output buffer has a current limiting resistor 47 when the transistor 46 is turned on.
There is a problem in that a current flows through the device, resulting in power consumption by the current limiting resistor 47. Furthermore, conventional external output buffers have a limited voltage at which transistor 46 can operate. Therefore, in order to drive a device such as a liquid crystal display control circuit or a printer drive control circuit that cannot be operated by the same power supply voltage, it is necessary to prepare a plurality of external output buffers that operate with the same power supply as those devices. , There is a problem.

The present invention has been made in view of the above problems, and an object of the present invention is to provide an external output buffer that reduces power consumption due to the need for a current limiting resistor by providing a C-MOS circuit in the output stage. To do. Furthermore, by providing the C-MOS circuit with a circuit that selects and supplies the required power supply from multiple power supplies, it is possible to drive multiple devices that operate in response to multiple power supplies using multiple power supply voltages. The purpose is to provide an output buffer.

[0009]

An external output buffer according to a first invention is a C-MOS for outputting a signal to be output to the outside.
A circuit and a switch for controlling whether or not to send the signal to be output to the C-MOS circuit. In the external output buffer according to the second aspect of the present invention, a C-MOS circuit is connected in parallel with a transistor of one conductivity type and has different signal drive rates.
It is composed of transistors of other conductivity type. The external output buffer according to the third aspect of the present invention is configured such that C-MOS circuits are connected in parallel, and each of the plurality of one conductivity type transistors and other conductivity type transistors having different signal driving rates. In the fourth invention, a required power source is selected from a plurality of power sources and applied to the C-MOS circuits of the second and third inventions.

[0010]

In the first invention, the signal to be output is C-MO.
Since it is output to the outside using the S circuit, the power consumption due to the current limiting resistance in the output stage can be reduced. In the second and third inventions, the high-speed output mode or the low-noise output mode is set according to the signal driving rate of the transistor that is turned on. Fourth
In the invention, the selected voltage can be applied to the circuit side receiving the output signal.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to the drawings showing the embodiments. FIG. 1 is a circuit diagram showing an embodiment of an external output buffer of the present invention. In the figure, reference numeral 17 is a terminal for inputting a binary signal to be output generated by a circuit (not shown), which is connected to each source of N-channel transistors 1 and 4. 11,12 are signals ■ 0 ", ■ 1"
Is connected to each source of the P-channel transistors 2 and 5. The terminal 18 is connected to the gates of the transistors 1, 2, 4 and 5, and each transistor 1, 2 is controlled by an enable signal that controls whether or not the binary signal to be output, which is input from the terminal 18, is transmitted.
Turn 2, 4, 5 on or off. Transistors 1 and 2
Each drain of (or 4, 5) is connected to one end of the parallel circuit of resistor 7 and switch 9 (or resistor 8 and switch 10),
The other end of the parallel circuit is connected to the gate of the N-channel transistor 3 (or the P-channel transistor 6). The transistors 3 and 6 form a C-MOS circuit, and the drains of the transistors 3 and 6 are both connected to the external output terminal 13. Power supply voltages V _CC and V _SS are applied to the sources of the transistors 3 and 6, respectively.

Next, the operation of the circuit shown in FIG. 1 will be described. When the enable signal input from the terminal 18 is 1 ″, the transistors 1 and 4 are turned on and the transistors 2 and 5 are turned off.
Value signal is from 0 "to 1" (or from 1 "to 0")
When it changes to, the transistor 3 changes from off to on (or on to off), and the transistor 6 changes from on to off (or off to on). Therefore, the binary signal to be output to the external output terminal 12 is from 0 "to 1"
(Or rising (or falling) from 1 "to 0")
The waveform is shown. In this case, the interlocked switches 9 and 10
When is on, it corresponds to the high-speed output mode,
A rising (or falling) waveform having a steep edge is output from the external output terminal 12, and when the switches 9 and 10 are off, the presence of the resistor 7 (or 8) corresponds to the low noise output mode. A rising (or falling) waveform having a gradual edge is output from the output terminal 12.

When the enable signal at the terminal 18 is (1) 0 ", the transistors 1 and 4 are both off and the transistors 2 and 5 are both on, so that the gates of the transistors 3 and 6 are (0)", As a result, the transistors 3 and 6 are both turned off. Therefore, the external output terminal 12 shows a high impedance state.

As described above, since the binary signal to be output which is input to the terminal 17 is output to the outside of the circuit by the C-MOS circuit composed of the transistors 3 and 6, the current limiting resistor is not necessary. Therefore, there is no power consumption due to the current limiting resistance. The transistors 1, 2, 4, 5 are replaced by P
A C-MOS transmission gate having a pair of a channel transistor and an N-channel transistor may be used.

FIG. 2 is a circuit diagram showing another embodiment of the external output buffer of the present invention. Terminal 114 is connected to each source of N-channel transistors 101, 104 and 107
The binary signal to be output, which is generated by the circuit without the OS, is input. The terminal 115 is connected to the source of the P-channel transistor 102 and supplies the signal "0" to the source. The terminal 113 is connected to the gates of the transistors 101 and 102, and supplies an enable signal (which can be output by "1") for controlling whether or not the output target signal can be transmitted to the gates.

Terminal 117 is a P-channel transistor 105,
It is connected to each source of 108 and gives a signal "1" to each source. Terminal 116 (or 118) is a transistor
It is connected to each gate of 104, 105 (or 107, 108) and provides the same enable signal as described above to each gate. The drains of the transistors 101 and 102 are both connected to the resistor 120 and one end of the parallel circuit of the switch 121.
The other end of the parallel circuit is connected to the gate of an N-channel transistor 103. Transistors 104, 105 (or 107,
Each drain of (108) is a P-channel transistor 106.
(Or 109) connected to the gate of transistor 103,106
(Or 109) constitutes a C-MOS circuit. Transistor 1
The signal drive ratio of 09 is lower than that of the transistor 106.

The power supply voltage V _SS (or V _SL ) is supplied to the source of the transistor 106 (or 109). P-channel transistor 110 and N-channel transistor 11
The power supply voltages V _CC and V _SH are supplied to the respective sources of 1. Terminal 112 is connected to the gates of the transistors 110 and 111, the control signal "1" to give a V _CC (or V _SH) to the source of the transistor 103 when the switch 121 in this embodiment is on (or off) (or " 0 ") should be entered. The drains of the transistors 110 and 111 are both connected to the source of the transistor 103 and another device (not shown), and V _CC or V _SH is supplied to the C-MOS circuit and other devices. Transistors 103, 106 and 109
The drains of both are connected to the external output terminal 122.

Next, the operation of the circuit shown in FIG. 2 will be described.
Since the signal driving rates of the transistors 106 and 109 are different and the transistor 106 is higher, the signal output due to the conduction thereof has a waveform in a high-speed output mode in which the rising and falling are steep. On the contrary, the signal output due to the conduction of the transistor 109 has a gradual rise and fall, and thus has a waveform in the low noise output mode in which noise is suppressed. Therefore, the enable signals at the terminals 116 and 118 are set to "1" corresponding to the high speed output mode and the low noise output mode, respectively.

On the other hand, the on / off of the switch 121 corresponds to the high speed output mode and the low noise output mode, respectively. In this embodiment, the on / off of the switch 121 and the "1" / "0" of the signal applied to the terminal 112 are determined. Work together. Therefore, in the high speed output mode, "1" / "0" of the output signal becomes _Vcc / _Vss , and in the low noise output mode, "1" / "0" of the output signal becomes _Vsh / Vs.
Become _SL .

The details will be described below. When the switch 121 is turned on, the enable signals of the terminals 113 and 116 are set to “1”, and the enable signal of the terminal 118 is set to “0” (high-speed output mode), the transistors 101, 104 and 10 are connected.
8 turns on and transistors 102, 105 and 107 turn off. In this state, the output target of terminal 114 is 2
When the value signal changes from "0" to "1" (or "1" to "0"), the transistor 103 is off to on (or on to off) and the transistor 106 is on to off (or off to on). Becomes Transistor 109 remains off.

Therefore, the binary signal output to the external output terminal 122 exhibits a rising (or falling) waveform having a sharp edge of "0" to "1" (or "1" to "0").
In this case, since the control signal at the terminal 112 becomes "1", the transistor 111 is turned on and the transistor 110 is turned off. As a result, the power supply voltage V _CC is supplied to the source of the transistor 103. Therefore, the external output buffer supplies the power supply voltage V _CC to other devices connected thereto, and further the external output terminal 12
2 indicates the signal "1" of the voltage V _CC . "0" is V _SS due to the turning on of the transistor 106.

Next, the switch 112 is turned off and the terminals 113 and 11 are
When each enable signal of 8 is set to “1” and the enable signal of the terminal 116 is set to “0” (low noise output mode), the transistors 101, 105 and 107 are turned on,
Further, the transistors 102, 104 and 108 are turned off. In this state, the binary signal to be output is from "0" to "1"
When it changes (or changes from "1" to "0"), the transistor 103 changes from off to on (or on to off) and the transistor 109 changes from on to off (or off to on).
Transistor 106 remains off.

Therefore, the binary signal output to the external output terminal 122 exhibits a rising (or falling) waveform having a gradual edge from "0" to "1" (or "1" to "0"). In this case, when the switch 121 is on, this corresponds to the high-speed output mode, and the rising waveform having a steep edge is output from the external output terminal 122. In this case, since the control signal at the terminal 112 is "0", the transistor 110 is turned on,
The transistor 111 is turned off, and V _SH is applied to the source of the transistor 103. Therefore, the power supply voltage or the voltage of "1" supplied to other devices becomes V _SH . When the transistor 109 is turned on, the voltage "0" becomes V _SL .

When the enable signals at the output terminals 113, 116 and 118 are all "0", the transistors 101, 104 and 107 are connected.
Are turned off and the transistors 102, 105 and 108 are turned on, so that the gates of the transistors 103, 106 and 109 are "0", "1" and "1", respectively, so that the transistors 103, 106 and 109 are turned off. Therefore, the external output terminal 122 shows a high impedance state.

As described above, the external output buffer of this embodiment can reduce the power consumption due to the current limiting resistance of the output stage by providing the C-MOS circuit in the output stage.
Further, by providing the power source selection circuit including the transistors 110 and 111 as in the above-described embodiment, the binary signal to be output can be output to the outside of the circuit as a binary signal corresponding to a plurality of different power source voltages. In the above-described embodiment, the power supply voltages V _CC and V _SH are selected by interlocking with the on / off of the mode selection switch 121, but the mode selection and the voltage selection can be made independent. .

In the above embodiment, the required power source is selected from the two types of power source voltages, but the required power source may be selected from three or more types of power source voltages. The number of parallel transistors in the C-MOS circuit may be three or more. Furthermore, the transistors on the input side such as the transistors 110 and 111 can be replaced with C-MOS transmission gates.

FIG. 3 is a circuit diagram showing still another embodiment of the external output buffer of the present invention. In this embodiment, two transistors are selectively connected in parallel so that the N-channel side of the C-MOS circuit is selectively turned on. The terminal 218 that gives a binary signal to be output is an N-channel transistor 20.
Connected to 1,204,104,107 sources. The drains of the transistors 201 and 204 are N-channel transistors 203 and 20.
Connected to 6 gates. The signal driving rate is high in the transistor 203 and low in the transistor 206. The terminal 219 to which the signal “0” is given is the P-channel transistor 202, 205.
Of the transistors 203 and 206, and the drains of these transistors are connected to the cables of transistors 203 and 206, respectively.

Terminal 21 to which each separate enable signal is applied
7 and 220 are connected to the gates of the transistors 201 and 202 and the gates of the transistors 204 and 205, respectively. The drains of the transistors 111 and 110 whose sources are connected to the voltages V _CC and V _SH , respectively, are collectively transistor 203,
Connected to 206 sources. Transistor 203,206
Of the P channel transistors 106 and 109 are connected together to the output terminal 122.

Since the other structure is similar to that of the embodiment shown in FIG. 2, the same reference numerals are given and the description thereof is omitted. In this embodiment, when the high-speed output mode is selected, the terminal 217,
The enable signal of 116 is set to "1", and the enable signals of the terminals 220 and 118 are set to "0". On the contrary, when the low noise output mode is selected, the enable signals at the terminals 220 and 118 are set to "1" and the enable signals at the terminals 217 and 116 are set to "0" in order to select the combination of the transistors 206 and 109 having a low signal driving rate. The voltage on the P-channel transistor side, that is, the voltage of the output signal "0" is V _{SS in the} high speed output mode and V _{SL in the} low noise output mode.

On the other hand, the voltage on the N-channel transistor side, that is, the voltage of the output signal "1" is set by setting the control signal at the terminal 112 to "1" or "0" independently of the selection of the transistors 203 and 206, that is, the mode selection. V _CC and V _SH can be arbitrarily selected. It goes without saying that a high impedance state can be obtained when all the enable signals of the terminals 217, 220, 116 and 118 are "0". In this example also
Of course, the number of transistors on the P-channel side and the number of N-channel sides of the C-MOS circuit may be three or more. Also, the transistors on the input side such as transistors 110 and 111
It can be replaced with a C-MOS transmission gate.

[0031]

As described above, the external output buffer of the present invention can reduce the power consumption due to the current limiting resistance by providing the C-MOS circuit in the output stage, and further by providing the power supply selecting circuit. Since the C-MOS circuit outputs signals corresponding to a plurality of different power supply voltages to the outside of the circuit, it is possible to drive a plurality of devices that operate corresponding to a plurality of power supply voltages.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an external output buffer of the present invention.

FIG. 2 is a circuit diagram showing another embodiment of the external output buffer of the present invention.

FIG. 3 is a circuit diagram showing still another embodiment of the external output buffer of the present invention.

FIG. 4 is a circuit diagram showing a conventional external output buffer.

FIG. 5 is a rising waveform diagram of a low noise output mode.

FIG. 6 is a rising waveform diagram of a high speed output mode.

[Explanation of symbols]

 1-6 Transistors 101-111 Transistors 201-206 Transistors

Claims (4)

[Claims] 1. A low noise output mode in which a level of a noise signal superimposed on the signal to be output is reduced and output to the outside of the circuit, and a signal having a steeper edge than the signal in the low noise output mode. In an external output buffer having a high-speed output mode that outputs to the outside of the circuit, a C-MOS circuit that outputs the signal to be output to the outside, and whether or not to send the signal to be output to the C-MOS circuit are controlled. An external output buffer, comprising: 2. A low noise output mode in which the level of a noise signal superimposed on the signal to be output is reduced and output to the outside of the circuit, and a signal having a steeper edge than the signal in the low noise output mode. In an external output buffer having a high-speed output mode for outputting to the outside of the circuit, it is composed of one conductivity type transistor and a plurality of other conductivity type transistors which are connected in parallel and have different signal drive rates. An external output buffer comprising: a C-MOS circuit for outputting the signal to be output to the outside by means of a switch; and a switch for controlling whether or not to send the signal to be output to the C-MOS circuit. . 3. A low noise output mode in which the level of a noise signal superimposed on the signal to be output is reduced and output to the outside of the circuit, and a signal having a steeper edge than the signal in the low noise output mode is provided. In an external output buffer having a high-speed output mode for outputting to the outside of the circuit, each of which is connected in parallel and is composed of a plurality of transistors of one conductivity type and transistors of another conductivity type having different signal drive rates. An external output buffer comprising a C-MOS circuit that outputs the signal to be output to the outside by selective conduction of the signal. 4. The external output buffer according to claim 2, further comprising a power supply selection circuit that selects a required power supply from a plurality of power supplies and supplies the selected power supply to the C-MOS circuit.