JPH06276384A - Line density conversion circuit - Google Patents

Abstract

PURPOSE:To convert a line density of input picture data into a line density of a predetermined multiple and to provide an output without increasing a storage capacity of a memory. CONSTITUTION:The conversion circuit is provided with a shift register 14 to store picture element data DX tentatively by one line and picture element data DX are inputted from a discrimination processing circuit 13 to the input side. The output side and the input side of the shift register 14 are interconnected via a data signal line 15. When the picture element data DX are outputted from the shift register 14 to the printer, the output picture element data DX are inputted to the shift register 14 again via the data signal line 15. Thus, even when the output of the picture element data DX by one line in the shift register 14 is finished, the same picture element data DX as the picture element data DX by one line outputted are stored in the shift register 14. Thus, the same picture element data DX are outputted again from the shift register 14.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a linear density conversion circuit which is applied to, for example, a facsimile machine and which converts a linear density of input image data into a linear density of a predetermined multiple and outputs the linear density.

[0002]

2. Description of the Related Art Generally, in a facsimile machine, a normal mode, a fine mode,
There are also three reading modes including a super fine mode. In the normal mode, the read line density in the sub-scanning direction is 3.85 lines / m.
m, twice in fine mode, 7.7 lines / mm, and 2 in super fine mode
Each reading is performed at double the line density of 15.4 lines / mm.

On the other hand, in a facsimile machine, when the received image data is recorded on a recording paper, there is one capable of recording at a linear density of 15.4 lines / mm corresponding to the linear density of the super fine mode. is there. And
In the conventional apparatus, for example, when the line density of the received image data is 3.85 lines / mm corresponding to the normal mode, each line data of the received image data is continuously made four times for each line data, It is stored in memory. That is, the received image data has a linear density of 4
Doubled, that is, converted to a linear density of 15.4 lines / mm, and stored in the memory. Then, while reading the image data in the memory, the image data is recorded on the recording paper at a linear density of 15.4 lines / mm.

[0004]

Therefore, in the conventional device, even if the received image data has a low linear density of 3.85 lines / mm, the memory has four times as much data as the received image data. Will be remembered. Therefore, there is a problem that the storage capacity of the memory increases and the manufacturing cost increases.

The present invention has been made to solve the above problems, and an object thereof is to convert the linear density of input image data into a predetermined linear density without increasing the memory storage capacity. Another object is to provide a linear density conversion circuit that can output the output.

[0006]

In order to achieve the above object, the present invention is a circuit for converting a linear density of input image data into a predetermined linear density and outputting the linear density. Holding means for temporarily storing and holding image data for a line is provided, and the data output side of the holding means is connected to the data input side, and when the image data is output from the holding means, the output image data is held. It is configured to input again.

[0007]

Therefore, according to the present invention, when image data for one line (line data) is input to the holding means, the input line data is temporarily stored and held in the holding means. Then, when line data is output from the output side of the holding means and the output line data is input to, for example, a printer, the printer performs recording based on the input line data. Further, when the line data is output from the holding means, the output line data is input again to the holding means. Therefore, even if the output of the line data in the holding means is completed, the same line data as the output line data is stored and held in the holding means. Therefore, the same line data can be output again from the holding means.

That is, the input line data is
Since it is possible to continuously output one line data a plurality of times, it is possible to convert (enlarge) the linear density of the input image data into a predetermined linear density and output the linear density. Therefore,
For example, when the image data stored in the memory is output to the printer for recording, the image data output from the memory is output to the printer while the linear density is converted by the holding means. Does not need to be stored in a state in which the image data is converted into a linear density of a predetermined multiple.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the linear density conversion circuit of the present invention is embodied in a facsimile machine will be described below with reference to the drawings.

FIG. 7 shows the circuit configuration of the facsimile apparatus of this embodiment. A CPU (Central Processing Unit) 1 has a ROM (Read Only Memory) 2 storing a program for controlling the operation of the entire apparatus including a program for linear density conversion, and a RAM for temporarily storing various information. A (random access memory) 3 is connected via a bus 4. NCU (Network Control Unit) 5
Has a function of controlling connection with a telephone line, sending dial pulses corresponding to the fax number of the other party, and detecting an incoming call. The modem 6 modulates and demodulates transmitted / received data, and at the same time, digital command signal (D
CS) and a digital identification signal (DIS).

The reading unit 7 is for reading an image on a document. The page memory 8 stores the received image data for one page for each line data Ld. In the present embodiment, the pixel data D forming one line data Ld
The dot number n of 1 to Dn is 2048. The enlargement / smoothing circuit 9 enlarges / smooths the image data transferred from the page memory 8 via the interface 21 (details will be described later) and outputs the image data to the printer 10. The interface 21 controls the transfer timing of image data from the page memory 8 to the enlargement / smoothing circuit 9.

The printer 10 is composed of, for example, a recording device of an electrophotographic recording system, and records image data on recording paper based on the image data input from the enlarging / smoothing circuit 9. The printer 10 of this embodiment is adapted to perform recording at a superfine mode linear density, that is, a linear density of 15.4 lines / mm.

When a call signal is transmitted from the exchange on the basis of a call from the calling side and the calling signal is detected by the NCU 5, the CPU 1 controls the NCU 5 to establish a line between the calling side and the calling side. Close it and make the device ready for reception. Then, after a predetermined facsimile signal such as a CNG signal is exchanged with the transmitting side, the CPU 1 controls the modem 6 to transmit the DIS signal, and the receiving side, that is, all the functions of the own side are transmitted to the transmitting side. Let us know. Also, the transmitting side transmits a DCS signal corresponding to the DIS signal,
A function selected from all functions of the receiving side is designated.

That is, in the facsimile apparatus of the present embodiment, the printer 10 records at a linear density of 15.4 lines / mm, and therefore the DIS signal causes 15.4 lines / mm.
Notify the transmitting side that it is possible to receive image data read with a linear density of mm. Then, for example, when the original reading mode on the transmitting side is the normal mode, the transmitting side reads D
The CS signal informs the receiving side that the read line density is the standard line density of 3.85 lines / mm.

After that, when the read image data from the transmitting side is received, the CPU 1 temporarily stores the image data in the RAM 3, and at least one page of the stored image data is stored in the page memory 8 for each line data Ld. Transfer and memorize. In this embodiment, the linear density of the received image data is 3.85 lines / mm, 7.7 lines / mm, 15.4.
In any case of line / mm, the CPU 1 causes the page memory 8 to store each line data Ld once for each line data Ld. After that, CPU1
The image data in the page memory 8 is sequentially transferred to the enlargement / smoothing circuit 9 for each line data Ld via the interface 21.

Here, the structure of the enlargement / smoothing circuit 9 will be described in detail. As shown in FIGS. 1 to 6, the first and second shift registers 11a and 11b have line data Ld.
Is temporarily stored for each 2045 pixels. The first to ninth pixel memories 12a to 12i are for temporarily storing each pixel data D constituting the line data Ld for each pixel, and the nine pixel memories 12a to 12i are used to store three pixels. A matrix M of × 3 is formed.

The first to third pixel memories 12a to 12c are connected in series with each other, and the input side of the first pixel memory 12a is connected to the interface 21. Also, the third
The output side of the pixel memory 12c is connected to the input side of the first shift register 11a. The fourth to sixth pixel memories 12d to 12f are connected in series with each other, the input side of the fourth pixel memory 12d is connected to the output side of the first shift register 11a, and the output side of the sixth pixel memory 12f is second shifted. It is connected to the input side of the register 11b. The seventh to ninth pixel memories 12g to 12i are connected in series with each other, and the input side of the seventh pixel memory 12g is connected to the output side of the second shift register 11b.

When the line data Ld is sequentially transferred from the page memory 8, the line data Ld is transferred to the first to third pixel memories 12a to 12c, the first shift register 11a, and the fourth to sixth pixel memories 12d. ~ 12f, second
Shift register 11b and seventh to ninth pixel memories 12
are sequentially input to g to 12i. And page memory 8
The pixel data D of each line data Ld fetched onto the matrix M shifts by one pixel in the main scanning direction as the transfer of the line data Ld from the.

The judgment processing circuit 13 is for smoothing the input image data. That is, when the pixel data D forming the line data Ld is stored in each of the pixel memories 12a to 12i forming the 3 × 3 matrix M, the pixel data D is output in parallel to the determination processing circuit 13. It At this time, the pixel data D stored in the pixel memory 12e located at the center of the matrix M becomes the target pixel data X. Then, this pixel data of interest X
Based on the black and white pattern of the eight pixel data D stored in the pixel memories 12a to 12d and 12f to 12i around, the determination processing circuit 13 determines one of the black and white data that the target pixel data X should take. To do.

For example, the ROM is used as data to be referred when determining the data to be taken by the pixel data X of interest.
2, table data (not shown) is stored in advance. In this table data, each black and white pattern of the eight pixel data D existing around the target pixel data X at the center of the matrix M is set as an address.
Then, corresponding to the address, one of black and white pixel data to be taken by the target pixel data X is set.

Therefore, when the pixel data D extracted on the matrix M is input to the determination processing circuit 13, the determination processing circuit 13 selects an address corresponding to the black and white pattern of the input pixel data D. At the same time, one of black and white data corresponding to the address is output to the A terminal of the data selector 16 described later as pixel data DX.

The shift register 14 as holding means is
The pixel data DX is for temporarily storing one line, that is, 2048 pixels, and the pixel data DX from the determination processing circuit 13 is input to the input side thereof.
Further, the data selector 1 is provided on the output side of the shift register 14.
The B terminal of 6 is connected. Then, the determination processing circuit 1
The pixel data DX1 to DXn corresponding to one line is stored in the shift register 14 as the pixel data DX as the determination result is sequentially output from 3.

The output side and the input side of the shift register 14 are connected via a data signal line 15. Then, as described above, when the pixel data DX1 to DXn for one line is stored in the shift register 14, the CPU 1
The transfer of the line data Ld from the page memory 8 is temporarily stopped. At this time, the output of the pixel data DX from the determination processing circuit 13 is also temporarily stopped.

Then, in this state, the CPU 1 outputs the pixel data DX1 to DXn in the shift register 14 to the B terminal of the data selector 16. At this time, the pixel data DX1 to DXn are transferred from the shift register 14 to the data selector 16.
Is output, the same pixel data DX1 to DXn are input again to the shift register 14 via the data signal line 15.

Therefore, even if the output of the pixel data DX1 to DXn for one line in the shift register 14 is completed, the same pixel data as the pixel data DX1 to DXn for one line output in the shift register 14 is completed. DX1 to DXn are stored and held. In addition, 1 in the shift register 14
With the pixel data DX1 to DXn for the lines stored,
When new pixel data DX is input from the determination processing circuit 13, the pixel data DX in the shift register 14 is output to the data selector 16, and the new pixel data DX is stored in the shift register 14. To be done.

For example, the linear density of received image data is 3.85.
In the case of line / mm, the CPU 1 temporarily stops the transfer of the line data Ld from the page memory 8 in order to quadruple the linear density of the received image data, and the same 1 from the shift register 14 Line pixel data DX1 ~
Output DXn three times. That is, the determination processing circuit 13
Since the pixel data DX1 to DXn have already been output to the data selector 16 once when the pixel data DX1 to DXn are output from the shift register 14, the shift register 14 may output the same three times.

When the line density of the received image data is 7.7 lines / mm, the CPU 1 transfers the line data Ld from the page memory 8 in order to double the line density of the received image data. , The pixel data DX1 to DXn for the same one line is output from the shift register 14 once. That is, as in the case described above, when the pixel data DX1 to DXn are output from the determination processing circuit 13, the pixel data DX1 to DXn have already been output to the data selector 16 once.
Since it is output to the shift register 14, the shift register 14 may output it once.

The data selector 16 has an A terminal and a B terminal.
Either one of the two types of data input from the terminal is selected, and the selected one data is output from the Q terminal to the printer 10. The pixel data DX from the determination processing circuit 13 is input to the A terminal. Also, the pixel data DX from the shift register 14 is connected to the B terminal.
Is entered.

A select signal is input from the CPU 1 to the S terminal of the data selector 16, and the data selector 16 selects one of the data input from the A terminal and the B terminal based on the select signal. Is output. For example, the line data Ld from the page memory 8
Is being performed and the pixel data DX is being output from the determination processing circuit 13, the CPU 1 causes the select signal to select the input from the A terminal. Therefore, the pixel data DX output from the determination processing circuit 13 is input to the printer 10 via the data selector 16.

Further, the pixel data DX output from the determination processing circuit 13 is input to the shift register 14 and the pixel data DX1 to DXn for one line is stored in the shift register 14.
When is stored, the CPU 1 temporarily stops the transfer of the line data Ld from the page memory 8. At this time, C
PU1 selects the input from the B terminal by the select signal. Therefore, the pixel data DX1 to DXn for one line in the shift register 14 is output to the printer 10 via the data selector 16.

Note that, for example, the first input line data Ld and the pixel data D at both ends of each line data Ld are
Since it cannot be the pixel data X of interest in the matrix M,
It seems that the data is not output to the printer 10 side. However, in reality, the data that cannot be the target pixel data X are output to the printer 10 side as they are, so that no data loss occurs during recording.

Next, the operation of the facsimile apparatus configured as described above will be described. Now, for example, when the original is read at a line density of 3.85 lines / mm on the transmitting side and the read image data is transmitted, the image data is temporarily stored in the RAM 3. Then, one page of the stored image data is transferred and stored in the page memory 8 for each line data Ld. At this time, the line data Ld of the image data is stored in the page memory 8 once for each line data Ld. After that, the image data in the page memory 8 is sequentially transferred to the enlarging / smoothing circuit 9 via the interface 21 one line data Ld at a time. The transfer timing of the line data Ld is controlled by the interface 21.

Then, from the page memory 8 to the enlargement / smoothing circuit 9, the first line data Ld (first line data L
When d1) is transferred, as shown in FIG. 1, the first three pieces of pixel data D1 to D3 of the same line data Ld1 are first stored in the first to third pixel memories 12a to 12c, respectively. Then, the line data Ld1 is input to the first shift register 11a via the first to third pixel memories 12a to 12c.

When the next line data Ld (second line data Ld2) is transferred, as shown in FIG. 2, the first three pixel data D1 of the same line data Ld2 are transferred.
-D3 are first to third pixel memories 12a to 12a, respectively.
It is stored in 12c. Accordingly, the first three pieces of pixel data D1 to D3 of the first line data Ld1 are stored in the fourth to sixth pixel memories 12d to 12f, respectively, and the remaining 2045 pixels of D4 to Dn are It is stored in the first shift register 11a.

When the transfer of the second line data Ld2 progresses and the transfer of the third line data Ld3 proceeds, as shown in FIG. 3, the first 3 of the same line data Ld3 are transferred.
The pixel data D1 to D3 are first to the first to the third, respectively.
It is stored in the pixel memories 12a to 12c. Then, in this state, the first three pixel data D1 to D3 of the second line data Ld2 are converted to the fourth to sixth pixel memories 12d to 1
Each of them is stored in 2f and the remaining D4 to D
2045 pixels up to n are transferred to the first shift register 11a.
It is stored in. Also, the first 3 of the first line data Ld1
One pixel data D1 to D3 is stored in the seventh to ninth pixel memories 1
The remaining 2045 pixels of D4 to Dn are stored in the second shift register 11b while being respectively stored in 2g to 12i.

In this way, each line data Ld1 is stored in each pixel memory 12a to 12i forming the matrix M.
When the pixel data D1 to D3 of .about.Ld3 are respectively stored, the pixel data D1 to D3 are output to the determination processing circuit 13 in parallel. Then, based on the black-and-white pattern of the eight pixel data D1 to D3 around the target pixel data X, the determination processing circuit 13 determines which of the black-and-white data the target pixel data X should take. It is output to the A terminal of the data selector 16 as DX.

At this time, the pixel data DX input to the data selector 16 is selected by the select signal from the CPU 1.
Are allowed to output to the printer 10. The pixel data DX output from the determination processing circuit 13 is also input to the shift register 14. Then, as shown in FIG.
When the pixel data DX is sequentially output from the determination processing circuit 13 as the transfer of the third line data Ld3 progresses, the pixel data DX1 to DXn for one line is stored in the shift register 14.
Is stored. Then, the first three pieces of pixel data D1 to D3 of the fourth line data Ld4 are stored in the first to third pixel memories 12a to 12c, respectively.
The transfer of the line data Ld4 is temporarily stopped. At the same time, the output of the pixel data DX1 to DXn for one line from the determination processing circuit 13 to the printer 10 is completed.

Then, in this way, the shift register 14
With the pixel data DX1 to DXn for one line stored therein, as shown in FIG.
The pixel data DX1 to DXn for the line is the data selector 16
Is output to. At this time, the pixel data D input to the data selector 16 by the select signal from the CPU 1
X1 to DXn are allowed to be output to the printer 10. still,
Pixel data DX1 from shift register 14 to printer 10
~ DXn is output, the same pixel data DX1 ~ D
Xn is input again to the shift register 14 via the data signal line 15.

At this time, since the linear density of the received image data is 3.85 lines / mm, in order to quadruple the linear density of the received image data, the same one line from the shift register 14 is used. The pixel data DX1 to DXn are output three times.

Then, the third pixel data DX1 to DX1
When the output of Xn is completed, the transfer of the fourth line data Ld4 is restarted. Then, as shown in FIG. 6, the pixel data Dx is output from the determination processing circuit 13 to the printer 10 and the shift register 14 in the same manner as described above. At this time, the previous pixel data DX1 in the shift register 14
To DXn are sequentially output to the data selector 16 side as new pixel data DX1 to DXn are input. However, at this time, since the data selector 16 has selected the input to the terminal A, the previous pixel data DX1 to DXn are the same as those of the printer 10.
It is invalidated without being output to.

As described above, every time the line data Ld of the received image data is input once, the judgment processing circuit 13 inputs the printer 10 once and the shift register 14 outputs the line data Ld three times to the printer 10. The pixel data DX1 to DXn for the lines are output. Then, based on the input of the pixel data DX from the shift register 14 and the determination processing circuit 13, the printer 10 records on the recording paper. At this time,
The recorded image has a linear density four times as high as that of the received image data, and is subjected to smoothing processing by the determination processing circuit 13.

That is, in this embodiment, the shift register 14
When the pixel data DX is output from the printer 10 to the printer 10, the output pixel data DX is input again to the shift register 14 via the data signal line 15. Therefore, the pixel data D for one line in the shift register 14
Even after the output of X1 to DXn is completed, the same pixel data DX1 to DXn as the output pixel data DX1 to DXn for one line is stored and held in the shift register 14. Therefore, the same pixel data DX can be output again from the shift register 14. For example, when the linear density of the received image data is 3.85 lines / mm, in order to quadruple the linear density of the received image data, the same one line of pixel data DX1 to DXn from the shift register 14 is used.
Can be continuously output a plurality of times.

Therefore, it is possible to easily convert the linear density of the received image data into a predetermined linear density and record the linear density. When the image data stored in the page memory 8 is output to the printer 10 for recording, the image data output from the page memory 8 is output to the printer 10 while converting the linear density by the shift register 14. can do. Therefore, it is possible to store the received image data in the page memory 8 in the same linear density as when it was received, and it is not necessary to store it in a state of being converted into a predetermined linear density.

Therefore, unlike the above-mentioned conventional technique, even if the linear density of the received image data is converted to a predetermined multiple and stored, the storage capacity of the page memory 8 may be sufficient to correspond to the linear density of the received image data. There is no fear that the storage capacity of the page memory 8 becomes large and the manufacturing cost rises.

The case where the received image data has a linear density of 7.7 lines / mm has not been described in detail, but in this case as well, the storage capacity of the page memory 8 is set in the same manner as described above. It does not have to be as large as the machine's line density of 15.4 lines / mm.

The present invention is not limited to the above-mentioned embodiment, but the present invention is embodied in an image forming apparatus or the like,
The determination processing circuit 13 for performing the smoothing processing may be excluded, and only the linear density conversion may be performed. Further, for example, the number of consecutively output four times per line data of the received image data is changed to a number other than four lines in the middle, and the configuration of each unit is within the scope not departing from the gist of the present invention. Can be appropriately changed and embodied.

[0047]

As described in detail above, according to the present invention, the linear density of input image data can be converted into a predetermined linear density and output without increasing the storage capacity of the memory. Exert the effect.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing an enlargement / smoothing circuit showing an embodiment in which a linear density conversion circuit of the present invention is embodied in a facsimile apparatus.

FIG. 2 is a circuit configuration diagram showing an enlargement / smoothing circuit.

FIG. 3 is a circuit configuration diagram showing an enlargement / smoothing circuit.

FIG. 4 is a circuit configuration diagram showing an enlargement / smoothing circuit.

FIG. 5 is a circuit configuration diagram showing an enlargement / smoothing circuit.

FIG. 6 is a circuit configuration diagram showing an enlargement / smoothing circuit.

FIG. 7 is a circuit configuration diagram of a facsimile device.

[Explanation of symbols]

1 ... CPU, 8 ... Page memory, 9 ... Enlargement / smoothing circuit, 14 ... Shift register as holding means, 15 ... Data signal line, Ld ... Line data, D ... Pixel data.

Claims (1)

[Claims] 1. A circuit for converting a linear density of input image data into a linear density of a predetermined number and outputting the linear density, and further comprising holding means for temporarily storing and holding the input image data for one line, A linear density conversion circuit configured to connect the data output side of the holding means to the data input side and input the output image data to the holding means again when the image data is output from the holding means.