JPH0628016A - Sequence control stopping circuit - Google Patents

Abstract

PURPOSE:To easily set up a stop condition code by reducing the bit width of a state value to be stopped in the case of stopping a sequence with a certain state value in a sequence control FF group in a data processor controlled by a hardware sequence control circuit. CONSTITUTION:This sequence control stopping circuit is provided with a coding circuit 40 for previously coding and outputting respective state values of the sequence control FF group 1 to (n). Each coded output is set up to the number of bits smaller than (n). A stopping condition storing part 41 has bit width equal to the number of bits of the coded output and previously stores a pattern code 46 to be stopped at its sequence. When a comparator 42 detects coincidence between the output of the circuit 40 and the output of the storing part 41, the clock of a clock supplying circuit 44 is stopped.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a sequence control stop circuit,
In particular, the present invention relates to a sequence control stop circuit for stopping the sequence control operation in accordance with the state value of a group of flip-flops (hereinafter simply referred to as FF) forming a sequence control circuit for sequence control.

[0002]

2. Description of the Related Art An example of a conventional sequence control stop circuit of this type is shown in FIG. In the figure, sequence control FFs 1 to n each consisting of a total of n bits are corresponding input signals 11 to 1 respectively.
n is fetched and set in synchronization with the clock. The n data registers 21 to 2n use the corresponding output signals of the sequence control FFs 1 to n as a set valid signal and the corresponding data 31 to 3n.
n is fetched and set in synchronization with the clock. The clock supply circuit 44 includes the FFs 1 to n and the data register 21.
Supply an operating clock of 2n.

When the sequence control is stopped, a state value code 46 having the same bit width n as the bit width of the sequence control FF and desired to be stopped is set in the stop condition storage unit 41 in advance. Then, the comparator 42 compares the state value code with the state value patterns of the sequence control FFs 1 to n, and when they match, one input of the AND gate 43 is set to logic "1".

At this time, to the other input of the AND gate 43, a signal which is preset to logic "1" is applied as the stop condition enable signal 45. Therefore, the comparator 42
In response to the supply of the logic "1" which is the coincidence output from the AND gate 43, the AND gate 43 generates a clock inhibition signal to the clock supply circuit 44 to stop the supply of the clock, thereby controlling the sequence of the data processing device. The operation can be stopped. After this stop, the hardware is diagnosed and analyzed.

For example, the state value of the sequence control FFs 1 to 20 of n = 20 bits is (00000000 1001).
(0001 0110), when the sequence is stopped, the state value code given to the stop condition storage unit 41 is also 20 bits and (0000
0000 1001 0001 0110).

In such a conventional sequence control stop circuit, since the state value code of the condition for stopping the sequence control needs to be the same as the state value pattern of the sequence control FF group, the number n of the FF group is n. The more
Setting the stop condition becomes complicated. In addition, when the number of state value patterns becomes extremely large, it is not necessary to actually stop in all state value patterns, and in many cases it is sufficient to stop only in a limited number of state value patterns, There is a drawback that there is a waste of setting the stop condition.

[0007]

SUMMARY OF THE INVENTION An object of the present invention is to provide a sequence control stop circuit in which a state value code of a stop condition of sequence control can be set with a state value code having a bit number as small as possible by eliminating waste and conforming to actual use conditions. Is to provide.

[0008]

A sequence control stop circuit according to the present invention receives a control sequence flip-flop group constituting a sequence control circuit for sequence control in a data processing device and all values of the flip-flop group as inputs. Coding means for generating and outputting a state value code indicating each state on the control sequence corresponding to each combination pattern of input values, and coded for stopping the data processing device in a certain state on the control sequence. Stop condition storing means for storing the stop condition in advance, and means for detecting the coincidence between the output of the stop condition storing means and the output of the encoding means to stop control the sequence control operation of the data processing device. It is characterized by

[0009]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a circuit block diagram of an embodiment of the present invention, and the same portions as those in FIG. 4 are designated by the same reference numerals. To describe only the parts different from the conventional example of FIG. 4, the coding circuit 40 receives the respective state values of the sequence control FF1 to FFn and inputs the respective state values on the control sequence corresponding to the respective combination patterns of these state values. A state value code indicating a value is generated and output. The bit width of this state value code is smaller than n, which is the bit width of FF1 to n, and n = 20.
In this case, the bit width of the code is set to 3, for example.

Therefore, the stop condition storage unit 41 can also set the 3-bit stop condition code 46 in advance, and this stop condition code and the output code of the encoding circuit 40 are compared by the comparison circuit 42. . When the two match, the clock supply operation of the clock supply circuit 44 is suppressed via the AND gate 43.

Since the other structure is the same as that of the circuit shown in FIG.
The description is omitted.

FIG. 2 is a circuit diagram showing a specific example of the encoding circuit 40 shown in FIG. 1, which is for generating a 3-bit code output with n = 20. FIG. 3 is an input / output logical value table of this coding circuit.

Under the actual sequence stop condition, F
Each of the F1 to F20 state values does not take "1", and it is often sufficient to stop the operation when only a limited number of state values take "1".

Therefore, in the present example, as shown in the logical value table of FIG. 3, only the six state values of FF1, 5, 9, 13, 15, and 17 take "1", and the other FFs show "1". It is assumed that all values can be fixed at "0" without taking "1".

For example, when the state values of the FFs 13 and 17 are "1" and all others are "0", the coded signal is "00".
When the state values of the FFs 13 and 15 are "1" and all others are "0", the coded signal becomes "010".

The logic circuit shown in FIG. 2 is obtained from the relationship of the truth table, and the NOR gate 51 outputs the outputs of the FFs 1, 5, 9, 13, 15, and 17 which may take the logic "1". To 57, respectively, and the outputs of the other FFs are combined by OR gates 58 to 60 and NOR gate 61. And all of these NOR gates 51-57, 6
Each output of 1 is combined by AND gates 62 to 68,
The outputs of the AND gates 62 to 68 are connected to the OR gate 6
These three OR gates 6 are combined by 9 to 71.
The outputs of 9 to 71 are 3-bit coded signals.

When the sequence control stop is performed when the state values of the FFs 13 and 17 are both "1" and the state values of the other FFs are all "0", the stop condition storage unit 41 is previously set.
Is set to 3-bit "001".

In this state, the FF 13
When the values of 1 and 17 are both "1" and the values of the other FFs are all "0", the coding circuit 40 generates and outputs the coded signal "001" of the stop condition.

Since the comparison circuit 42 detects the coincidence of both codes at this time, the coincidence output becomes "1", and the clock inhibition command is supplied to the clock supply circuit 44 through the AND gate 43. As a result, the sequence control operation is stopped, and the hardware circuit at this time is diagnosed and analyzed.

The coding circuit shown in FIG. 2 is a gate circuit of an encoder and is constructed by using one IC. Other than this example, a memory such as a ROM or a RAM may be used as the encoding circuit and each state value of the sequence control FF groups 1 to n may be given as an address input.

[0022]

As described above, according to the present invention, the code value for the stop condition is made to have a small number of bits by coding the state value of the sequence control FF group by a predetermined method. As a result, the code for the stop condition can be easily set, and the memory for the code setting can be small in capacity.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing an example of the encoding circuit of FIG.

FIG. 3 is a diagram showing an input / output relationship of the encoding circuit of FIG.

FIG. 4 is a diagram showing an example of a conventional sequence control stop circuit.

[Explanation of symbols]

 1-n sequence control FF group 21-2n data register group 40 coding circuit 41 stop condition storage unit 42 comparison circuit 43 AND gate 44 clock supply circuit

Claims (1)

[Claims] 1. A control sequence flip-flop group that constitutes a sequence control circuit for sequence control in a data processing device, and all values of the flip-flop group are input, and each combination pattern of these input values is input. Encoding means for generating and outputting a state value code indicating each state on the corresponding control sequence, and a stop condition for storing in advance a coded stop condition for stopping the data processing device in a certain state on the control sequence. A sequence control stop circuit comprising: storage means and means for detecting a match between the output of the stop condition storage means and the output of the encoding means to stop control the sequence control operation of the data processing device. .