JPH0628055A - Clock signal generating circuit - Google Patents

Abstract

PURPOSE:To input an external clock signal with low frequency and to form an internal clock signal with high frequency in an LSI based upon the external clock signal. CONSTITUTION:This clock signal generating circuit is provided with a flip flop (FF) 1 for forming a signal F synchronized with an external clock CKO, an oscillation circuit (oscillator) 2 for outputting an internal clock signal CKI whose oscillation start and stop are controlled by the signal F and a pulse counting circuit (counter) 3. The counter 3 counts up internal clock signals CKI, and when the count value reaches a set value, generates a reset signal N to the FF 1 to stop its oscillation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock signal generation circuit, and more particularly to a clock signal generation circuit for a computer.

[0002]

2. Description of the Related Art Due to recent advances in LSI technology, internal processing has become faster, and the frequency of clock signals for controlling sequential circuits of the entire LSI has increased to 50 MHz or higher.
However, when the clock frequency exceeds 30 MHz, it becomes difficult to design the board on which the LSI is mounted, and it is necessary to suppress the clock frequency outside the LSI.

In many cases, the clock signal input to the LSI is required to have the same high-level and low-level periods (duty ratio 50%). Therefore, a double frequency is generated by the oscillator on the board. It is general that the frequency is divided by 2 and used as a clock signal for the LSI. Therefore, there is a problem that an expensive oscillator must be used when the clock frequency becomes high.

A case of a micropro essor will be described as an example of the LSI. By incorporating a microprocessor and cache memory inside the LSI,
Data transfer with the outside of the LSI can be delayed. As a result, the clock frequency in the LSI is 50
25MHz outside the LSI even if operating at MHz
It is also possible to operate with.

In this case, a 100 MHz oscillator is used,
The frequency is divided by 2/4 on the board to generate clocks of 50 MHz and 25 MHz, respectively. The 50 MHz clock is supplied to the LSI, and the 25 MHz clock is supplied to other circuits on the board. But,
100 MHz oscillators are generally expensive. As LSI technology advances and higher frequencies are required, it is difficult to make an oscillator that stably oscillates.

Therefore, it becomes necessary to supply a 25 MHz clock to the LSI to generate a 50 MHz clock with a duty ratio of 50% inside the LSI. As a conventional solution to this problem, the following two methods have been used.

The first method is to use a phase locked loop.

In this method, a voltage-controlled oscillator (VCO) and a phase comparator are used to match the signal obtained by dividing the output of the VCO with the input clock. A frequency that is an integral multiple of the input clock can be oscillated by changing the division ratio. The disadvantage is that in order to obtain stable oscillation, it is necessary to narrow the oscillation frequency range of the VCO so that the maximum oscillation frequency is twice the minimum oscillation frequency.

The second method is a method of multiplying by using a differentiating circuit.

By differentiating the input clock by the differentiating circuit, a pulse having a constant width is obtained at the rising / falling edge to obtain a doubled frequency. The drawback is that unless the input clock has a duty ratio of 50%, a clean clock waveform cannot be obtained and the LSI may malfunction.

[0011]

The above-mentioned conventional clock signal generation circuit has a drawback that the range of clock frequencies that can be generated by the first method using the PLL is narrow.
In general, the power consumption of an LSI is almost proportional to the clock frequency, and therefore there is a problem that it cannot be used when the power consumption is to be reduced as much as possible due to the decrease in the clock frequency.

The second method using the differentiating circuit has a drawback that the duty ratio must be 50%. In this case, the clock is generated by oscillating a frequency twice the required clock frequency outside the LSI. Since it needs to be generated, there is a problem that it is not a solution for eliminating the need for a high frequency oscillator.

[0013]

A clock signal generating circuit of the present invention counts the second clock signal and an oscillation control circuit which generates an oscillation control signal synchronized with a first clock input from the outside. And a pulse counting circuit that outputs a stop control signal for controlling the oscillation control signal so as to stop the oscillation when the count value reaches a predetermined value.

[0014]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of a clock signal generating circuit of the present invention.

The clock signal generating circuit of this embodiment is shown in FIG.
, A reset set (RS) type flip-flop 1 with a reset priority set by an external clock CKO, and an oscillator that outputs and outputs an internal clock signal CK1 whose start and stop of oscillation are controlled by an output signal F of the flip-flop 1. 2 and a counter 3 that counts the falling edge of the internal clock signal CKI.

Next, the operation of this embodiment will be described.

FIG. 2 is a time chart of the circuit of this embodiment shown in FIG.

In FIG. 2, the external clock signal CKO is a periodic signal having a period T. The signal F from the flip-flop 1 is set at the rising edge of the external clock signal CKO and causes the oscillator 2 to start oscillating. The oscillator 2 oscillates at a cycle t while the signal F is at the high level, and the internal clock CKI
Is output. The counter 3 counts the falling edge of the internal clock CKI, outputs a high-level signal N after resetting the flip-flop 1, and counts twice. Here, the internal clock CKI is stopped when two pulses are output. External clock CKO again
Rises, the flip-flop 2 is set, the counter 3 is reset, and the above operation is repeated.

As described above, in the first embodiment, two pulses of the cycle t are output every cycle T.

Here, consider the case where the frequency of the input external clock CKO is changed.

FIG. 3A shows the case where the frequency of the external clock CKO is the highest. The period t of the oscillator 2 is set so that T at this time is T _min = 2 × t. Of course, the sequential circuit controlled by the internal clock CKI is designed so that the minimum cycle is t.

When the frequency of the external clock CKO is low, the internal clock CKI is alternately generated to have the cycle t and the cycle (T-t) as shown in FIG. 3B. Even in this case, the sequential circuit controlled by the internal clock CKI operates normally because the minimum cycle is designed to be t. The frequency of the external clock CKO has dropped,
Even if the cycle T becomes infinite, the sequential circuit controlled by the internal clock CKI operates normally only by extending the width of the low level of the internal clock CKI.

Next, a second embodiment of the present invention will be described.

FIG. 4 is a block diagram showing a second embodiment of the clock signal generating circuit of the present invention.

The second embodiment is realized by a more concrete circuit of the first embodiment.

The clock signal generation circuit of this embodiment is shown in FIG.
As shown in FIG. 3, in addition to the flip-flop 1 and the oscillator 2 in the first embodiment, a differentiation circuit 4 including an inverter that is a delay element and a NAND gate, a shift register 5, and an inverter I1 are provided. Is configured. The flip-flop 1 is composed of two NAND gates. The oscillator 2 includes inverters I21 to I26 which are delay elements connected in series with the NAND gate N21.
It consists of and. The shift register 5 is composed of D-type flip-flops 51 and 52.

Next, the operation of this embodiment will be described.

FIG. 5 is a time chart of the circuit of this embodiment shown in FIG.

Next, the operation of the clock signal generator of FIG. 4 will be described with reference to FIG.

In FIG. 5, it is a periodic signal of the external clock signal CKO period T. The differentiating circuit 4 detects the rising of the external clock signal CKO and generates the signal E. While the signal E is at the low level, the flip-flop 1 is set and the flip-flops 51 and 52 of the shift register 5 are set.
Is reset. When the signal F becomes high level, the NAND gate N21 of the oscillator 2 is opened.

The oscillator 2 oscillates at a cycle t while the signal F is at a high level, and outputs the internal clock CKI. The half cycle t / 2 includes NAND gate N21 inverters I21 to I21.
This is the sum of 26 delay times.

Flip-flop 3 of shift register 5
The inputs of 1, 32 are high level. Internal clock CK
The signal H goes high at the first fall of I, and the signal K goes high at the next fall.

During the period when the signal K is at the high level, the flip-flop 1 is reset, and the oscillator 2 stops when it outputs two pulses to the internal clock CKI. When the external clock CKO rises again, the flip-flop 1 is set and the above operation is repeated.

As described above, also in the second embodiment, two pulses of the cycle t are output for each cycle T. This corresponds to doubling the clock frequency.

In a similar manner, multiplication by n is possible. If the number of flip-flops 51 and 52 forming the shift register 5 is increased to n, n pulses of the cycle t are output for each cycle T.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various modifications can be made. For example, it goes without saying that a CR delay oscillator, a crystal oscillator, or the like may be used instead of the ring oscillator that uses an inverter as a delay element as an oscillator without departing from the gist of the present invention.

[0038]

As described above, the clock signal generating circuit of the present invention includes an oscillation control circuit for generating an oscillation control signal synchronized with an external clock, and the start and stop of oscillation controlled by the oscillation control signal. Since the oscillator circuit that outputs the clock signal and the pulse counter circuit that counts the internal clock signal and outputs the stop control signal when the set count value is reached, the duty ratio of the external clock must be 50%. Since it operates normally even if the cycle becomes long and becomes infinite, for example, there is an effect that power consumption can be reduced in proportion to the clock frequency.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a clock signal generation circuit of the present invention.

FIG. 2 is a time chart showing an example of the operation of the clock signal generation circuit of this embodiment.

FIG. 3 is a time chart showing another example of the operation of the clock signal generation circuit of this embodiment.

FIG. 4 is a block diagram showing an example of a conventional clock signal generation circuit.

FIG. 5 is a time chart showing an example of an operation in the conventional clock signal generation circuit.

[Explanation of symbols]

 1, 51, 52 Flip-flop 2 Oscillator circuit 3 Counter 4 Differentiator circuit 5 Shift register N21 NAND gate N21 NAND gate I1, I21 to I26 Inverter

Claims (2)

[Claims] 1. An oscillation control circuit that generates an oscillation control signal that is synchronized with a first clock input from the outside, and an oscillation that outputs and outputs a second clock signal whose start and stop are controlled by the oscillation control signal. And a pulse counting circuit that outputs a stop control signal that controls the oscillation control signal so as to stop the oscillation when the second clock signal is counted and reaches a predetermined count value. Clock signal generation circuit. 2. The oscillation control circuit includes an RS flip-flop set by the first clock and reset by the stop control signal, and the oscillation circuit has an output of the RS flip-flop connected to one input. 2. The clock signal generation circuit according to claim 1, further comprising a ring oscillator configured by serially connecting a NAND gate and at least one inverter on a ring.