JPH0628286B2 - Linear semiconductor integrated circuit - Google Patents

Description

The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit having a pattern layout that allows easy model expansion so as to meet the requirements of custom ICs. Is something
Furthermore, the present invention relates to a semiconductor integrated circuit that prevents interference.

(B) Conventional Technology In general, JP-A-59-84542 (H01L 2
1/76), a semiconductor integrated circuit technology for forming a plurality of circuit blocks on the same semiconductor substrate has a configuration shown in FIG.

FIG. 11 is a schematic plan view of the semiconductor chip (1).
Reference characters f to f denote circuit blocks. These circuit blocks have different frequencies and signal levels to be handled, and also have different functions.

This circuit block is formed in the N type region (3) on the P ⁻ type semiconductor substrate (2) as shown in FIG. 12, and each circuit block is adjacent to the periphery of the high concentration P ⁺ type region. It is divided by (4). Here, it is shown by block b and block c.

The P ⁺ type region (4) for this partition has one end in contact with the P ⁻ type semiconductor substrate (2) and the other end ohmic-connected to the ground line (6) through the oxide film (5) on the semiconductor surface. To be done.

The ground line (6) is collected from each block in the central part of the integrated circuit, and the ground bonding pad G at the left end
Has been extended to ND.

Next, the power supply line (Vcc) of each block circuit is gathered on the outer peripheral portion of the integrated circuit and individually connected to the power supply bonding pad, as shown in FIG.

On the other hand, since the circuit blocks a to f have different functions, the number of elements existing in the block is different and the block sizes are different.

(C) Problem to be Solved by the Invention As described above, since the circuit blocks a to f have different sizes, all the circuit blocks are efficiently and
In order to fit within (1), there is a problem that the size of each circuit block interacts with each other, which makes integration on the same chip difficult.

Further, when the circuit block a is deleted and another circuit block a'having improved characteristics is inserted, or a circuit block g having another function is added to the circuit block configuration of FIG. It was necessary to recreate all the patterns because the size of was different.

Therefore, in recent years, when the life of the product has become extremely short, if the user wants to embed a unique circuit desired by a user in a certain chip, the user desires a short circuit period, but the circuit It had a problem that it needed a very long delivery time to recreate the pattern.

In addition, signal wiring between circuit blocks and wiring such as a feedback line have a problem of causing interference due to unnecessary radiation from high frequency circuit blocks.

(D) Means for Solving the Problems The present invention has been made in view of the problems, and divides the semiconductor chip into a first region and a second region at the center of the semiconductor chip. The area is divided into a large number of mats having substantially the same size by division lines, a plurality of electronic block circuits having different functions are integrated into an integer number of mats, and the second ground line and the second ground line formed in the divided area are formed. In addition to the power supply line, a wiring area is provided, and this wiring is used as a signal line or a feedback line between electronic circuit blocks,
The solution is to provide a shield metal on this wiring.

Further, the problem is solved by providing second and third divided regions in the first and second regions, respectively, and providing shielded wiring similarly to the divided regions.

(E) Operation According to the present invention, the upper surface of the semiconductor chip is divided into a large number of mats having substantially the same size by the division line, and the electronic circuit blocks having a plurality of different functions are housed in an integer number of mats. Thus, it becomes possible to design each electronic circuit block and divide the electronic circuit block into a certain number of elements to design each mat. Therefore, it is possible to divide each electronic circuit block for parallel design, and it is possible to significantly reduce the design period.
Further, the circuit can be changed for each electronic circuit block and for each mat, so that it is not necessary to change the design of the entire IC.

On the other hand, the divided region divides the semiconductor chip into the first and second regions and extends from the left side to the right side of the semiconductor chip. By effectively using this region, the wiring does not intersect with other electrodes. It is provided. That is, in FIG. 1, the divided regions between the mat E and the mat J or between the mat K and the mat M are not provided with the first and second extension electrodes in the vertical direction, so that the wiring is arranged in this region. Can be provided arbitrarily. Similarly, the second and third divided regions are also provided in the vertical direction.

Furthermore, by providing a shield electrode on this wiring, it is possible to prevent interference without receiving unnecessary radiation from a region adjacent to this wiring.

(F) Example First, an example of the present invention will be described in detail with reference to FIG. For convenience of description, the structure of mat division, which is one of the features of the present invention, will be described here.

Using the divided region (11) indicated by the chain double-dashed line on the upper surface of the semiconductor chip (10), the first and second regions (1
2) and (13) are divided into two, and the respective areas (12) and (13) are A to
It is divided into mats J, K to T. A ~ J, K ~ T
Each mat is divided by a partition line ( 14 ) in which a power line and a ground line are adjacently extended in parallel.

Regarding the arrangement of the power supply line and the ground line forming the partition line ( 14 ), the power supply line is provided on the left side of each of the mats A to J and K to T, and the ground line is provided on the right side. Therefore, only the partition lines ( 14 ) at both ends are formed by one of the power supply line and the ground line, and the intermediate partition line is constituted by both. Power supply lines and ground lines adjacent to the mats A to J and K to T are integrated in the respective mats to supply power to the circuit blocks.

The first area (12) includes mats A to D that are the third area (15) and mats E to J that are the fourth area (16).
It is divided by the second divided area (17). Further, the second area (13) is provided with mats K to M which are the fifth areas (18), mats N to T which are the sixth areas (19), and third areas.
It is divided by the divided area (20).

The first power supply line (21) of the mats A to D is connected to the third power supply line (22) formed at the upper end of the mat,
It extends to the power supply pad V _CC1 . Further, the first power supply line (23) of the mats E to J is connected to the third power supply line (24) formed at the upper end of the mat, and the second layer electrode (25) hatched by dots is used. Cross over,
It is connected to the third power supply line (22) in the third region (15).

On the other hand, the first ground line of the mats A to D (26)
Is the second ground line (2
7) and extends to the ground pad GND1 via the second extension electrode (28). Further, the first ground lines (29) of the mats E to J are connected to the second ground line (30) formed at the lower end of the mat, and the second layer electrodes (31) hatched by dots are used. It crosses over and is connected to the second ground line (27) of the third region (15).

Mats K to M are V, which will become clear later.
Power supply and ground pads different from _CC1 , V _CC2 , NGD1 and NGD2 are used.

The first power supply line (32) of the mat N to mat T is connected to the second power supply line (33) formed at the upper end of the mat and is connected to the power supply pad V _CC2 by the first extension electrode (34). It has been extended. The first ground line (35) of the mats N to T is connected to the third ground line (36) formed at the lower end of the mat and extends to the ground pad GND2. Further, a ground line (37) extends in the clockwise direction from the left side of the mat E and is connected to the ground pad GND2.

Each of the mats A to J divided by the division line ( 14 ) described above
K to T are formed in a shape of substantially the same size, and specifically, the width is set so that six NPN transistors are arranged, and the length is a fixed number of elements which is easy to design, for example, It is set so that about 100 elements can be laid out. The size of this mat can be arbitrarily selected according to the number of elements that can be easily designed by an electronic circuit block to be integrated into an IC.

The circuit elements integrated in the mat are composed of transistors, diodes, resistors and capacitors, and are separated by normal PN separation, and the wiring of each element is connected by the first electrode layer of the two-layer wiring, with the exception of The electrodes of the second layer are crossed over.

Next, with reference to FIGS. 8A and 8B, the circuit elements integrated in the mat and the partition line ( 14 ) will be specifically described.

FIG. 8A is an enlarged top view of the vicinity of the mat B. The division line ( 40 ) indicated by the left-hand dashed line is the division line ( 14 ) provided between the mat A and the mat B, and the division line ( 41 ) indicated by the right-hand dashed line is the mat B and the mat. It is a division line ( 14 ) provided between C. And this division line
Between ( 40 ) and ( 41 ), the transistor (42) shown by the dotted line,
A diode (43), a resistor (44) and a capacitor (45) are integrated. Although these elements are rough in the drawing, they are actually densely integrated. The wiring between the elements in the mat is substantially formed by the first electrode layer (46) indicated by the alternate long and short dash line.
Wiring between the mat and the mat of the mat C, for example, a signal line and a feedback line are formed by the second electrode layer (47) shown by solid lines. The first and second electrode layers (46) and (47) are connected to each other at the contact regions indicated by the cross marks.

FIG. 8B is a sectional view taken along the line AA ′ in FIG. 8A. N type epitaxial layer on P type semiconductor substrate (48)
(49) are laminated, and a P ⁺ -type isolation region (5) that reaches the semiconductor substrate (48) from the surface of the epitaxial layer (49) is formed.
0) is formed, and many island regions are formed. An NPN transistor is provided in this island region (51).
(42), Diode (43), Resistor (44) and Capacitor (45)
Etc. are made, and an N ⁺ type buried region (53) is formed between the collector region (52) of the NPN transistor (42) and the semiconductor substrate (48). The epitaxial layer (4
A silicon oxide film (54) is formed on the surface of 9) by, for example, the CVD method.
And a first electrode layer (46) is formed on the silicon oxide film (54). An insulating film (55) such as PIX is formed so as to cover the first electrode layer (46), and a second electrode layer (47) is formed on the insulating film (55). Has been done. The power supply line (56) and the ground line (57) are provided on the isolation region (50), and the ground line (57) is in ohmic contact with the isolation region (50) to stabilize the substrate potential. I am measuring.

More specifically, as shown in FIG. 1, in the first area (12), A to
10 mats of J are formed, and K to K are formed in the second area (13).
Ten mats of T are formed, and the mats are formed in substantially the same space where about 100 elements can be integrated, and each mat is divided by a partition line ( 14 ).

AM / FM shown in FIG. 9 is contained in the above 20 mats.
A one-chip IC for a stereo tuner is formed. 9th
The figure is a block diagram for explaining this electronic block circuit. The FM front end block (60), FM-IF block (61), noise canceller block (62), multiplex decoder block (63), AM tuner block (64) ), A total of five electronic circuit blocks. Although each circuit block is well known, its function will be briefly described.

First, the FM front-end block (60) is a channel selection part of FM broadcasting, receives FM broadcasting signals of several tens of MHz to several hundreds of MHz, and converts them into an intermediate frequency signal of 10.7 MHz. Since it has about 250 pieces, K ~ M
Are collected on the mat. Next, the FM-IF block (6
In 1), the intermediate frequency signal is amplified and then detected to obtain an audio signal. Since it has about 430 elements, it is integrated in the mats E to I. The noise canceller block (62) is for removing pulse noise such as ignition noise. Since it has about 270 elements, it is integrated in the N to P mats. Further, the multiplex decoder block (63) is a block for stereo demodulating a stereo signal, and since it has about 390 elements, it is integrated in the mat of Q to T.
Lastly, the AM tuner block (64) is a channel selection part for AM broadcasting, converts the AM broadcasting signal received by the antenna to an intermediate frequency (450 KHz), and detects it to obtain an audio output. About 350 Since it has the element of
Collected on D mat.

Further, in FIG. 10A, FIG. 10B and FIG. 10C, an AM tuner block (64), a front end block (60), an FM-IF block (61) and a multiplex decoder block (63) are further added, respectively. A block diagram is shown.

First, the local oscillation circuit (OSC) (65) in the AM tuner block (64) of FIG.
X) (66) is on mat B, and automatic gain control circuit (AGC) (6
7), the high frequency amplifier circuit (RF) (68) and the intermediate frequency amplifier circuit (IF) (69) are on the mat C, and the detection circuit (DET) (70)
Of the mats A to D are substantially integrated on the mat D, and through the third power supply line (22) extending from the power supply pad V _{CC1 in the} shape of a octopus as shown in FIG. Power line (21)
_Is supplied with V _CC . In addition, the ground pad GND1 is provided with a second ground line on the first divided region (11) via one of four second extension electrodes (28) in the shape of octopus legs provided between the mat M and the mat N. (27), and each second ground line (27) is connected to the first ground line (26) of the mats A to D.

Next, the front end block (60) composed of the high frequency amplifier circuit (71), the mixing circuit (72) and the local oscillator circuit (73) of FIG. 10B handles a signal of a very small level of several μV. Dislikes the interference from other circuit blocks, especially the FM-IF block (61), and the local oscillator circuit (73) in this block oscillates itself to generate unnecessary radiation. Therefore, in particular, it is separated from the FM-IF block (61), and the OSC block (73) is most reluctant to interfere, so another power supply V _CC3 ,
We are using the V _CC4, GND3, GND4.

That is, the K- which is diagonal to the FM-IF block (61)
The local oscillator circuit (73) is integrated on the mat K, which is the corner of the mat, and the other pads V are provided on both sides of the local oscillator circuit (73).
_A first power supply line and a ground line are provided through CC4 and GND4. The other L and M mats are provided with the respective first power supply line and ground line through V _CC3 and GND ₃ .

On the other hand, the FM-IF block (61) including the intermediate frequency amplification circuit (74), the detection circuit (75), the S meter (76), etc.
~ Integrated on the mat I, the detection circuit (75) on the mat I,
The S meter (76) etc. is on the matte G, and further the intermediate frequency amplifier circuit
The limiter circuit and mute circuit in (74) are E, F
And G are practically integrated on the mat.

Here, a limiter circuit having a very high gain of 80 to 100 dB and a detection circuit (75) having a large signal level, and the limiter circuit and an S meter (76) having a large signal level generate oscillation due to feedback, and the detection circuit (75) and S Since the characteristic of the meter (76) deteriorates due to mutual interference, the first power supply line (23) of the mats E, F, G is connected to one third power supply line (24) and the first power supply line (24) of the mats H, I. One power supply line (23) is connected to one third power supply line (24). In addition, the matte J is an integrated circuit of optional circuits from the G user.
The power supply line (23) is also connected to one third power supply line (24).

The first ground line (29) on the E to J mats
Is a second ground line (27) to which the second extension electrode (28) extends from the ground pad GND1 and is connected at one end.
And are connected in the same manner as described above.

Then, the DC amplifier circuit (77), the decoder circuit (78), and the lamp driver circuit (79) of the multiplex decoder block (63) of FIG. 10C are arranged on the mat Q and the mat R, and the phase comparison circuit (80). , A low pass filter circuit (81), a voltage controlled oscillator (82), a frequency divider circuit (83), etc.
Are virtually integrated into. In addition, the first extension electrodes (34) extending from the power supply pad V _{CC2 in the} shape of octopuses are
It passes between the tuner block (64) and the FM-IF block (61), and the second power line (3) on the first divided region (11).
One end is connected to 3). And one to mat Q and R 1
A book extends to the mats S and T, and one extends to the mats N to P which become the noise canceller block (62).

On the other hand, the ground pad GND2 has two octopus-like third pads.
Connected to the ground line (36) of
It extends to the mat of P, the mat of Q, R, and the mat of S, T.

Further, for the purpose of preventing mutual interference between blocks, pad V
_CC1 and V _CC2 and pads GND1 and GND2 are separately used, the pads V _CC1 and V _CC2 are connected to one lead, and the pads GND1 and GND2 are connected to one lead. This prevents the fluctuation of the pad V _CC1 from being directly transmitted to the pad V _CC2 , and by using two thin metal wires,
The impedance of this thin metal wire is lowered. Therefore, the pulse noise or the like that has entered the leads is not amplified through the impedance, and voltage fluctuations can be prevented.

The above is a description of mat division, and an example of this characteristic point will be described. For example, if the AM tuner block (64) is not needed, four mats that will be the multiplex decoder block (63) are integrated as they are in the mats A to D, and the mats I and J are put in the remaining mats Q and R, for example. To be integrated. Therefore, the I, J, S, and T mats become redundant, so that by removing this mat, the mats can be neatly housed in a rectangular chip. Here, the wiring of the first layer in the mat is used as it is, and only the wiring between the mats and the wiring between the blocks may be considered.

Further, when the FM-IF block (61) is partially improved, for example, only the mat F which is an improved part may be taken out and improved, and the other mats E, G and H can be used as they are. When adding another block which is an option for the user, all the mats are used as they are, and the required number of mats may be added to this block. Here, the mat J is used as this option mat.

That is, since mats having the same size are formed in a matrix, replacement, addition, and deletion are very easy.

Next, the shield electrode will be described. The hatched area in FIG. 1 is the shield electrode, and the configuration of this shield electrode is shown in FIGS. 3 to 7. Also, thick solid lines indicate wiring.

As described above, in the first divided region (11), the second power supply line (33) and the second ground line (30) are provided on the first layer in parallel from the left side to the right side, Second divided area (1
A first extension electrode (34) and a second extension electrode (28) are provided on the first layer in 7) and the third divided region (20). The first
If the width of the decomposition area (11) of the mat is expanded, for example, the second ground line (30) connected to the first ground run-in of the mat F and the mat G and the first ground of the mat H and the mat I. The second ground line (3
It is possible to widen the distance from (0). Therefore, wiring can be provided from the mat H to the point f. Also, the second ground line (30) of the mat J and the second ground line of the mat S and the mat T.
Wiring can be provided from below the mat E to below the mat J by widening the distance from the power supply line (33).

As described above, the first divided region 11 can be utilized as a wiring region except for the region where the first extension electrode 34 and the second extension electrode 28 are concentrated. The second and third divided areas
Similarly, (17) and (20) can be utilized, and an example is shown by the wiring connecting from the mat M to the mat E through the points a, b and c.

More specifically, the wiring extending from the mat H extends horizontally to the point f, and extends vertically from the point f to the point e to form the first layer. The points e to d are formed on the second layer in order to cross over the second power supply line (33). The wiring extending from the mat M extends horizontally from the point a to the point b, and is formed in the second layer to cross over the second extension electrode (28). In order to avoid the electrode of the second layer hatched at the points from b to point c, the first
It is formed in the layer. From point c to mat E,
To cross over the first extension electrode (34), the second
It is formed in the layer. In the above configuration, the first
Substantially all of the wiring portion formed in the layer is provided with the shield electrode in the second layer. An example of this is shown in the hatched area. The relationship between the shield electrode, the wiring, and the semiconductor substrate is shown in FIGS. 3 to 7 as a cross-sectional view taken along the line AA 'in the drawings.

Further, in FIG. 2, the first to third divided areas (11), (1
The dummy islands (90) formed in (7) and (20) are shown. The dummy islands (90) are quadruple as shown in the figure, but the number is not limited to this. This dummy island
As can be seen from FIG. 3, (90) is a P ^K type isolation region (9) reaching the semiconductor substrate (91) to which the ground potential is given.
Since it is composed of the N type epitaxial layer surrounded by 2), a barrier is formed by this PN junction, and it becomes possible to prevent a leak current.

Next, the sectional views of FIGS. 3 to 7 will be described. First, in FIG. 3, there are two N-type dummy islands (90) surrounded by P-type isolation regions (92).
Wiring (93) is provided through the first-layer insulating film above (0). A first shield electrode (94) is provided on both sides of the wiring (93), and a second insulating film is formed so as to cover the wiring (93) and the first shield electrode (94). The second shield electrode (94) and ohmic contact with the first shield electrode (94) through the second insulating film to cover the first shield electrode (94) and the wiring (93). 95) has been formed. Here, V _CC or GND may be applied to the second shield electrode (95).

Next, FIG. 4 is almost the same as FIG. 3, but the first shield electrode (94) is in ohmic contact with the N-type island region (90). Where the second shield electrode
(95) may be applied to V _CC .

Then, in FIG. 5, the first shield electrode (94) is in ohmic contact with the P-type isolation region (92), and wiring is provided in the dummy island region (90). Therefore the second
The shield electrode (95) is applied to GND.

Subsequently, FIG. 6 has a three-layer structure unlike the example described above. The first shield electrode (9
4) is in ohmic contact with the isolation region (92).
The wiring (93) is formed on the second layer, and the second shield electrodes (95) are provided on both sides of the wiring (93).
4) as an ohmic contact, and a third shield electrode (96) of the third layer is formed so as to cover the second shield electrode (95) and the wiring (93).

Here, the first shield electrode (94) of the first layer may be the same as the polysilicon low antibody formed in the mat, for example. In addition, the above-described configuration produces the same effect as that of the one-core shielded wire used conventionally.

Further, FIG. 7 shows an example in which the wiring (93) and the shield electrode are provided on the P-type isolation region (92). Here, the first shield electrode (94) makes ohmic contact with the isolation region (92). However, this is not the case. A three-layer structure may be used as shown in FIG. In the above description, the wiring (93) is provided on the first divided area (11), but the second and third divided areas are described.
Similarly, the configurations of FIGS. 3 to 7 can be implemented in (17) and (20).

(G) Effect of the invention As is apparent from the above description, firstly, the dividing line ( 14 )
By dividing the upper surface of the semiconductor chip (10) into a large number of mats of substantially the same size and accommodating a plurality of electronic circuit blocks having different functions in an integer number of mats, it is possible to design in parallel for each electronic circuit block The design period can be greatly shortened. Further, since the electronic circuit block is divided into a certain number of elements and the design for each mat can be performed, the parallel design for each mat can also be performed. Further, since circuit changes such as deletion, addition, and correction can be designed for each electronic circuit block or each block, only the change for each block or each mat is sufficient, and the design change of the entire IC is not necessary. Furthermore, since the mat can be made into a cell as a basic block, once the design is completed, other mats can be used as they are, and the reliability can be improved very much by modifying only the mat to be changed when the circuit is changed thereafter.

Further, the wiring (93) is provided in the divided areas by widening the width of the divided areas (11), (17) and (20). Moreover, by changing the positions of the second ground line (30) and the second power supply line (33), the first divided region (11) excluding the first and second extension electrodes (34), (28). ), The wiring can be provided horizontally with an arbitrary length. On the other hand, by changing the positions of the first and second extension electrodes, the second and third divided regions are formed.
Wiring is also provided in (17) and (20).

Secondly, it is possible to effectively shield by utilizing the isolation region (92) and the dummy island (90) formed in the divided regions (11), (17) and (20). That is, by providing the first and second shield electrodes (94) and (95) as shown in FIG. 3, unnecessary radiation from above and from the side can be prevented. 4 is an N-type island region (90), FIG. 5 is a P-type isolation region (92) and semiconductor substrate (91), FIG. 6 is the first shield electrode (94), and FIG. The lower layer of the wiring can also be shielded by the P-type isolation region (92), and it can be used like a single-core shield wire that has been conventionally used. Therefore, interference can be prevented without receiving unnecessary radiation from the electric circuit block.

[Brief description of drawings]

1 is a plan view showing a semiconductor device of the present invention, FIG. 2 is a view showing a dummy island formed in FIG. 1, FIG. 3 is a view showing an example of a shield electrode used in FIG. 4 is a diagram showing an example of the shield electrode used in FIG. 1, FIG. 5 is a diagram showing an example of the shield electrode used in FIG. 1, and FIG. 6 is a diagram showing an example of the shield electrode used in FIG. FIG. 7 is a diagram showing an example of the shield electrode used in FIG. 1, FIG. 8A is a partially enlarged view of the mat B, and FIG. 8B is A- of FIG. 8A.
A sectional view taken along line A ', FIG. 9 is an AM / FM stereo tuner block circuit diagram, FIG. 10A is an AM tuner block diagram, and FIG. 10B is a diagram for explaining an FM front end block and an FM-IF block, FIG. 10C is a multiplex decoder block diagram, FIG. 11 is a plan view of a conventional semiconductor integrated circuit, and FIG. 12 is a sectional view between block b and block c in FIG. (10) …… Semiconductor chip, (11) …… Divided area, (12) …… First area, (13) …… Second area, (14) …… Division line,
(15) ... third area, (16) ... fourth area, (17) ... second divided area, (18) ... fifth area, (19) ... sixth area , (20) …… third divided area, (27), (30) …… second ground line, (33) …… second power supply line, (90) …… dummy island, (93) ... … Wiring, (94)… First shield power supply, (95)… Second shield electrode, (96)… Third shield electrode.

Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 27/04 A 8427-4M

Claims (4)

[Claims] 1. A division region that substantially divides the semiconductor chip into a first region and a second region in the center of the semiconductor layer of the semiconductor chip, and is positioned in the first region and the second region, An arrangement region (mat) of semiconductor elements formed in the semiconductor layer, which is formed of a plurality of shapes having substantially the same size; and a first power supply line provided on one side of the arrangement region (mat). A first ground line provided on the other side opposite to the one side, and the first power line and the first ground line are electrically connected to a power pad and a ground pad around the semiconductor chip. In order to achieve this, the second power supply line and the second ground line arranged in the divided region in the direction orthogonal to the first power supply line and the first ground line, and the size of the circuit is substantially A linear semiconductor integrated circuit in which a semiconductor element of a linear electronic circuit including a plurality of electronic circuit blocks divided according to different functions is formed in the arrangement region (mat), All the semiconductor elements are substantially formed in a plurality of placement areas (mats) obtained by dividing the total number of semiconductor elements of the electronic circuit block in units of the placement area (mat). A linear semiconductor integrated circuit characterized in that a signal line connecting between the mats is provided between power supply lines or between the second ground lines. 2. The linear semiconductor integrated circuit according to claim 1, wherein a shield electrode is provided on the wiring. 3. The linear semiconductor according to claim 2, wherein the semiconductor layer in the divided region is provided with an isolation region for isolating the semiconductor layer, and the isolation region and the shield electrode are electrically connected. Integrated circuit. 4. A dummy island completely surrounded by the isolation region is provided in the divided region, and the dummy island and the shield electrode are electrically connected.
A linear semiconductor integrated circuit according to the item.