JPH06282940A - Phase synchronizing circuit for recording and reproducing device - Google Patents

Abstract

PURPOSE:To obtain a phase synchronizing circuit capable of stopping the read phase synchronism when a write phase synchronism is out of synchronism by monitoring the phase synchronizing state of a write phase synchronization oscillation circuit. CONSTITUTION:A servo phase synchronization oscillation circuit 11 synchronizes a bite clock for controlling the revolving speed of a motor with a phase synchronizing signal 1b and generates a phase synchronization completion signal 1c at the time of the completion of the synchronism. A write phase synchronization oscillation circuit 12 synchronizes write clocks 1e, 1f with a bite clock 1d. A sub-phase synchronization controlling circuit 14 monitors whether the write clock 1d is made to be a prescribed frequency dividing rate or not and outputs phase synchronization completion signals 1g, 1k when a coincidence is made. A main phase synchronization controlling circuit 13 forms reference clocks 1i, 1f from the write clocks 1e, 1f in a condition that the phase synchronization completion signals 1c, 1g are supplied. A read phase synchronization oscillation circuit 15 synchronizes a read clock with reference clocks 1i, 1j.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in a recording / reproducing apparatus for magnetic disks and the like, and is a phase synchronizing circuit for synchronizing a servo phase of a motor for rotating an information recording medium and a clock phase for reading / writing information recording medium. Regarding

[0002]

2. Description of the Related Art A conventional phase synchronizing circuit used in, for example, a magnetic disk recording / reproducing apparatus is a servo phase synchronous oscillation for synchronizing the servo phase of a disk rotating motor with a phase synchronizing signal based on a read signal from the disk. A circuit and a read / write phase-locked oscillation circuit for synchronizing the clock phase for disk read / write.
Generally, the output of the servo phase locked oscillator is divided by the write phase locked oscillator and the read phase locked oscillator is synchronized by the divided output.

However, in the conventional phase locked loop circuit as described above, the phase locked end signal is output to the servo phase locked oscillator circuit so that the sync state can be recognized, but the write phase locked oscillator circuit outputs the phase locked signal. Since the phase synchronization state cannot be easily grasped, its output is supplied to the read phase synchronization oscillation circuit as a reference clock regardless of whether the phase synchronization is abnormal or normal.

[0004]

As described above, in the phase synchronization circuit of the conventional recording / reproducing apparatus, the phase synchronization state of the write phase synchronization oscillation circuit could not be easily grasped. Further, the reference clock is supplied to the read phase locked oscillator circuit regardless of whether the output phase locked state of the write phase locked oscillator circuit is abnormal or normal. Therefore, if the phase synchronization of the write phase synchronization output becomes abnormal, an error may occur in the read phase synchronization and an error may occur in the reproduced data.

The present invention has been made in order to solve the above problems, and it is possible to easily grasp the phase-locked state of the write phase-locked oscillator circuit. It is an object of the present invention to provide a phase synchronization circuit of a recording / reproducing apparatus that is not performed and does not cause an error in reproduced data.

[0006]

A phase synchronization circuit of a recording / reproducing apparatus according to the present invention generates a byte clock for servo phase synchronization for controlling the number of rotations of a motor for rotating an information recording medium. A servo phase-locked oscillation circuit that synchronizes with a phase-locked signal representing the number of rotations of the motor and generates a phase-locked end signal after the synchronization is finished, and a write clock for writing information to the information recording medium, and the write clock To the byte clock output from the servo phase-locked oscillator circuit, and the write clock output from the write phase-locked oscillator circuit is counted by the byte clock, Monitor whether or not it has a predetermined frequency division ratio, and when it matches, phase synchronization Write output from the write phase-locked oscillator circuit, provided that each phase-locked end signal is supplied from the sub-phase-locked loop control circuit that outputs the end signal and the servo phase-locked oscillator circuit and the sub-phase-locked loop control circuit. A main phase synchronization control circuit for generating a reference clock from a clock and a read phase synchronization oscillation circuit for generating a read clock for reading information from the information recording medium and synchronizing the read clock with a reference clock. Composed.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

Referring to FIG. 1, a phase synchronization circuit of a magnetic disk recording / reproducing apparatus according to the present invention comprises a servo phase synchronization oscillation circuit 11, a write phase synchronization oscillation circuit 12, a main phase synchronization control circuit 13, and a sub phase synchronization control circuit. 14 and a read phase locked oscillator circuit 15.

The servo phase synchronous oscillator 11 generates a half byte clock 1d for servo phase synchronization for controlling the rotation speed of a disk rotation motor, and this half byte clock 1d is a phase synchronization signal 1b representing the rotation speed of the motor. To the phase synchronization end signal (1) 1
generate c.

The write phase synchronous oscillator circuit 12 generates a pair of write clocks (1) 1e and write clock (0) 1f, and the write clocks 1e and 1f are half-byte clocks output from the servo phase synchronous oscillator circuit 11. 1d
Sync to.

The sub phase synchronization control circuit 14 is provided with a write clock 1e output from the write phase synchronization oscillation circuit 12.
For 1f, by counting the half-byte clock 1d output from the servo phase-locked oscillator circuit 11, it is monitored whether the half-byte clock 1d has a predetermined frequency division ratio, and it is determined that the frequency division ratio is equal. Only at this time, the phase synchronization end signals 1g and 1k are output.

The main phase synchronization control circuit 13 is activated by the phase synchronization signal 1b, and the servo phase synchronization oscillation circuit 11 is activated.
And the phase synchronization end signal 1 from the sub phase synchronization control circuit 14.
Provided that c and 1g are supplied, the reference clocks (1) 1i and (0) 1j synchronized with the write clocks 1e and 1f output from the write phase locked oscillator circuit 12 are generated. Then, the main phase synchronization control circuit 13 outputs the generated reference clocks (1) 1i and (0) 1j when the enable signal 1a designating the output is given. The main phase synchronization control circuit 13 receives the phase synchronization end signals 1c and 1g, and outputs the phase synchronization end signal 1h when the reference clocks (1) 1i and (0) 1j are synchronized with the write clocks 1e and 1f. To do.

The read phase locked oscillator circuit 15 generates a read clock for reading information from the disk and synchronizes the read clock with the reference clocks 1i and 1j output from the main phase locked control circuit 13.

The operation of the above configuration will be described below with reference to FIGS. 2 and 3.

FIG. 2 shows the timing relationship of each circuit output of the phase-locked loop having the above-mentioned structure. FIG. 3 shows the enable signal 1a, the phase-locked signal 1b, and the phase-locked end signal 1.
With respect to c and 1g, the truth table shows the conditions under which the main phase synchronization control circuit 13 outputs the reference clocks 1h and 1j.

When the enable signal 1a is at L (low) level (designating that output is disabled), the phase synchronization signal 1b
Is inverted from the L level to the H (high) level, the servo phase synchronization oscillator circuit 11 synchronizes the half byte clock 1d with the phase synchronization signal 1b, and after the synchronization is completed, sets the phase synchronization end signal (1) 1c to the H level. To do.

Next, the write phase locked oscillator circuit 12 receives the half byte clock 1d and receives the write clocks 1e and 1e.
Synchronize f. Then, the sub phase synchronization control circuit 14 writes the write clock 1 based on the half byte clock 1d.
e, 1f are monitored, the half byte clock 1d is counted for a certain period, and if the write clocks 1e, 1f are normally synchronized during that period, the phase synchronization end signals 1g, 1k are set to the H level. If it is abnormal, leave it at the L level.

The main phase synchronization control circuit 13 receives the phase synchronization signal 1b and enters a synchronization monitoring state, and the servo phase synchronization oscillation circuit 11 and the sub phase synchronization control circuit 14 send H level phase synchronization end signals 1c and 1g. Whether or not the write phase locked oscillator circuit 12 is normally performing the synchronization processing is determined depending on whether or not the write phase locked oscillator 12 is present.

When the phase synchronization end signals 1c and 1g are both at H level, the reference clocks 1i and 1j synchronized with the write clocks 1e and 1f are generated. Then, after waiting for the enable signal 1a to become the H level (output designation), the reference clocks 1i and 1j that have been subjected to the synchronous processing are output to the read phase locked oscillator circuit 5, and the read clocks are synchronized with the reference clocks 1i and 1j. .

In the main phase synchronization control circuit 13, the phase synchronization end signal 1c from the servo phase synchronization oscillation circuit 11 and the phase synchronization end signal 1g from the sub phase synchronization control circuit 14 are at H level, and the reference clock The phase synchronization end signal (3) 1h is output immediately after 1i and 1j are synchronized with the write clocks 1e and 1f. As a result, the subsequent circuit can recognize that the synchronization processing has been completed.

Therefore, the phase synchronization circuit having the above configuration monitors the phase synchronization processing for the write clock as well,
Since the read clocks are synchronized with the reference clocks 1i and 1j only when the write clock is normal, it is possible to prevent an error from occurring during disk reproduction.

In the above embodiment, the phase synchronization control circuit is divided into main and sub, but they are integrated as shown in FIG. 4 (the same parts as those in FIG. 1 are designated by the same reference numerals). The phase synchronization control circuit 18 described above may be used.

Further, in the embodiment shown in FIG. 4, the half byte clock 1d is supplied to the phase synchronization control circuit 18, but FIG. 5 (the same parts as those in FIG. 4 are designated by the same reference numerals).
As shown in, the phase synchronization control circuit 18 may be replaced with a phase synchronization control circuit 18a to which the half-byte clock 1d is not supplied.

In addition, it goes without saying that the present invention is not limited to any of the above-described embodiments, and can be implemented with various modifications within the scope of the invention.

[0025]

As described above, according to the present invention, the phase locked state of the write phase locked oscillator can be easily grasped, and when the write phase locked is lost, the read phase locked is not performed. It is possible to provide a phase synchronization circuit of a recording / reproducing apparatus in which an error does not occur in reproduced data.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing a configuration of an embodiment of a phase synchronization circuit of a recording / reproducing apparatus according to the present invention.

FIG. 2 is a timing chart showing the input / output timing relationship of the output signal of the main part of the embodiment of FIG.

FIG. 3 is a truth table showing conditions under which the main phase synchronization control circuit of the embodiment of FIG. 1 outputs a reference clock.

FIG. 4 is a block circuit diagram showing a configuration of another embodiment according to the present invention.

FIG. 5 is a block circuit diagram showing a configuration of still another embodiment according to the present invention.

[Explanation of symbols]

 11 Servo Phase Synchronous Oscillator 12 Write Phase Synchronous Oscillator 13 Main Phase Synchronous Control Circuit 14 Sub Phase Synchronous Oscillator 1 5 Read Phase Synchronous Oscillator 1a Enable Signal 1b Phase Synchronous Signal 1c Phase Synchronous End Signal (1) 1d Half Byte Clock 1e , 1f Write clock (1), (0) 1g Phase synchronization end signal (2) 1h Phase synchronization end signal (3) 1i, 1j Reference clock (1), (0) 1k Phase synchronization end signal (4) 18, 18a Phase synchronization control circuit

Claims (3)

[Claims] 1. A servo phase synchronization byte clock for controlling the number of revolutions of an information recording medium rotation motor is generated, the byte clock is synchronized with a phase synchronization signal representing the number of revolutions of the motor, and after completion of the synchronization. A servo phase-locked oscillation circuit that generates a phase-locking end signal, and a write clock that generates a write clock for writing information on the information recording medium and synchronizes the write clock with a byte clock output from the servo phase-locked oscillation circuit. The phase-locked oscillator circuit and the write clock output from the write-phase-locked oscillator circuit are counted by the byte clock to monitor whether or not the byte clock has a predetermined frequency division ratio. A sub phase synchronization control circuit that outputs a phase synchronization end signal when they match, the servo phase synchronization Main phase synchronization control for generating a reference clock from the write clock output from the write phase synchronization oscillation circuit, provided that each phase synchronization end signal output from the oscillation circuit and the sub phase synchronization control circuit is input. A phase synchronization circuit for a recording / reproducing apparatus, comprising: a circuit; and a read phase-locked oscillation circuit that generates a read clock for reading information from the information recording medium and synchronizes the read clock with the reference clock. . 2. The phase synchronization circuit of the recording / reproducing apparatus according to claim 1, wherein the main phase synchronization control circuit and the sub phase synchronization control circuit are integrated. 3. The phase synchronization of the recording / reproducing apparatus according to claim 1, wherein the main phase synchronization control circuit has a function of notifying the end of the phase synchronization of the servo phase synchronization oscillation circuit and the write phase synchronization oscillation circuit. circuit.