JPH0628863Y2 - Liquid crystal display - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a liquid crystal display device, and more particularly to an active matrix type liquid crystal display device.

[Prior Art and Problems Thereof]
Active matrix type liquid crystal display devices are known. The active matrix type liquid crystal display panel is generally constructed as shown in FIG. That is, the gate drive signals X1, X2, gate lines (gate lines) which ... is input 1a, 1b, ... and segment signals _Y 1, Y
Segment line (drain line) 2 to which ₂ , ... Is input
Liquid crystal driving TFTs (thin film transistors) 3aa, 3ab, ..., 3ba, 3bb, ... Are provided at respective intersections with a, 2b ,. In this case, the TFTs 3aa, 3ab, ..., 3ba,
In 3bb, ..., the gate electrodes are gate lines 1a, 1b ,.
, And the drain electrodes are connected to the segment lines 2a, 2b ,. And the above T
, 3ba, 3bb, ... Between the source electrodes of the FTs 3aa, 3ab, ..., 3ba, 3bb, ... And the common voltage V _COM are provided parallel circuits of the liquid crystal elements 4, 4 ,. The capacitor 5 has the capacity of the liquid crystal layer, but an auxiliary capacitor may be attached separately. In addition, the TFTs 3aa, 3ab,
A common electrode to which a constant common voltage V _COM is applied is provided on the substrate on the opposite side of the substrate on which the liquid crystal element 4 is provided. Then, the active matrix type liquid crystal display panel 6 configured as described above is
It is driven by the drive circuit shown in FIG. In this case, the liquid crystal display panel 6 is provided with scanning lines (gate lines) that are almost twice the number of scanning lines of the video signal.

In FIG. 4, 11a, 11b, ..., 12a, 12b, ... are sample circuits, which are color video signals (Video signals) A,
B and C are input. The sample circuits 11a, 11b,
, 12a, 12b, ... are sampling signals YS1, YS3, ..., YS provided from the shift registers 13a, 13b.
2, YS4, ... Sequentially sample the video signals A, B and C, and output them to the hold circuits 14a and 14b. The shift registers 13a, 13b, ... Are odd-numbered signals DY which are alternately applied from the timing circuit (not shown) every horizontal scanning.
O and the even signal DYE are sequentially shifted in synchronization with the clock pulse φ _S , and m / 2 sampling signals YS1, YS3, ..., YS2, YS4 are respectively generated within one horizontal scanning period.
... is generated. The hold circuits 14a and 14b are then
Is the latch clock φ _L given by the timing circuit.
Thus, the signals from the sample circuits 11a, 11b, ... 12a, 12b, ... Are read and held until the next cycle, and the segment electrodes of the liquid crystal display panel 6 are driven.

Further, the liquid crystal display panel 6 is supplied with gate drive signals X1, X3, ... From the odd side gate drive circuit 15a, and gate drive signals X2, X4 ... From the even side gate drive circuit 15a. The gate driving circuits 15a and 15b output odd and even timing signals DXO and DXE output from the timing circuit in synchronization with the vertical synchronizing signal as clock pulses φ.
_XO , φ _XE are read and sequentially shifted to generate the gate drive signals X1, X3, ..., X2, X4.

In FIG. 4, the video signals A, B, and C are arranged in the order of R, G, and B for each 1H because the color pixel array of the liquid crystal display panel 6 has a mosaic shape as shown in FIG. Needs to be changed and is output through the circuit shown in FIG.

In FIG. 5, 16a to 16c are inversion control circuits for R, G, and
The video signal of B is inverted every time the frame signal φ _F is given and is input in parallel to the switching circuits 17a to 17c. Switching circuit
Reference numerals 17a to 17c sequentially switch the signals R, G, B from the inversion control circuits 16a to 16c in accordance with the switching signals φ _{HP1 to} φ _HP3 provided by the timing circuit, and the above sample circuits 11a, 11b, ..., 12a, Output to 12b, ...

In the above configuration, when the liquid crystal display panel 6 has the same number of scanning lines as the standard of the video signal (525 in the NTSC system, 480 effective scanning lines), the video signal is sent in the interlaced system. Then, every other scanning line is scanned. Now, assuming that video signals of 1H, 3H, 5H, ... Are sent in odd fields as shown in FIG. 7, first, the video signal of 1H is sampled by the sampling circuit.
.. are sampled in synchronism with the sampling signal from the shift register 13a and held in the hold circuit 14a. Signal held in the hold circuit 14a during the next 1H in synchronism with the latch pulse phi _L, the segment signals Y1, Y3, are sent as ... to the liquid crystal display panel 6. At this time, if the gate drive signal X1 is output from the odd-numbered gate drive circuit 15a,
As shown in FIG. 3, the TFT 3aa provided at the intersection of the common line 1a and the segment line 2a is turned on while the gate drive signal X1 is applied, and the TFT 3aa is supplied with the video signal supplied from the sample hold circuit 14a. Charge the level to capacitor 5. Since the TFT 3aa is held in the ON state while the gate drive signal X1 is applied, the terminal voltage (X1, Y1) of the capacitor 5 during that period.
Is held at the above video signal level. Thereafter, when the timing signal φ _XO is applied to the odd-numbered gate drive circuit 15a to shift the held data, the gate drive signal X1
Goes low and the gate drive signal X3 goes high. When the gate drive signal X1 becomes low level, the TFT 3aa is turned off, the electric charge charged in the capacitor 5 starts to be discharged, and the terminal voltage (X1, Y1) thereof is sequentially decreased. Then, after that, when the gate drive signal X1 is output from the odd-numbered gate drive circuit 15a in the next frame, TF
T3aa is turned on again, and at that time, charging of the capacitor 5 is started according to the video signal output from the hold circuit 14a. At this time, the level of the video signal is controlled by the inversion control circuit 16
Since it is inverted by a to 16c, the capacitor 5 is charged with a voltage in the opposite direction to the common voltage V _COM from the previous frame.

In this way, the terminal voltage of the capacitor 5 changes as shown in FIG. 7, and the liquid crystal element 4 is drive-controlled according to this voltage.

As described above, in the conventional liquid crystal driving method, the charge / discharge cycle of each pixel in the liquid crystal display panel 6 is in units of one frame, and flicker of 30 Hz occurs. In the case of a TV screen, if the frequency of flicker is reduced to 30 Hz, it will be quite annoying to the viewer, and there is a problem that the image will be considerably difficult to see.

However, when displaying an interlaced video signal, flicker of 30 Hz occurs as described above. Therefore, it is conceivable that the line-sequential system is used for display in order to reduce the flicker. However, for that purpose, since the original information is only for every other scanning line, it is necessary to display two scanning lines at the same time or provide a memory for one line.

In the former case, in the case of the active matrix type liquid crystal display device, the cycle of charging / discharging the pixel becomes the same as that at the time of interlace, and flicker cannot be prevented.

On the other hand, in the latter, in the case of the active matrix type, since it originally has a hold circuit for one line, it is conceivable to read it out twice for the first and second lines. However, in the case of the active matrix type, since the analog information is held as it is, there is a problem that the electric charge that has been charged once is discharged and the second time reading cannot be performed.

[Object of the Invention] The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an active matrix type liquid crystal display device that can realize line-sequential scanning and reduce the influence of flicker.

[Points of the Invention] In the present invention, in the active matrix type liquid crystal display device, when the video signals of N scanning lines of one field transmitted by the interlace system are displayed on a liquid crystal display panel having scanning lines of approximately 2N. A first hold circuit that samples and holds a video signal to be displayed on the n-th (n is an odd or even) scanning line of the liquid crystal display panel;
A second hold circuit for holding the same information as the hold circuit of FIG. 2 is provided, and the electric charge charged in the first hold circuit is discharged at a first timing within a predetermined period to discharge the nth pixel of the liquid crystal display panel. Line-sequential scanning is performed by discharging the charges stored in the second hold circuit to the (n + 1) th pixel at the second timing during the predetermined period. .

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, 21a, 21b, ...
Color video signals A, B, C sent from the switching circuits 17a to 17c shown in the figure are input. The sample circuits 21a and 21
.. are supplied from the shift register 22 in response to the sampling signals YS1, YS2 ,.
The signals A, B, C from 17c are sequentially sampled and the first
Of the hold circuits 23a, 23b, ... The shift register 22 sequentially shifts a signal DY given from a timing circuit (not shown) every horizontal scanning in synchronization with the clock pulse φ _S , and m sampling signals YS1 and YS2 within one horizontal scanning period. , ... is generated. Further, except for the sample circuit 21a at the first stage, the sample circuit 21b,
The outputs of 21c, ... Are the second hold circuits 24a, 24b ,.
Sent to. The hold circuits 23a, 23b, ..., 24a,
24b hold the output signals of the sampling circuits 21a, 21b, ... And output them in synchronization with the latch pulse φ _L sent from the timing circuit. Latch pulse φ
_L is the horizontal erase (retrace) period BH as shown in FIG.
High level only during. The first hold circuits 23a, 23b, ... And the second hold circuits 24a, 24
The signals output from b, ... Are changeover switches 25a, 25
selected by b, ..., Segment drive signals Y1, Y
2, ... Are sent to the TFT liquid crystal display panel 26. The changeover switches 25a, 25b, ... Are controlled by a switch signal SW sent from the timing circuit.
As shown in FIG. 2, the switch signal SW becomes high level only in the latter half of the horizontal erasing period BH.

Further, the liquid crystal display panel 26 is provided with m, for example, 480 scanning lines, which is almost twice the number of scanning lines of the video signal, and its gate electrode is formed by the odd side gate drive circuit 27 and the even side gate drive circuit 28. Driven. The odd-numbered gate drive circuit 27 reads and shifts the odd-numbered timing signal DXO synchronized with the vertical synchronizing signal sent from the timing circuit by the clock pulse φ _XO , and shifts the odd-numbered gate drive signals X1, X3, X5, ... Occur. The even-numbered side gate drive circuit 28 reads and shifts the even-numbered timing signal DXE synchronized with the vertical synchronizing signal sent from the timing circuit by the clock pulse φ _XE , and shifts the even-numbered side gate drive signals X2, X4, X6. ... is generated.

Next, the operation of the above embodiment will be described with reference to the timing chart of FIG. The sampling circuits 21a, 21b, ... Sample the color video signals A-C sent from the switching circuits 17a-17c shown in FIG. 5 in synchronization with the sampling signals YS1, YS2 ,. ,twenty three
Output to b, ... The outputs of the other sample circuits 21b, 21c, ... Excluding the first-stage sample circuit 21a are sent to the second hold circuits 24a, 24b ,. The hold circuits 23a, 23b, ..., 24a, 24b ,.
Hold the signals sampled by a, 21b, .... As described above, the video signals A to C for one horizontal scanning line are sampled by the sampling circuits 21a, 21b ... And held in the first hold circuits 23a, 23b ,. It And
When one horizontal period is completed and the horizontal erase period BH shown in FIG. 2 is entered, the latch pulse φ _L becomes high level, and the signals held in the hold circuits 23a, 23b, ..., 24a, 24b ,. Is output. Further, in the first half of the horizontal erasing period, the switch signal SW is held at the low level and the changeover switches 25a, 25b, ... Are held in the first hold circuit.
23a, 23b, ... Side is selected. Therefore, it is held in the first hold circuits 23a, 23b, .... The signals are sent to the liquid crystal display panel 26 as segment drive signals Y1, Y2, .... In the first half of the horizontal erase period BH,
A gate drive signal is output from the odd-numbered gate drive circuit 27 and sent to the TFT liquid crystal display panel 26. If the gate drive signal X1 is output from the odd-numbered side gate drive circuit 27, for example, the TFT liquid crystal display panel 26 is
In the figure, the TFT 3 connected to the gate line 1a
.. are turned on, and the capacitor 5 is charged to the level of the segment signals Y1, Y2 ,.

After that, in the latter half of the horizontal erasing period BH, the switch signal SW becomes high level, and the changeover switches 25a, 25b,
Are switched to the second hold circuits 24a, 24b, ..
Therefore, the signals held in the second hold circuits 24a, 24b, ... Are selected by the changeover switches 25a, 25b ,. At this time, the TFT liquid crystal display panel 26 has an even side gate drive circuit 28
The gate drive signal X2 is given from the gate line 1b
TFTba, bb, ... Connected to are turned on. As a result, the capacitors 5 connected to the TFTs ba, bb, ... Are charged to the level of the segment signals Y1, Y2 ,.

Therefore, the liquid crystal elements 4 of the first horizontal scanning line and the second horizontal scanning line are driven for display by the charging voltage of the capacitor 5 during the next horizontal scanning period after the end of the horizontal erasing period. At this time, the charging voltage of the capacitor 5 is gradually discharged. In the horizontal scanning period, the switching circuit
Video signal A of the next scanning line sent from 17a to 17c
C is sampled by the sample circuits 21a, 21b, ... And held in the first hold circuits 23a, 23b ,.

Thereafter, the same operation is repeated, and in each horizontal erasing period BH, the pixels of the odd-numbered gate lines and the even-numbered gate lines of the liquid crystal display panel 26, that is, the capacitors 5, are charged by the video signal for one horizontal scanning line, The liquid crystal element 4 is driven for display based on the charging voltage. As a result,
In the TFT liquid crystal display panel 26, each pixel is charged for each field, and the charge / discharge cycle thereof is 60 Hz.

As the TFT liquid crystal display panel 26, one that can sufficiently charge each pixel is used. For example NTS
In the case of C method, 1H is 63.5 μs, and the horizontal blanking period is 1
It is 0.8 μs, and the pixel signal is charged to 2 scanning lines within this horizontal blanking period, so 5 μs for 1 scanning line.
It is sufficient to use the TFT liquid crystal display panel 26 that can be charged in the s position.

In the above embodiment, the case where the TFT liquid crystal display panel 26 in which the segment lines are derived from the upper direction is used is shown, but the same can be applied to the case where the segment lines are alternately derived from the vertical direction. Is.

[Effects of the Invention] As described in detail above, according to the present invention, in an active matrix type liquid crystal display device, N video signals of one field transmitted by an interlace system are used and the number of scan lines is approximately 2N. When displaying on one liquid crystal display panel, the first sample-holding of the video signal for displaying on the n-th (n is odd or even) scanning line of the liquid crystal display panel
And a second hold circuit for holding the same information as that of the first hold circuit, and the electric charge charged in the first hold circuit is discharged at a first timing within a predetermined period. Since the nth pixel of the liquid crystal display panel is charged and the n + 1th pixel is discharged at the second timing during the predetermined period, the electric charge stored in the second hold circuit is discharged.
Even in the interlace system, line-sequential scanning can be performed, and flicker can be made less noticeable than in the past. Further, since the electric charge is sent to one pixel by one holding circuit, sufficient electric charge can be applied to each pixel.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration of an active matrix type liquid crystal display device according to an embodiment of the present invention, and FIG.
FIG. 4 is a timing chart for explaining the operation of FIG. 1, FIG. 3 is a diagram showing an electrical configuration of a TFT liquid crystal display panel, and FIG. 4 is a block diagram showing a circuit configuration of a conventional active matrix type liquid crystal display device. Fig. 5 and Fig. 4
FIG. 6 is a block diagram showing the configuration of a switching circuit for switching the order of video signals to be input to the liquid crystal display device shown in FIG. 6, FIG. 6 is a diagram showing the color pixel arrangement sequence of the TFT liquid crystal display panel, and FIG. 7 is the operation shown in FIG. It is a timing chart for explaining. 21a, 21b, ... Sample circuit, 22 ... Shift register,
23a, 23b, ... First hold circuit, 24a, 24b ,.
... second hold circuit, 25a, 25b, ... Changeover switch, 26 ... TFT liquid crystal display panel, 27 ... Odd side gate drive circuit, 28 ... Even side gate drive circuit.

Claims (1)

[Scope of utility model registration request] 1. An active matrix type liquid crystal display device for displaying a video signal of N scanning lines of one field transmitted by an interlace system on a liquid crystal display panel having approximately 2N scanning lines. A first hold circuit that samples and holds the video signal to be displayed on the n-th (n is an odd or even) scanning line, and a second hold circuit that holds the same information as the first hold circuit. , The electric charge charged in the first hold circuit is discharged at a first timing in a predetermined period to charge the nth pixel of the liquid crystal display panel, and the n + 1th pixel is generated at a second timing in the predetermined period. And a means for performing line-sequential scanning by discharging the electric charge stored in the second hold circuit to the second pixel. Rix type liquid crystal display device.