JPH06290261A - Image processor - Google Patents

Abstract

PURPOSE:To transfer an optional image area and to perform image processing at a high speed by storing the start point and end point of row addresses and column addresses supplied to an image memory. CONSTITUTION:The image processor equipped with plural image memories 1 for storing video signals converted into digital signals has counters 3 and 4 which generate row address data and column address data indicating data storage locations in the image memories 1. Further, the processor is equipped with a circuit which stores start point address data and end point address data which can optionally be set in advance for the row addresses and column addresses and a circuit which compares the output data of the counters with the end point address data. Although the contents of all the image memories need to be transferred before at the time of image transfer, the addresses are divided into rows and columns and the counters are provided independently to transfer the image of only an optional image area, thereby shortening the image processing time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus equipped with a plurality of image memories.

[0002]

2. Description of the Related Art In recent years, image processing apparatuses have been widely applied to FA fields such as component mounting machines and inspection machines, but with the increase in equipment speed and diversification of image processing data, a plurality of image cameras and image memories are used. Therefore, a means for high speed processing is adopted. The image data stored in the image memory is subjected to various kinds of processing, and when there are a plurality of image memories, the image data is transferred to be separately processed in another image memory. Addition and speeding up of those functions are important issues.

Input and output of image data in conventional image recognition hardware will be briefly described with reference to FIG.

FIG. 5 shows the hardware configuration of a conventional image processing apparatus. In FIG. 5, the camera board 7 A / D-converts the analog signal output from the video camera 8 to output the digital signal 21, and the digital signal output from the image memory 5 is D / A-converted to monitor 9. Or output to. The image memory control circuit 1 has an address 10, a read signal 11 and a write signal 1 to be given to the image memory.
A circuit for generating 2 controls a signal for writing data to the image memory and reading the written data.

The camera board 7 and the image memory control circuit 1 store the image data sent from the camera board 7 in order in the image memory 5 or in the image memory 5 by synchronizing with the synchronizing signal 22. The displayed data can be displayed correctly on the monitor.

Input from the camera 8 and output to the monitor 9 are performed through the video buffer 6, but the data stored in the image memory 5 is usually processed by the CPU 2 in various ways. Need to switch to. In this case, the CPU 13 supplies the address 13, the read signal 14 and the write signal 15 to the image memory.

FIG. 6 shows a circuit configuration for transferring data from the image memory 1 to the image memory 2, which will be described with reference to the timing chart of FIG.

A counter is usually used for the address given to the image memory, and the count is incremented from address 0 in synchronization with a predetermined clock. The counter is an up-counter with a synchronous clear, and the synchronous signal generating circuit 17 gives a synchronous signal 18 to the image memory generating circuit 3 to clear the counter 5 and output the address 0 to the image memory 1. At this time, by giving the read signal 9, the data content DATA0 of the address 0
Is output from the image memory 1. Thereafter, the image data 13 is sequentially output each time the address is counted up.
The output image data appears on the data line of the image memory 2 via the transfer buffers 15 and 16. However, since this data 14 has a delay with respect to the reference clock 20, it is necessary to write to the image memory 2 at the next clock. Must be used. Therefore, the synchronization signal generation circuit 17 is
On the other hand, the synchronization signal 19 is output after sending only one clock. Since the counter 6 lags behind the counter 5 by one clock, by writing the write signal 12 to the image memory 2 at this time, writing can be sequentially performed from DATA0. That is, if the value of the counter is set according to the data amount of the image memory, the transfer from the image memory 1 to the image memory 2 can be easily performed.

[0009]

Since the above method is fixed by hardware in accordance with the data amount of the image memory (data amount for one screen), one image is transferred at a time.
You have to transfer the screen. However, the reason why the image is transferred in the image processing is to analyze a part of the image. Therefore, transferring one screen is a time loss and becomes a problem in speeding up the image processing.

It is an object of the present invention to incorporate an image processing apparatus capable of transferring an arbitrary area of an image memory and performing image processing at a higher speed into various FA devices.

[0011]

An image recognition apparatus of the present invention includes a row address generation counter and a column address generation counter for generating a row address and a column address given to an image memory, and a starting point of each of the row address and the column address. An image processing apparatus comprising a circuit for storing an end point and a circuit for comparing output data of the two types of counters with the end point address.

[0012]

The image recognition apparatus of the present invention can transfer an arbitrary image area by storing the starting point and the ending point of the row address and the column address given to the image memory, and the image processing can be performed at high speed.

[0013]

Embodiments of the present invention will be described with reference to FIGS. 1, 2 and 3.

FIG. 1 is a block diagram showing the configuration of an image memory control circuit in this embodiment, FIG. 2 is a detailed block diagram of the image memory control circuit, and FIG. 3 is a region of the image memory. As shown in FIG. 3, the normal image memory space has a vertical length of 512.
It is configured like a cross 512. So in Figure 1,
The image memory 1 having an address of 512 × 512 = 256K is used. The address 5 given to the image memory 1 is 18 bits, but if it is considered by dividing it into an upper address 9 bits and a lower address 9 bits, it may coincide with the vertical 512 and horizontal 512 address spaces shown in FIG. I understand. Therefore, the upper 9 bits are divided into a V (row) address and the lower 9 bits are divided into an H (column) address, and a counter is used for each. The image memory control circuit 2 of FIG. 1 incorporates a V counter 4 and an H counter 3 for generating a V address and an H address.

FIG. 2 shows V / V of the image memory control circuit of FIG.
3 is a detailed representation of an address generation circuit centered on an H counter. The 9-bit counter 2 for generating the H address counts up according to the reference clock 15, and the H start point storage circuit 4 is a circuit for storing the start point (H0) of the H address. , H counter 2 is loaded with H0. The H end point storage circuit 6 is a circuit for storing the end point (Hn) of the H address, and the comparison circuit 8 outputs a signal when the output value of the H counter becomes equal to Hn, and this signal is the load of the H counter. Used as signal 18. In addition, this signal is FF (flip-flop)
It is shifted one stage by 10 and used as a clock 16 (VCLK) of the V counter 1 for V address generation. The V start point storage circuit 7 is a circuit for storing the start point (V0) of the V address, and when the synchronizing signal is input, the V counter is set to V0.
To load. The V end point storage circuit 8 is a circuit for storing the end point (Vn) of the V address, and the comparison circuit 7 is the V counter 1
It is a circuit which outputs a signal when the output value of Vn becomes equal to Vn. The FF 9 shifts the output signal of the comparison circuit 7 by one stage according to VCLK, and this signal becomes the end signal 17.

Next, the flow of the image transfer processing by the above circuit configuration will be described based on the flowchart shown in FIG.

In step # 1, H0, Hn, V0 and Vn are set in the memory circuits 4, 6, 3 and 5, respectively. In step # 2, whether to transfer the image (Yes),
It is determined whether or not to perform (No). In the case of Yes, the synchronizing signal 14 is input, V0 is loaded in the V counter 1 in step # 3, and H0 is loaded in the H counter 2 in step # 4. In step # 5, output 13 of H counter 2
The comparison circuit 8 determines whether (H0 at the beginning) is equal to Hn. If No, the count is incremented by the reference clock 15. Therefore, this loops until the output of the H counter 2 becomes equal to Hn. Therefore, the V0 address, that is, the address from the column H0 to the column Hn of the V0 row in FIG. 3 is generated. Then, when it becomes equal to Hn (Yes), the process proceeds to the next step # 6. In step # 6, FF
Since VCLK16 is output from 10, V counter 1 is counted up to (V0 + 1). Therefore, in step # 7, the comparison circuit 7 determines whether or not the output 12 of the V counter 1 is equal to Vn. If they are not equal, H0 is reloaded into the H counter 2. Then, by repeating the above operation in step # 5, (V
Addresses in columns 0 to Hn of the (0 + 1) th row are generated.

The output 12 of the V address becomes equal to Vn sometime after the above repetition, and the comparison circuit 7 outputs a signal. However, when the output ends at that moment, the V address 12 becomes an address from V0 to (Vn-1). Since only this is output, in step # 7, it is compared with (Vn + 1). In this embodiment, FF9 is used to set V
This is realized by shifting one stage by CLK16.

As described above, according to this embodiment, the address to the image memory is divided into the H address and the V address, and the H counter and the V counter output the respective values, and the starting point and the ending point of each counter are stored. By providing a circuit that compares the end point and the output of the counter, it is possible to output only the address in the area surrounded by the thick line in FIG. Further, since H0, Hn, V0, and Vn can be set arbitrarily, it is possible to access only an area having an arbitrary size at an arbitrary position. Therefore, two image memories having this address output circuit are used and the same setting is made. Then, as in the conventional example, by synchronizing the two image memories and operating the read signal and the write signal, the image transfer in an arbitrary area can be performed.

[0020]

According to the image processing apparatus of the present invention, conventionally, all the image memories (for one screen) are used when performing image transfer.
However, by dividing the address into rows and columns and independently providing a counter, it is possible to transfer an image only in an arbitrary image area, and the image processing time can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram showing an image memory and an image memory control circuit configuration in an image processing apparatus of the present invention.

FIG. 2 is a block diagram showing a detailed configuration of an image memory control circuit in the image processing apparatus.

FIG. 3 is an explanatory diagram of an area of an image memory in the image processing apparatus.

FIG. 4 is a flowchart showing an operation of an image memory control circuit in the image processing apparatus.

FIG. 5 is a block diagram showing the configuration of a conventional image processing apparatus.

FIG. 6 is a block diagram showing a configuration of a conventional image transfer circuit.

FIG. 7 is a flowchart of the operation of the image transfer circuit.

[Explanation of symbols]

 1 image memory 2 image memory control circuit 3 column counter 4 row counter 5 address signal 6 read signal 7 write signal 8 synchronization signal 9 clock 201, 202 counter 203 V start point storage circuit 204 H start point storage circuit 205 V end point storage circuit 206 H end point Storage circuit 207, 208 Comparison circuit 209, 210 Flip-flop 211 OR gate 212 Upper address 213 Lower address 214 Sync signal 215 Clock 216 VCLK 217 End signal 218 Load signal 501 Image memory control circuit 502 CPU 503 Video buffer 504 CPU buffer 505 Image memory 506 Video buffer 507 Camera board 508 Camera 509 Monitor 510, 513, 516 Address signal 511, 514, 517 Read signal 512, 512 515,518 Write signal 519,520,521 Data signal 522 Sync signal 601,602 Image memory 603,604 Image memory control circuit 605,606 Internal counter 607,608 Address signal 609,610 Read signal 611,612 Write signal 613,614 Data signal 615, 616 Transfer buffer 617 Synchronous signal generation circuit 618, 619 Synchronous signal 620 Clock

Claims (1)

[Claims] 1. An image processing apparatus comprising a plurality of image memories for storing video signals converted into digital signals, wherein row address data and column address data indicating a data storage location in the image memory with respect to the image memory. And a circuit for storing start point address data and end point address data capable of setting arbitrary values of the row address and the column address in advance, and comparing the output data of the counter with the end point address data. An image processing apparatus comprising a circuit.