JPH0591403A - Image data transfer device - Google Patents

Abstract

(57) [Abstract] [PROBLEMS] To provide a transfer device capable of clipping a necessary processing area from image data and transferring it to a memory in the processing device without temporarily storing the image data of the effective area in a dedicated memory. A horizontal and vertical direction starting point counters 21 and 22 triggered by horizontal and vertical synchronizing signals HS * and VS *, respectively, and horizontal and vertical width counters 23 and 24 respectively triggered by the counters are registers. A predetermined preset signal is loaded from the circuit 3, and valid signals HEN * and VEN * having a time width corresponding to the processing area are loaded.
To occur. The image data selection circuit 1 is controlled by these valid signals and outputs only the image data in the processing area to the memory in the processing device. Counters 23, 2
4 further supplies a processing area column signal and a row signal to the frame memory address output circuit 4, which in turn supplies a memory address signal based on the supplied column and row signals and the offset address signal FAOFA from the register circuit 3. FA
Is supplied to the processing device, the memory AD is addressed by the signal AD, and the data from the selection circuit 1 is stored.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image data transfer apparatus, and more particularly to clipping a necessary area of image data into a clipping, that is, a rectangle, and storing the image data of the clipped necessary area in a frame memory in a processing apparatus. The present invention relates to an image data transfer device for processing.

[0002]

2. Description of the Related Art A conventional image data transfer device will be described by taking the NTSC system as an example. Image data in an input signal region (about 760 × 760 to 950 × 950 pixels) as schematically shown in FIG. The image data of the effective image area (about 512 × 512 pixels) transferred to the above and actually displayed on the display screen in the input signal area is stored in the dedicated image memory and then clipped in the effective image area. Image data of the processing area you want to process
It is configured to read out from the dedicated image memory, store it in a frame memory included in a processing device such as a CPU, and execute processing of image data in the stored processing area.

[0003]

In the conventional image data transfer apparatus thus constructed, a dedicated memory for storing the image data of the effective area is required, and the dedicated memory is temporarily stored in this way. It is necessary to transfer the image data in the processing area to a frame memory such as a CPU after the image data is stored in memory, which requires a large-capacity memory, and it takes time to process the image data in the processing area. Had problems. The present invention has been made in order to solve such a problem, does not require a dedicated memory, and shortens the required processing time,
It is an object of the present invention to provide a clipping image data transfer device capable of performing image processing in near real time.

[0004]

In order to solve the above-mentioned object, the image data transfer apparatus of the present invention comprises a. Image data selection means having a switching gate for inputting image data and selectively outputting the image data, b. The horizontal and vertical valid signals, which are triggered by the horizontal and vertical synchronization signals and have a time width corresponding to the horizontal and vertical start points and the end points of the processing area, are supplied to the switching gates as control signals. When the effective signals are output together, the switching gate is turned on, and during the period when these effective signals are output, the row and column numbers of the pixels in the processing area are set with the starting point of the processing area as the origin. Effective signal / matrix signal generating means for sequentially outputting the processing region row and column signals shown, c. Data from the processing device is stored, and based on the stored data, horizontal and vertical direction starting point signals of the processing region and horizontal and vertical direction width signals are supplied to the effective signal / matrix signal generating means and processed. Register means for generating an offset address signal representing a starting address value for storing the image data of the starting point pixel of the area in the frame memory, d.
A frame memory address generating unit for generating an address signal of a frame memory based on an offset address signal and a processing region row and column signal is provided, and a predetermined processing region of input image data is clipped by the transfer device, Synchronizing the image data of the processing area and the address signal of the frame memory storing the image data,
Moreover, it is characterized in that it can be transmitted to the processing device in almost real time.

[0005]

Embodiments of the present invention will be described below with reference to the drawings. In the drawings, * represents negative logic. FIG. 1 shows a schematic block diagram of an embodiment of the present invention. In the figure, 1 is an image data selection circuit for selectively outputting image data, and 2 is the image data selection circuit 1.
And a processing area matrix signal generating circuit for generating a processing area row and column signal having a starting point of the processing area as an origin, and a processing device (not shown) such as a CPU. ), A predetermined preset signal is supplied to the signal generating circuit 2, and an offset address signal indicating a leading address for storing the image data of the clipped processing area in the frame memory in the CPU is supplied. A register circuit for supplying 4 is a frame for generating an address signal of a frame memory based on an offset address signal from the register circuit 3 and a processing area row and column signal from the effective signal / processing area matrix signal generating circuit 2. The memory address generation circuit 5 supplies a clock signal of a predetermined timing to the circuits 1, 2 and 4. A timing generating circuit.
Note that these circuits 1 to 5 are preferably configured as one IC chip.

The image data selection circuit 1 is composed of D-flip-flops (DF / F) 11 to 13, an LTE / GTE comparator 14, and an output selection circuit 15 having a switching gate. D-
Image input data I for each pixel supplied to the F / F 11
D and the field identification input signal FLDI are DF / F
12 is supplied to the output selection circuit 15 and the on / off state of the switching gate of the output selection circuit 15 is switched based on the valid signal from the signal generation circuit 2 to output an image after clipping, that is, only in the processing region. The data OD and the field identification output signal FLDO are output. The two-stage connected D-F / Fs 11 and 12 are used in consideration of the signal delay in the effective signal / processing area matrix signal generation circuit 2 and the frame memory address generation circuit 4.
This is to synchronize the supply of the image data and the valid signal to the output selection circuit 15 and to output the image data and the frame memory address signal from the address selection circuit 4 in synchronization. Further, in the case of the non-interlaced method, it goes without saying that the field identification signal is not input / output.

The comparator 14 is supplied with the upper limit comparison signal LTE and the lower limit comparison signal GTE representing the upper limit comparison level and the lower limit comparison level for comparison from the register circuit 3, and these signals and the image data from the D-F / F 11 are supplied. The signal is compared. When the image data signal is equal to or higher than the lower limit comparison signal GTE, the lower limit comparison result signal G is sent via the D-F / F 13.
TEA = 1 is supplied to the output selection circuit 15. On the other hand, if the image data signal is less than or equal to the upper limit comparison signal LTE, DF
The upper limit comparison result signal LTEA = 1 is supplied to the output selection circuit 15 via / F13. When the mode designated by the register circuit 3 is the comparison result output mode, the output selection circuit 1
5 outputs the comparison result according to the values of LTEA and GTEA.

Effective signal / processing area matrix signal generation circuit 2
Is composed of horizontal and vertical direction starting point counters 21 and 22, and horizontal and vertical direction width counters 23 and 24 connected to the counters, respectively. The horizontal synchronizing signal HS * from the image data input bus, vertical Sync signal VS *
Respectively, as a trigger signal, the starting point counter 21,
22 is supplied. Further, the counters 21 and 22 are respectively provided with a horizontal direction start point signal HOFS and a vertical direction start point signal VOFS representing the column number and the row number of the pixel at the start point of the processing area, and the width counters 23 and 24 are respectively provided. , A horizontal width signal HWID and a vertical width signal VWID representing the number of pixels in the horizontal and vertical directions in the processing area
Is supplied from the register circuit 3 as a preset signal.

Horizontal and vertical width counters 23, 24
Supplies to the output selection circuit 15 of the image data selection circuit 1 horizontal and vertical direction enable signals HEN * and VEN * representing whether the image data is in the processing area as control signals. , 24 are triggered when the horizontal and vertical direction start point counters 21 and 22 detect the start point of the processing area, and the width signal H is started from the trigger point.
During the time width defined by WID and VWID, signal HEN
The signal levels of * and VEN * are inverted, and when both are at the inverted level, the switching gate of the output selection circuit 15 is turned on. Further, the width counters 23 and 24 are
The frame memory address generation circuit 3 is supplied with a processing area column signal and a processing area row signal in which pixels in the processing area are renumbered with the horizontal and vertical start points of the processing area as origins. These counters 21 to 24 are triggered as described above and count the clock of the cycle described below from the timing signal generation circuit 4 up to (or from) the preset value.

The register circuit 3 is supplied with a write signal WR *, a chip enable signal CE *, an address signal AD, and a data signal DB from the CPU via the CPU bus. Under the signals CE * and WR *, the address signal AD is supplied. Is addressed and a predetermined data signal DB is stored. The data signal DB includes signals GTE and LTE supplied to the comparator 14 of the image data selection circuit 1 and each counter 2 of the effective signal / processing area matrix signal generation circuit 2.
Signals HOFS, HWID, VOF supplied to 1-24
S, VWID are included, and further, an offset address signal FAOFS indicating a start address of a frame memory (in the CPU) for storing image data is included. The signal FAOFS is supplied to the frame memory address generation circuit 4.

The frame memory address generation circuit 4 includes an adder circuit 41 and a multiplexer 4 as shown in FIG.
2 and a strobe generating circuit 43, and an adding circuit 4
1, the offset address signal FAOFS from the register circuit 3 and the processing area row signal from the counter 24 are added, and the added signal is added to the high-order address signal HFA.
In addition, the processing area column signal from the counter 23 is used as the low-order address signal LFA, and these are multiplexed by the multiplexer 42.
And the frame address signal FA is output. Further, the high-order address strobe signal HFAS * is supplied from the strobe generating circuit 43 to the CPU when the high-order address signal is output.

The timing generating circuit 5 includes a frequency dividing circuit, and a clock CLK having the same cycle as the transmission cycle of image data for each pixel is supplied from the image data input bus.
Further, the enable signal IDEN * for controlling whether or not the input of the image data is received is supplied from the CPU bus. When enabled by signal IDEN *,
A clock having the same cycle as the clock CLK is supplied to the D-F / F 11 to 13 of the image data selection circuit 1 to sequentially update the image data in pixel units, and the effective signal / processing area matrix signal generation circuit 2 in the horizontal direction. The clock is also supplied to the start point and width counters 21 and 23. Further, the circuit 5 divides the clock CLK to generate a divided clock having the same cycle as the horizontal synchronizing signal HS *, which is used for the vertical start point and width counters 22 and 24 of the signal generating circuit 2. And the frame memory address generation circuit 4 to determine the switching timing of the high-order address signal and the low-order address signal, and the generation timing of the high-order address strobe signal HFAS *.

The main operation of the image data transfer circuit configured as described above will be described below with reference to the timing diagrams of FIGS. 3A to 3I and the image pixel layout diagram shown in FIG. Explained. In the following, the image data corresponding to the pixel (i, j) [i is the pixel row number and j is the pixel column number] is denoted by D _(i , _j) , and the processing area is four pixels (I, _j) . J), (I, J + N), (I
+ M, J), (I + M, J + N), so that the value I is the vertical start point signal VOFS from the CPU and the value J is the horizontal start point signal HOFS from the CPU.
However, the value M as the vertical width signal VWID and the value N as the horizontal width signal HWID are already stored in the register circuit 3, and these values are stored in the respective counters 21 to 2.
4 has been supplied.

When the enable signal IDEN * is inverted to the low level and the image data transfer device becomes operable, as shown in FIG. 3 (B) in synchronization with the rising edge of the clock CLK shown in FIG. 3 (A). Image data is sequentially D-
The data is taken into the F / F 11, is stored in the D-F / F 12 at the next rising edge of the clock, and is supplied to the output selection circuit 15.

The horizontal synchronizing signal HS * (FIG. 3) supplied after the enable signal IDEN * is inverted at a low level.
(D)), the start point counter 2
1 is triggered, and starts counting down from the value J each time the clock CLK is input from the timing generation circuit 5. When the value of the counter 21 becomes zero, the counter triggers the horizontal width counter 23 in the subsequent stage in synchronization with the next clock. As a result, the horizontal direction valid signal HEN * from the counter 23 is inverted from the high level to the low level as shown in FIG. 3 (F), and the counter 23 counts the clock signal CLK from the timing generation circuit 5. Start from scratch. When the counter 23 counts up to the value N, the signal HEN * is inverted to the high level again. The above operation is repeated each time the horizontal synchronizing signal HS * arrives.

On the other hand, the vertical starting point counter 22 is
Vertical sync signal VS * from the image data input bus (see FIG.
(C)) It is triggered by the rising edge of (C)) and counts down from the value I each time the divided clock (the same frequency as the horizontal synchronization signal HS *) from the timing generation circuit 5 arrives, but outputs until the count value becomes zero. 3 is not flipped, and therefore the vertical width counter 24 is not triggered,
As shown in (E), the horizontal direction effective signal VEN *, which is its output, remains at the high level. Therefore, the signal HEN
Output selection circuit 1 even when * is inverted to low level
The switching gate of No. 5 is kept in the off state, as shown in FIG.
No image data is output as shown in (G).

When the count value of the counter 22 becomes equal to zero, the counter 24 is triggered in synchronization with the next clock, and the valid signal VEN is output as shown in FIG. 3 (E ').
* Becomes low level at that time, and with it, counter 2
4 starts counting the divided clock from the timing generation circuit 41. While the signal VEN * is at the low level and the signal HEN * from the counter 23 is at the low level, the switching gate of the output selection circuit 15 is turned on, as shown in FIG. The selected input image data ID is selected as shown in FIG.
5 to the CPU via the image data output bus. Then, when the count value of the counter 24 becomes equal to the preset value N, the signal VEN * is returned to the high level, but thereafter, even if the valid signal HEN * is inverted to the low level, the image data is not output.

Further, as described above, the width direction counter 2
3 and 24 are respectively counted by the frame memory address generation circuit 4 (0 in the counter 23).
To N, 0 to M in the counter 24) are sequentially supplied as a processing region column signal and a processing region row signal, and the adder circuit 41
High-order address signal HFA from (offset address F
The added value of the AOFS and the processing area row signal) and the low-order address signal LFA (processing area column signal) are supplied to the multiplexer 4
It is switched by 2 and output. The multiplexer 42
The switching operation in is controlled by a divided clock (that is, a signal synchronized with the horizontal synchronizing signal HS *) from the timing generation circuit 5, and as shown in FIG. 3 (H '), one clock cycle from the rising edge of the divided clock. During this period, the high-order address signal HFA _I is output, and in synchronization with this, the high-order address strobe signal H shown in FIG.
FAS * is output from the strobe generating circuit 43. C
In the PU, the high-order address signals are latched at the trailing edge of the strobe signal HFAS *, and subsequently the low-order address signals LFA _{0 to} LF are sequentially input in synchronization with the clock.
In combination with A _N (FIG. 3 (H ′)), addressing of the frame memory is executed.

Therefore, for example, when the bus for transmitting the address signal FA is composed of 12 bits, the high-order address HFA is transmitted during the horizontal blanking period, and the low-order address LFA is sequentially transmitted during the output of the valid signal. Therefore, each of the high-order address signal and the low-order address signal can be 12 bits, so that a total of 24 bits of the address signal can be supplied to the memory of the CPU.

The frame memory is addressed by this frame memory address, and the address signal FA
Is output in synchronization with the image data corresponding to the pixels in the processing area each time it is output from the output selection circuit 15, so that the high-order address (low-order address is zero) defined by the offset address signal FAOFS is the first. As a result, the image data in the processing area is D _(I , _J) D _(I , _{J + 1)} ... D _(I , _{J + N)} by the address defined by the high-order address = (FAOFS + M) and the low-order address = N. D _{(I + 1} , _J) D _{(I + 1} , _{J + 1)} … D _{(I + 1} , _{J + N)} ……… D _{(I + M} , _J) D _{(I + M} , _{J + 1)} … It will be stored in the order of D _{(I + M} , _{J + N)} .

[0021]

Since the present invention is configured as described above, the necessary processing area can be clipped from the image data and transferred to the processing device such as the CPU in almost real time without passing through the dedicated memory. Therefore, it is possible to obtain the effect of speeding up the processing of the clipped image data. Further, since the high-order address signal and the low-order address signal are switched and output, the address signal having a large number of bits can be transmitted even if the number of bits of the address signal transmission bus is small.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing an embodiment of an image data transfer device of the present invention.

FIG. 2 is a block diagram showing an internal configuration of a frame memory address selection circuit provided in the embodiment shown in FIG.

3A to 3I are timing waveform diagrams for explaining the operation of the embodiment shown in FIG.

FIG. 4 is a pixel arrangement diagram schematically showing a relationship between an input signal area, an effective image area, a processing area, and a pixel arrangement in one frame or an odd (even) field.

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[Procedure amendment]

[Submission date] September 21, 1992

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Correction target item name] All drawings

[Correction method] Change

[Correction content]

[Fig. 2]

[Figure 1]

[Figure 3]

[Figure 4]

Claims (3)

[Claims] 1. An image data transfer apparatus for clipping a predetermined processing area of image data and transferring the image data of the processing area to store in a predetermined address area of a frame memory in the processing apparatus. Image data selection means having a switching gate for selectively outputting the image data, triggered by horizontal and vertical synchronization signals, and corresponding to start and end points in the horizontal and vertical directions of the processing area The horizontal and vertical direction effective signals of the time width are supplied to the switching gate as a control signal to turn on the switching gate when both the horizontal and vertical effective signals are output, and these effective signals are output. The processing area that represents the row and column number of the pixel in the processing area with the starting point of the processing area as the origin during the period Effective signal / matrix signal generating means for sequentially outputting a column signal and a column signal, data stored from the processing device, and based on the stored data, horizontal and vertical direction start point signals of the processing region, and horizontal and vertical direction signals. Register means for supplying a width signal to the effective signal / matrix signal generating means and for generating an offset address signal representing a start address value for storing the image data of the starting point pixel of the processing area in the frame memory, the offset address signal and An image data transfer device comprising a frame memory address generating means for generating an address signal of a frame memory based on a processing area row and column signal. 2. The image data transfer device according to claim 1, wherein the frame memory address generating means adds an offset address signal and a processing area row signal, and the obtained addition signal is used as a high-order address signal and processed. A multiplexer circuit for switching the area column signal as a low-order address signal and outputting the low-order address signal, and a strobe generation circuit for outputting a strobe signal for distinguishing the high-address signal from the low-order address signal at the time of outputting the high-address signal An image data transfer device characterized by: 3. The image data transfer apparatus according to claim 1, wherein the effective signal / matrix signal generating means comprises: first and second counters triggered by horizontal and vertical synchronization signals; and the first and second counters. Each of which is triggered by the count-up output of the above and outputs a horizontal and vertical direction valid signal, and outputs a processing area row and column signal, the first and third counters respectively comprising: The horizontal start point and the width signal from the register means are respectively supplied as preset signals to count clocks having a cycle that matches the image data transmission cycle, and the second and fourth counters are arranged in the vertical direction from the register means. The start point and width signals are respectively supplied as preset signals so that clocks with a cycle that matches the cycle of the horizontal synchronization signal are counted. Image data transfer device, characterized in that have been made.