JPH06291267A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To provide a method of controlling a response time, a current amount, and the like of an internal circuit constituted by MOS transistors and raise the degree of freedom of a design in a semiconductor integrated circuit formed by MOS transistors. CONSTITUTION:This embodiment comprises a 4-step inverter formed with P channel MOS transistors 1 to 4 and N channel MOS transistors 5 to 8 and is constituted as a delay circuit in response to an input signal 101 and an output signal 102. Here, substrate electric potentials of the P channel MOS transistors 1 to 4 and N channel MOS transistors 5 to 8 are controlled and set at an optional electric potential, respectively, whereby a response time, a current amount, and the like of these P channel MOS transistors and N channel MOS transistors can be controlled and regulated and also the degree of freedom of a circuit design is enhanced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, it relates to a semiconductor integrated circuit configured by using MOS transistors.

[0002]

2. Description of the Related Art A conventional semiconductor integrated circuit using MOS transistors has an N-channel MOS circuit shown in FIG. 3A as shown in FIG. 3A and FIG.
In the case of the transistor 13, the potential of the substrate B is fixed to the source or GND (may be a negative potential as in the dynamic RAM) and used, and FIG.
In the case of the P-channel MOS transistor 14 of, the potential of the substrate B is generally fixed to the source or V _DD (power supply potential) before use.

[0003]

DISCLOSURE OF THE INVENTION The conventional MOS described above
In a semiconductor integrated circuit configured using transistors, for example, in an inverter formed by using a P-channel MOS transistor and an N-channel MOS transistor, a NAND circuit and a NOR circuit, the response time t _PD and the power are The response time t _PD and power of the MOS transistor are regulated by the process conditions, circuit configuration (load capacitance and resistance, etc.), usage conditions, etc. when the MOS transistor is diffused.

Therefore, for example, when there is a predetermined requirement for the response time t _PD, the P-channel MOS transistor and the N-channel MOS transistor forming the circuit are optimized in design corresponding to their ratio or threshold voltage. Or increasing the transistor size of the P-channel MOS transistor and the N-channel MOS transistor to improve the performance of these MOS transistors, the response time t _PD is shortened. .

When it is desired to reduce the required power, an optimization design corresponding to the ratio or threshold voltage of the P-channel MOS transistor and the N-channel MOS transistor is performed, or a countermeasure for the response time t _PD . On the contrary, there is a drawback that there is only a countermeasure for reducing the power by reducing the transistor size of these MOS transistors and lowering the performance.

[0006]

A semiconductor integrated circuit according to the present invention is a semiconductor integrated circuit composed of MOS transistors, and at least one or more MOS transistors have a common or independent potential level commonly or independently. It is characterized by including a power supply means for supplying a substrate potential.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention. As shown in FIG. 1, in this embodiment,
An input signal 101 and an output signal 102 are generated by a four-stage inverter formed using P channel MOS transistors 1 to 4 and N channel MOS transistors 5 to 8.
A delay circuit corresponding to is constructed. The substrate potential of the P-channel MOS transistors 1 to 4 forming these inverters is supplied with the voltage output from the voltage generation circuit (1) 10 whose output voltage is controlled by the control circuit (1) 9. The substrate potentials of the N-channel MOS transistors 5 to 8 are supplied with the voltage output from the voltage generation circuit (2) 12 whose output voltage is controlled by the control circuit (2) 11.

Now, receiving the control signal of the control circuit (1) 9,
The output voltage level of the voltage generation circuit (1) 10 is set to a voltage slightly lower than the V _DD level, and the control circuit (2)
It is assumed that the output voltage level of the voltage generating circuit (2) 12 is set to a voltage slightly higher than the GND level in response to the control signal of 11. In such a state, when the input signal 101 changes from the "L" level to the "H" level, the output signal 102 also changes from the "L" level to the "H" level. Channel MOS
The depletion layer generated immediately below the channel at the time of switching the transistors 1 to 4 and the N channel MOS transistors 5 to 8 is because the substrate potentials of the P channel MOS transistors 1 to 4 and the N channel MOS transistors 5 to 8 are V _DD and GND. It spreads more than at one time, which causes a faster response time due to the increased movement of the carrier, and also an increase in the amount of current flowing. Also,
The same applies when the input signal 101 changes from "H" level to "L" level.

Further, contrary to the above case, the control circuit (1)
In response to the control signal of 9, the output voltage level of the voltage generation circuit (1) 10 is set to a voltage slightly higher than the _VDD level, and the voltage generation circuit receives the control signal of the control circuit (2) 11 to generate the voltage. When the output voltage level of the circuit (2) 12 is set to a voltage slightly lower than the GND level, and the input signal 101 changes from the “L” level to the “H” level, the output signal 102 also changes to “H” level. The L level changes to the “H” level. At this time, however, the depletion layer generated immediately below the channel at the time of switching the P channel MOS transistors 1 to 4 and the N channel MOS transistors 5 to 8 is opposite to the above case. Since the carrier is slightly narrow, the carrier movement is reduced, the response time is delayed, and the amount of current flowing is reduced.

Even when it is desired to change the threshold voltage of the inverter or NAND circuit and NOR circuit during the circuit operation of the semiconductor integrated circuit using the MOS transistor by using the above phenomenon, the substrate potential of the MOS transistor can be changed. Can be easily realized by using a voltage generating circuit and a control circuit corresponding to the voltage generating circuit, and the degree of freedom in design is increased.

Next, a second embodiment of the present invention will be described. FIG. 2 is a circuit diagram showing the present embodiment, in which an input signal 101 and an output signal 102 are dealt with by a four-stage inverter formed using P channel MOS transistors 1 to 4 and N channel MOS transistors 5 to 8. The input first stage circuit is configured. 2, the substrate voltage of the P-channel MOS transistor 1 forming the first stage inverter is supplied with the output voltage of the voltage generation circuit (1) 10 whose output voltage is controlled by the control circuit (1) 9.
Substrates of P-channel MOS transistors 2, 3 and 4 forming the inverters of the third, fourth and fourth stages are respectively connected to the sources and supplied with the power supply voltage V _DD . In addition, N-channel MOS transistors 5, 7 and 8 forming the first-stage, third-stage and fourth-stage inverters
Of the N-channel M, which are connected to the sources and are supplied with the GND level to form the second-stage inverter.
The substrate potential of the OS transistor 6 is supplied with the voltage output from the voltage generation circuit (2) 12 whose output voltage is controlled by the control circuit (2) 11.

Now, receiving the control signal of the control circuit (1) 9,
The output voltage level of the voltage generation circuit (1) 10 is set to a voltage slightly higher than the _VDD level, and the control circuit (2)
It is assumed that the output voltage level of the voltage generation circuit (2) 12 is set to a voltage slightly lower than the GND level in response to the control signal of 11. In such a state, the input signal 101 is at the TTL level (“H” level = 2.4V,
Even when input at "L" level = 0.8 V), the output signal 102 changes with the amplitudes of the _VDD level and the GND level. That is, the P-channel MOS transistor 1
By controlling the substrate potentials of the N-channel MOS transistor 6 and the N-channel MOS transistor 6, the threshold voltage of the first-stage inverter formed by the P-channel MOS transistor 1 and the N-channel MOS transistor 5 is set to a low value. The threshold voltage of the second-stage inverter formed by the MOS transistor 2 and the N-channel MOS transistor 6 is set to a high value, whereby a semiconductor integrated circuit capable of handling an TTL level input signal. The circuit design of the circuit can be performed.

[0014]

As described above, the present invention provides a MOS
Applied to a semiconductor integrated circuit composed of transistors, a voltage generation circuit capable of supplying an arbitrary voltage commonly or independently to the substrate potential of the MOS transistor, and a control circuit for controlling the output voltage of the voltage generation circuit By including the above, it is possible to suppress the response time, the power (current amount), the threshold voltage, and the like in the semiconductor integrated circuit, and it is possible to increase the degree of freedom in design.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a diagram showing electrode connection of a MOS transistor in a conventional example.

[Explanation of symbols]

 1-4 P-channel MOS transistor 5-8 N-channel MOS transistor 9 Control circuit (1) 10 Voltage generation circuit (1) 11 Control circuit (2) 12 Voltage generation circuit (2)

Claims (1)

[Claims] 1. A semiconductor integrated circuit composed of MOS transistors, comprising power supply means for supplying a substrate potential of an arbitrary potential level to a substrate of at least one or more MOS transistors in common or independently. A characteristic semiconductor integrated circuit.