JPH06292016A - Picture processing unit - Google Patents

Abstract

(57) [Summary] [Purpose] Tone image data is converted into black and white binary image data at high speed. [Arrangement] An image memory for storing an original image and a result image, a constant register 33 for storing a constant for comparison in a binarization process, and arithmetic logic between the constant register 33 and the original image in the image memory. An arithmetic circuit 34 capable of performing arithmetic operations to select and output arithmetic results and carry information, status information such as zero display information, and a thinning circuit 35 for thinning out the status information output from the arithmetic circuit 34 are provided. By writing the thinned data in the image memory, the binarization processing of the gradation image is performed at high speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of document image processing, and more particularly to an image processing apparatus for binarizing a gradation image at high speed.

[0002]

2. Description of the Related Art In recent years, processing of image data by computers has become popular. Image data is input to a computer by a dedicated scanner, a fax machine, or the like. At the input section, one pixel is treated as gradation data, for example, by expressing it in 8 bits, and C
In order to be easily processed by the PU, a process of converting a pixel into a monochrome binary image in which 1 pixel is represented by 1 bit is required.

A concrete binarization process is, for example, as shown in FIG. FIG. 8A is a gradation image of 1-bit 8-bit, and each pixel is represented by a numerical value of 0-255.
(B) and (c) are binary images in which one pixel is 1 bit after binarizing the gradation image of (a). (B) is (a)
Each pixel is compared with a constant 128, and a pixel larger or equal to this constant is represented as 1, and a smaller pixel is represented as 0. Similarly, (c) is compared with the constant 128,
Pixels that are equal to this constant are expressed as 1, and pixels that are not equal are expressed as 0. In FIG. 8, the image is described as having a size of 5 × 5 for simplification of description, but it goes without saying that the vertical and horizontal sizes are usually arbitrarily specified.

The binarization process is performed in the process of converting a source image into a destination image, as shown in FIG. The source image is the SORG which is the start position of the memory.
And the width SWD of the entire source area and the start position SORG are X
It is defined by the upper left coordinate SP of the source image when represented by (0, 0) of the Y coordinate and the size SNx, SNy of the source image. Similarly, the destination image is defined by the head position DORG of the memory, the horizontal width DWD of the entire area, the upper left coordinate DP of the image, and the image sizes DNx and DNy.

Conventionally, such binarization processing has been performed in FIG.
The image processing apparatus as shown in FIG. In FIG. 10, 1 is an image input device such as a scanner, 2 is an image memory for storing an input gradation image or a binarized image, 3 is a CPU for performing binarization processing, and 4 is a CPU.
Reference numeral 3 is a program memory for storing a program for performing binarization processing. The CPU 3 executes the binarization process of the gradation image stored in the image memory 2 according to the program stored in the program memory 4. 5
Is a bus, which is a path for transferring data and programs.

[0006]

However, in the conventional image processing apparatus, the binarization processing is performed by comparing each pixel with a constant as described with reference to FIG. I had the problem that I couldn't do it.

An object of the present invention is to solve such a conventional problem and to provide an image processing apparatus capable of high-speed binarization processing.

[0008]

In order to achieve the above object, the present invention is capable of performing a comparison operation on a plurality of pixels at a time, the configuration can be changed according to the number of bits constituting one pixel, and the invention can be applied to each pixel. An arithmetic circuit capable of outputting not only the arithmetic result but also state information of the arithmetic result for the most significant bit (MSB), and a thinning circuit for selecting and outputting an arbitrary bit of the output of the arithmetic circuit are provided. There is.

[0009]

According to the present invention, with the above configuration, the arithmetic circuit is caused to perform a comparison operation, for example, subtraction, between the data read from the memory and the constant, and the status information of the operation result of each pixel, for example, carry information or zero display. Information such as information is sent to each pixel MS
By outputting to B, selecting only the bit corresponding to, for example, MSB of each pixel in this information by a thinning circuit, and collecting only the thinned information consisting of only 0s and 1s, binarization is performed at high speed. Processing can be performed.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of the entire image processing apparatus that performs binarization processing according to an embodiment of the present invention. In FIG. 1, 11 is an image input device, 12 is an image memory for storing input gradation images and binarized images, and 13 is a CPU. 14 is CP
U13 is a program memory that stores a program for performing processing, and 15 is an image processing device that performs binarization processing in accordance with instructions from the CPU 13. CPU 13 is bus 1
The image processing device 15 is controlled via 6 and the image processing device 15 reads out the contents of the image memory 12 via the bus 17 and binarizes the result. Write to.

FIG. 2 shows the configuration of the image processing apparatus 15. In FIG. 2, 16 and 17 are the buses described in FIG. Reference numeral 18 is a control unit that interprets instructions from the CPU 13 given from the bus 16, and 19 is an image processing unit that actually performs binarization processing, and is controlled by the control unit 18. Reference numeral 20 is an input / output control unit. The image processing unit 19 uses the internal bus 21.
The gradation image data is input from the input / output control unit 20 via the, and the processing result, that is, the binary image data is sent to the input / output control unit 20 via the internal bus 22, and the image is sent via the bus 17. Write to the memory 12.

The CPU 13 shown in FIG. 1 uses the definition information of the processed image described in FIG. 9 and the type of binarization, here, the information of which result (b) or (c) of FIG. 8 is obtained, and comparison. A constant to be given is given to the image processing device 15, and the image processing device 15 is activated, whereby the control unit 18 interprets the given information and controls the image processing unit 19 to automatically perform the binarization processing. Do.

Next, the processing in the image processing unit 19 will be described with reference to FIG.
Will be described in detail. Here, the bit number of one word of image data to be processed will be described as 32 bits. Therefore, the bus width is all 32 bits. In FIG.
Reference numeral 31 is a source image address generation circuit that automatically generates a read address of the source image. Reference numeral 32 is a source image data register that holds the source image data (gradation image) read by the input / output control device 20 in accordance with the address designated by the address generation circuit 31.
The content of the address generation circuit 31 is updated every time one word (32 bits) of the source image is read. Reference numeral 33 is a constant register for storing a constant for comparison in the binarization process. 34 is a data register 32 and a constant register 33
4 is an arithmetic circuit for performing an arithmetic operation, and the types of arithmetic operations are 16 kinds of logical operations from the top to the 16th, and three kinds of arithmetic operations thereunder, as shown in FIG. Figure 4
In, the ADDSR in the bottom column is an operation of right shifting by 1 bit after arithmetic addition, and the type of data to be shifted to the most significant bit can be selected.

The type of data shifted to the above-mentioned most significant bit will be concretely described with reference to FIG. FIG. 5A is a diagram for explaining the function of the most significant bit (MSB) of the arithmetic circuit 34, and is a portion for selecting information to be output as a result of the arithmetic operation. Bit position represents MSB as 0,
It is assumed to increase by 1 in the direction of the least significant bit (LSB). When 1 pixel is 8 bits, i is
There are four types: 0, 8, 16, 24. In the figure, f (i) is the data of the calculation result. CF (i), VF (i), ZF
(I) is status information indicating the state of the operation result, and carry information (carry), overflow information,
This is zero display information. Any one of f, CF, VF, and ZF is selected according to the value of the control information CTL (i), and is output as the calculation result F (i). It is possible to control which information is selected in all calculations. FIG. 5B shows M
This is an output selection part for each bit other than SB. That is,
For operations other than ADDSR, the operation result f of that bit
(J) is selected, and in the operation of ADDSR, the operation information of the bit one bit higher than that bit is selected and output as the operation result F (j).
Controlled by (j). Possible values of j are 0 to 31.
Is a value other than i.

The arithmetic circuit 34 has the number of bits constituting one pixel (hereinafter, referred to as a pixel mode. That is, when the pixel mode is 8, it means that the number of bits constituting one pixel is 8 bits). The configuration changes accordingly. FIG. 6 shows a change in the configuration corresponding to the pixel mode. FIG. 6A shows the case where the pixel mode is 32, and 3
A 2-bit operation is performed. (B) has a pixel mode of 1
In the case of No. 6, two types of operations of upper 16 bits and lower 16 bits of 32-bit data are independently performed.
That is, carry information from the lower 16 bits is not propagated. (C) shows the case where the pixel mode is 8, the 32-bit data is divided into four in 8-bit units, and each operation is independently performed. (D) shows the case where the pixel mode is 4, in which 32-bit data is divided into 8 in 4-bit units, and the calculation is independently performed. As described above, the arithmetic circuit 34 is divided according to the pixel mode, the status information is generated as the arithmetic result for each of the divided arithmetic circuits, and the MSBs of the arithmetic circuits are divided.
The output part of is as shown in FIG. The output selection portion of the remaining bits other than the MSB of each arithmetic circuit is as shown in (b).

As described above, the arithmetic circuit 34 can perform the operation selected from the operations shown in FIG. 4, output the result, and select and output the status information from the MSB. Then, in the binarization process, a process of selecting status information is performed. Specifically, in order to obtain the result of FIG. 8B, carry information CF (i) is selected from the MSB of each arithmetic circuit, and in order to obtain the result of FIG. 8C, The zero display information ZF (i) is controlled to be selected from the MSB of each arithmetic circuit.

In FIG. 3, reference numeral 35 is a thinning circuit,
This is a part for thinning out the data received from the arithmetic circuit 34. The thinning rate is 1 / (pixel mode). For example, when the pixel mode is 8, as shown in FIG.
The thinning process of 8 is executed, and the most significant bit (MSB) of each arithmetic circuit is selected. In FIG. 7, 39 is an output of the arithmetic circuit 34, and status information is selected and output to MSBs F0, F8, F16, and F24 in 8-bit units. This data is the thinning circuit 3
The thinning processing is performed in 5, and as a result, only status information like 40 is selected and output. In the decimation circuit 35, the data from the arithmetic circuit 34 is processed until the decimation result reaches 32 bits or the last data is processed, and it is connected to the already existing decimation result 40, and when either condition is reached. , The result is output.

Such a thinning circuit 35 can be realized by an information compression circuit as disclosed in, for example, Japanese Patent Laid-Open No. 60-084072. This information compression circuit has a structure in which information selection circuits are relatively regularly arranged in each element of the matrix,
This circuit is controlled by a control signal according to the thinning rate, and can select and output any bit of the input information. The operation of the thinning circuit 35 of the present device can be realized by operating the control signal of this device by setting only the bit corresponding to the MSB of each pixel to 1 and to the other bits to 0.

In FIG. 3, reference numeral 36 denotes an arithmetic circuit for performing an arithmetic operation between the data output from the thinning circuit 35 and the output of the destination image data register 37. The kind of the arithmetic operation is for simplification of explanation. Arithmetic circuit 34
Same as. Reference numeral 38 denotes a destination image address generation circuit that generates an address of the destination image in the image memory. Address generation circuit 3
The contents of the image memory designated by 8 are read and then stored in the data register 37. Thereafter, the arithmetic circuit 36 causes the contents of the data register 37 and the thinning circuit 3
The specified operation is performed with the output of 5. The result is written to the address designated by the address generation circuit 38. The contents of the address generation circuit 38 are updated when the reading and writing are completed. With this function, it becomes possible to perform an operation between the value already stored in the image memory and the processing result of this device.

[0020]

As described above, according to the present invention, a plurality of pixels can be compared and calculated at a time, the configuration can be changed according to the number of bits constituting one pixel, and the most significant bit (MSB) corresponding to each pixel can be changed. ), A gradation circuit is provided with an arithmetic circuit capable of outputting status information of the arithmetic result in addition to the arithmetic result, and a thinning circuit for selecting and outputting any bit of the output of the arithmetic circuit. The binarization processing of can be performed at high speed.

[Brief description of drawings]

FIG. 1 is a block diagram of an entire image processing apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram of an image processing apparatus in the embodiment.

FIG. 3 is a detailed block diagram of an image processing unit of the image processing apparatus in the embodiment.

FIG. 4 is a list diagram showing types of calculations in a calculation circuit in the embodiment.

FIG. 5 is a schematic diagram for explaining the operation of the arithmetic circuit in the embodiment.

FIG. 6 is a schematic diagram for explaining a configuration of an arithmetic circuit in the embodiment.

FIG. 7 is a schematic diagram for explaining the operation of the thinning circuit in the embodiment.

FIG. 8 is a schematic diagram for explaining a process of binarizing a gradation image.

FIG. 9 is a schematic diagram for explaining applying binarization processing to a region.

FIG. 10 is a block diagram of an entire image processing apparatus in a conventional example.

[Explanation of symbols]

 11 image input device 12 image memory 13 CPU 14 program memory 15 image processing device 16, 17 bus 18 control unit 19 image processing unit 20 input / output control unit 21, 22 internal bus 31 source image address generation circuit 32 source image data register 33 constant register 34 arithmetic circuit 35 thinning circuit 36 arithmetic circuit 37 destination image data register 38 destination image address generation circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Akio Uesugi 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Chika Onodera 1006 Kadoma, Kadoma City, Osaka Matsushita Electric Sangyo Co., Ltd.

Claims (1)

[Claims] 1. A plurality of pixels can be compared and operated at a time, the configuration can be changed according to the number of bits constituting one pixel, and the most significant bit (MSB) corresponding to each pixel can be operated in addition to the operation result. An image processing apparatus comprising: an arithmetic circuit capable of outputting the resulting state information; and a thinning circuit for selecting and outputting an arbitrary bit of the output of the arithmetic circuit.