JPH06292101A - TV receiver - Google Patents

Abstract

(57) [Summary] [Object] The present invention determines whether or not a vertical synchronizing signal has a predetermined waveform obtained from a video signal, and does not cancel mute when it is not the predetermined waveform obtained from a video signal. An object of the present invention is to provide a television receiver that can be used. According to the present invention, a display control circuit having a vertical cycle counter and a horizontal cycle counter for controlling video display, a sync separation circuit for extracting a vertical sync signal and a horizontal sync signal, and a count value of the vertical cycle counter are provided. In a television receiver equipped with an audio mute circuit that mutes the display period control signal and the vertical synchronizing signal that are asynchronous with each other, a timing signal and a vertical synchronizing signal immediately after the end of the vertical synchronizing signal. OR circuit 21 to which is input
And the latch circuits 13 and 22 to which the output of the OR circuit 21 is input to the reset terminal, and the latch circuits 13 and 22.
The output of the flip-flop 14 is inputted through the inverter circuit 23 and outputs the mute signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a television receiver having an improved audio mute circuit.

[0002]

2. Description of the Related Art FIG. 4 is a circuit diagram showing an overall configuration of a liquid crystal TV (television) receiver. That is, the radio wave received by the antenna 11 is supplied to the tuner 12. The tuner 12 selects a designated channel according to the tuning signal and converts it into an intermediate frequency signal. The intermediate frequency signal output from the tuner 12 is sent to the TV linear circuit 13. The TV linear circuit 13 is composed of an intermediate frequency amplification circuit, a video detection circuit, a video amplification circuit, an AFT detection circuit, and the like. The TV linear circuit 13 amplifies the intermediate frequency signal from the tuner 12 and detects an image by the video detection circuit. Then, an audio signal is extracted from the output signal of the video detection circuit and sent to the audio circuit 14. The audio circuit 14 is composed of an audio detection circuit and an audio amplification circuit. The signal from the TV linear circuit 13 is audio-detected and converted into a low frequency signal, and then the audio is amplified and the speaker 1 is amplified.
Drive 5

The output signal of the video detection circuit in the TV linear circuit 13 is amplified by the video amplification circuit and then sent to the chroma circuit 16 and the sync separation circuit 17. The sync separation circuit 17 separates the horizontal and vertical sync signals included in the video signal and outputs the composite sync signal C-SYNC.
To the tuning control circuit 18 and the horizontal synchronizing signal H-SY.
The NC and the vertical synchronization signal V-SYNC are output to the timing control circuit 19. Also, the TV linear circuit 13 is
The output signal of the intermediate frequency amplifier circuit is A by the AFT detection circuit.
FT detection is performed to extract an S-shaped AFT signal and output to the tuning control circuit 18. The tuning control circuit 18 is provided with key inputs such as tuning setting data and tuning up / down instructions from the key input unit 20. The tuning control circuit 18 creates a tuning signal based on the operation of the tuning up / down key in the key input unit 20 and the AFT signal from the TV linear circuit 13 and outputs it to the tuner 12.

The audio mute circuit 181 determines the reception electric field state based on the presence / absence of the composite sync signal C-SYNC input from the sync separation circuit 17, and outputs a mute signal MUTE to the audio circuit 14. The audio circuit 14 stops the output operation while the mute signal MUTE is given.

The timing control circuit 19 creates a sampling signal φs based on the horizontal and vertical sync signals sent from the sync separation circuit 17 and creates the A / D conversion circuit 2.
Output to 1. The A / D conversion circuit 21 samples the chroma signal output from the chroma circuit 16 in synchronization with the sampling signal φs, converts it into digital data of 3 to 4 bits, and outputs it to the segment driver 23. Further, the timing control circuit 19 creates a timing signal for display control based on the synchronization signal given from the synchronization separation circuit 17, and controls the operation of the segment driver 23 and the common driver 24. The common driver 24 generates a scanning signal according to the timing signal from the timing control circuit 19 and sequentially drives the common electrodes of the LC (liquid crystal) panel 22. The segment driver 23 sequentially reads the 3- to 4-bit video data supplied from the A / D conversion circuit 21 in accordance with the timing signal from the timing control circuit 19, reads the video data for one line, and then reads the video data. Accordingly, a gradation signal is created and the segment electrodes of the LC panel 22 are driven for display.
FIG. 5 is a circuit diagram showing a conventional audio mute circuit. That is, the composite synchronizing signal C is applied to one input terminal of the OR circuit 11.
A vertical synchronizing signal CKV obtained by synchronously separating Sync by the synchronous separating means is input, and the other input terminal of the OR circuit 11 is controlled by the display period control using the count value of the vertical cycle counter of the display controlling means. The signal ECB is input. The output signal of the OR circuit 11 is the NAND circuits 12, 1
3 is input to the set terminal of the set / reset latch circuit, and the reset signal ECE generated by the vertical cycle counter is input to the reset terminal of the latch circuit. The output signal of the latch circuit is the flip-flop 14
The flip-flop 14 is latched at the rising edge of the display start signal DOUT produced by the vertical cycle counter input to the control terminal CK, and the mute signal MUTE is taken out from the output terminal. Therefore, as shown in FIG. 7, the NAND circuits 12 and 13 are
The output (point A) of the latch circuit is a reset signal EC
It is reset ("L" level) when E becomes "L" level (low level), and set "H" when both the display period control signal ECB and the vertical synchronizing signal CKV become "L" level.
The result is input to the input terminal I of the flip-flop 14, the flip-flop 14 is latched at the rising edge of the display start signal DOUT, and the output terminal mutes the mute signal MUTE (“M” at the “L” level). State) is taken out. Therefore, the phase comparison between the display period control signal ECB and the vertical synchronization signal CKV is performed, and if they are synchronized (normal electric field state in FIG. 7A), the mute signal MUTE is at “H” level, and the mute is released. , Asynchronous state (weak electric field state in FIG. 7B), the mute signal MUTE becomes “L” level, and the mute signal operates.

FIG. 6 shows a vertical sync signal CKV by the sync separation means.
It is a circuit diagram which shows the circuit which acquires. That is, the composite sync signal C
-Sync is converted into an integral waveform by an LPF (low pass filter) 33 and input to a non-inverting terminal of a comparator 34, and a power supply voltage V _DD is applied to an inverting terminal of the comparator 34.
Is divided by resistors 31 and 32, and the set voltage value is input. The vertical synchronizing signal CKV is extracted from the comparator 34 when a waveform satisfying the set voltage value input to the inverting terminal is input to the non-inverting terminal.

[0007]

Therefore, if the vertical synchronizing signal CKV extracted from the comparator 34 is synchronized with the display period control signal ECB, the composite synchronizing signal C-Syn.
Even if it is not c, the mute is released. There is a sound signal as a signal having the same cycle as the display period control signal ECB, and in this case, there is a drawback that mute is not applied.

The present invention has been made in view of the above situation, and it is determined whether the vertical synchronizing signal has a predetermined waveform obtained from the video signal, and if it is not the predetermined waveform obtained from the video signal, An object of the present invention is to provide a television receiver that can prevent mute release.

[0009]

In order to solve the above-mentioned problems, the present invention extracts a vertical control signal and a horizontal control signal, and display control means having a vertical period counter and a horizontal period counter for controlling image display. In a television receiver including a sync separation means and an audio mute means for muting the display period control signal created by using the count value of the vertical cycle counter and the vertical sync signal asynchronously, The mute means is in a mute state when the timing signal immediately after the end of the vertical sync signal and the phase of the vertical sync signal are in phase with each other.

The present invention further includes a display control means having a vertical cycle counter and a horizontal cycle counter for controlling image display, a sync separation means for extracting a vertical sync signal and a horizontal sync signal, and a count for the vertical cycle counter. In a television receiver provided with a sound mute means for muting the display period control signal generated by using the value and the vertical sync signal asynchronously, the sound mute means is provided immediately after the end of the vertical sync signal. If the later timing signal and the vertical synchronizing signal are in phase with each other and the horizontal display period signal and the horizontal synchronizing signal are not in sync with each other, the mute state is set.

[0011]

According to the present invention, by the above means, the vertical synchronizing signal is a predetermined waveform obtained from the video signal depending on whether or not the timing signal immediately after the vertical synchronizing signal ends and the phase of the vertical synchronizing signal are synchronized. If the timing signal immediately after the end of the vertical sync signal and the phase of the vertical sync signal are synchronized, it is determined that the waveform is not the predetermined waveform obtained from the video signal, and the mute is not released. To do.

[0012]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 3 is a timing chart showing signals of respective portions of FIG. In the figure, CKV is a vertical synchronizing signal, ECB is a display period control signal, ECE is a reset signal, DOUT is a display start signal, VJD is a timing signal immediately after the end of the vertical synchronizing signal, CKH is a horizontal synchronizing signal, and SH is a horizontal signal. Display period signal, A is input signal of flip-flop 14, MU
TE is a mute signal. That is, the television receiver of the present invention includes a display control circuit having a vertical cycle counter and a horizontal cycle counter for controlling video display, a sync separation circuit for extracting a vertical sync signal and a horizontal sync signal, and the vertical cycle counter. It is composed of an audio mute circuit that mutes the phases of the display period control signal generated by using the count value and the vertical synchronizing signal asynchronously. In this audio mute circuit, as shown in FIG. 1, a vertical synchronizing signal CKV obtained by synchronizing and separating the composite synchronizing signal C-Sync at a synchronizing and separating circuit stage is input to one input terminal of an OR circuit 11.
The display period control signal ECB generated by using the count value of the vertical cycle counter of the display control circuit is input to the other input terminal of the OR circuit 11. The output signal of the OR circuit 11 is input to the set terminal of the set / reset latch circuit including the NAND circuits 13 and 22. The timing signal VJD immediately after the vertical synchronizing signal CKV generated by using the count value of the vertical cycle counter of the display control circuit is input to one input terminal of the OR circuit 21, and the other input of the OR circuit 21 is input. The vertical synchronizing signal CKV is input to the terminal. At the reset terminal of the set / reset latch circuit including the NAND circuits 13 and 22, a reset signal ECE generated by a vertical cycle counter and the OR circuit 21 are provided.
Output signal is input. The output signal of the set / reset latch circuit composed of the NAND circuits 13 and 22 is input to the input terminal I of the flip-flop 14 via the inverter circuit 23, and the flip-flop 14 is controlled by the control terminal C.
The mute signal MUTE is taken out from the output terminal by being latched at the rising edge of the display start signal DOUT generated by the vertical cycle counter input to K. Therefore,
Point A in the figure is reset ("L" level) when the reset signal ECE becomes "L" level, and the display period control signal EC
When both B and the vertical synchronizing signal CKV are at "L" level, they are set ("H" level), and the result is input to the input terminal I of the flip-flop 14, and the flip-flop 1
4 is latched at the rising edge of the display start signal DOUT, and the mute signal MUTE (in the mute state at the "L" level) is taken out from the output terminal. Therefore, the display period control signal ECB and the vertical synchronization signal CKV are compared in phase, and if they are in sync, the mute is released, and if they are not in sync, the mute is applied. In this case, if the vertical synchronizing signal CKV is at the “H” level when the timing signal VJD is at the “L” level, the state at the point A in the figure does not change, but the vertical synchronizing signal CKV is at the “L” level. If it is still output with, the point A in the figure is reset (“L”
Level), and the mute signal MUTE output from the flip-flop 14 is in the mute state at the “L” level. The input signal of the flip-flop 14 once becomes the “H” level due to the OR output of the display period control signal ECB and the vertical synchronizing signal CKV, but the output of the flip-flop 14 is latched at the rising edge of the display start signal DOUT. It does not change.

FIG. 2 is a circuit diagram showing another embodiment of the present invention, and FIG. 3 is a timing chart showing signals of respective parts of FIG. That is, as shown in FIG. 2, the audio mute circuit has a composite sync signal C at one input terminal of the OR circuit 11.
A vertical synchronizing signal CKV obtained by synchronously separating Sync by a synchronous separating circuit is input, and the other input terminal of the OR circuit 11 is controlled by a display period control using the count value of the vertical cycle counter of the display control circuit. The signal ECB is input. The output signal of the OR circuit 11 is the NAND circuits 13 and 4
It is input to the set terminal of the set / reset latch circuit consisting of two. The timing signal VJD immediately after the vertical synchronizing signal CKV generated by using the count value of the vertical cycle counter of the display control circuit is input to one input terminal of the OR circuit 21, and the other input of the OR circuit 21 is input. The vertical synchronizing signal CKV is input to the terminal. The horizontal display period signal SH made by using the count value of the horizontal cycle counter of the display control circuit is input to one input terminal of the OR circuit 41, and the composite synchronizing signal C- is input to the other input terminal of the OR circuit 41. A horizontal synchronizing signal CKH obtained by synchronizing and separating Sync with a synchronizing separation circuit is input. The NAND circuit 1
The reset signal ECE generated by the vertical cycle counter and the output signals of the OR circuits 21 and 41 are input to the reset terminal of the set / reset latch circuit composed of 3, 42. The output signal of the set / reset latch circuit composed of the NAND circuits 13 and 42 is the inverter circuit 2
3 is input to the input terminal I of the flip-flop 14, and the flip-flop 14 is input to the control terminal CK.
It is latched at the rising edge of T, and the mute signal MUTE is taken out from the output terminal. Therefore, point A in the figure is reset (“L” level) when the reset signal ECE becomes “L” level, and set (“H” level) when both the display period control signal ECB and the vertical synchronization signal CKV become “L” level. And the result is flip-flop 1
4 is input to the input terminal I of the flip-flop 14
Is latched at the rising edge of the display start signal DOUT, and the mute signal MUTE (in the mute state at the "L" level) is taken out from the output terminal. Therefore, the display period control signal ECB and the vertical synchronization signal CKV are compared in phase, and if they are in sync, the mute is released, and if they are not in sync, the mute is applied. In this case, if the vertical synchronizing signal CKV is at the “H” level when the timing signal VJD is at the “L” level, the state at the point A in the figure does not change, but the vertical synchronizing signal CKV is at the “L” level. If it is still output, the point A in the figure is reset (“L” level), and the mute signal MUTE output from the flip-flop 14 is in the mute state at the “L” level. Further, when the horizontal display period signal SH is at "L" level and the horizontal synchronization signal CKH is at "H" level and the phases are synchronized, the state of the point A in the figure does not change, but the horizontal synchronization signal CKH is If the phase is asynchronous at the "L" level, A in the figure
The points are reset (“L” level), and the mute signal MUTE output from the flip-flop 14 is in the mute state at the “L” level. The flip-flop 14
Input signals of the display period control signal ECB and the vertical synchronization signal C
The output of the flip-flop 14 does not change because the output of the flip-flop 14 is latched at the rising edge of the display start signal DOUT, although it becomes the "H" level once by the OR output of KV.

[0015]

As described above, according to the present invention, the vertical synchronizing signal can be obtained from the video signal depending on whether the timing signal immediately after the vertical synchronizing signal ends and the phase of the vertical synchronizing signal are synchronized. If the timing signal immediately after the end of the vertical sync signal and the phase of the vertical sync signal are synchronized, it is determined that the waveform is not the predetermined waveform obtained from the video signal. It is possible not to release the mute.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing another embodiment of the present invention.

FIG. 3 is a timing chart showing signals of respective parts of FIGS. 1 and 2.

FIG. 4 is a configuration explanatory diagram showing an overall configuration of a liquid crystal television receiver.

FIG. 5 is a circuit diagram showing a conventional audio mute circuit.

FIG. 6 is a circuit diagram showing a circuit for obtaining a vertical synchronization signal CKV.

FIG. 7 is a timing chart showing signals of respective parts of FIG.

[Explanation of symbols]

11, 21, 41 ... OR circuit, 12, 13, 22, 42
... NAND circuit, 14 ... Flip-flop, 23 ... Inverter circuit, 31, 32 ... Resistor, 33 ... Low-pass filter, 34 ... Comparator.

Claims (4)

[Claims] 1. A display control means having a vertical cycle counter and a horizontal cycle counter for controlling image display, a sync separation means for extracting a vertical sync signal and a horizontal sync signal, and a count value of the vertical cycle counter. In a television receiver provided with an audio mute means for muting the created display period control signal and the vertical sync signal in asynchronism with each other, the audio mute means is a timing signal immediately after the end of the vertical sync signal. A television receiver characterized by being in a mute state if the phase of the vertical synchronizing signal is synchronized with the vertical synchronizing signal. 2. A display control circuit having a vertical cycle counter and a horizontal cycle counter for controlling video display, a sync separation circuit for extracting a vertical sync signal and a horizontal sync signal, and a count value of the vertical cycle counter. In a television receiver equipped with an audio mute circuit for muting the produced display period control signal and the vertical synchronizing signal in asynchronism with each other, the timing signal and the vertical synchronizing signal immediately after the end of the vertical synchronizing signal are input. A television receiver comprising: an OR circuit, a latch circuit to which the output of the OR circuit is input to a reset terminal, and a flip-flop that receives the output of the latch circuit and outputs a mute signal. 3. A display control means having a vertical cycle counter and a horizontal cycle counter for controlling image display, a sync separation means for extracting a vertical sync signal and a horizontal sync signal, and a count value of the vertical cycle counter. In a television receiver provided with an audio mute means for muting the created display period control signal and the vertical sync signal in asynchronism with each other, the audio mute means is a timing signal immediately after the end of the vertical sync signal. And a phase of a vertical synchronizing signal is synchronized, and a horizontal display period signal and a horizontal synchronizing signal are in a mute state if they are not synchronized. 4. A display control circuit having a vertical cycle counter and a horizontal cycle counter for controlling video display, a sync separation circuit for extracting a vertical sync signal and a horizontal sync signal, and a count value of the vertical cycle counter. In a television receiver equipped with an audio mute circuit for muting the produced display period control signal and the vertical synchronizing signal in asynchronism with each other, the timing signal and the vertical synchronizing signal immediately after the end of the vertical synchronizing signal are input. A first OR circuit that is
A second OR circuit to which the horizontal display period signal and the horizontal synchronizing signal are input, a latch circuit to which the output of the second OR circuit and the output of the first OR circuit are input to a reset terminal, and the latch circuit And a flip-flop for receiving a mute signal and outputting a mute signal.