JPH0629448A - Lead frame and semiconductor device - Google Patents
Lead frame and semiconductor deviceInfo
- Publication number
- JPH0629448A JPH0629448A JP4257759A JP25775992A JPH0629448A JP H0629448 A JPH0629448 A JP H0629448A JP 4257759 A JP4257759 A JP 4257759A JP 25775992 A JP25775992 A JP 25775992A JP H0629448 A JPH0629448 A JP H0629448A
- Authority
- JP
- Japan
- Prior art keywords
- tab
- hole
- resin
- lead
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/013—Manufacture or treatment of die-attach connectors
- H10W72/01308—Manufacture or treatment of die-attach connectors using permanent auxiliary members, e.g. using alignment marks
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
(57)【要約】
【構成】タブ1に貫通穴2を形成する。貫通穴2はタブ
の減肉部17を素子搭載面側に形成するようにし、これ
が封止樹脂の板厚内での係止部となっている。このタブ
の上面に素子を搭載して樹脂部5にて封止する。
【効果】タブ1と樹脂部5が剥離したときのタブ1下方
の樹脂部5を拘束する距離が短くなるので、水蒸気の圧
力による樹脂部5の応力が低減し、リフロ−クラックを
防止することができる。
(57) [Summary] [Structure] A through hole 2 is formed in the tab 1. The through hole 2 is formed such that the thinned portion 17 of the tab is formed on the element mounting surface side, and this serves as a locking portion within the thickness of the sealing resin. An element is mounted on the upper surface of this tab and sealed with a resin portion 5. [Effect] Since the distance for restraining the resin portion 5 below the tab 1 when the tab 1 and the resin portion 5 are peeled off is reduced, the stress of the resin portion 5 due to the pressure of water vapor is reduced, and reflow cracks are prevented. You can
Description
【0001】[0001]
【産業上の利用分野】本発明はリ−ドフレ−ム及び半導
体装置に係り、特にリフロ−半田付け時の加熱による樹
脂クラック防止に好適なリ−ドフレ−ム及び半導体装置
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame and a semiconductor device, and more particularly to a lead frame and a semiconductor device suitable for preventing resin cracks due to heating during reflow soldering.
【0002】[0002]
【従来の技術】樹脂封止型の半導体装置では従来のピン
挿入タイプに代わり、基板に直接リ−ドを半田付けする
面付け実装タイプが主流になりつつある。このようなパ
ッケ−ジでは、高温高湿環境で保存すると樹脂が水分を
吸収し、半田付け加熱時(リフロ−時)に水分がタブ
(素子搭載部のこと。以下本願において同じ。)と樹脂
部との界面で蒸気になり、タブ下面コ−ナ部にクラック
が生じ易い。このクラックは、半田リフロ−時に発生す
る為、俗にリフロ−クラックと呼ばれている。2. Description of the Related Art In a resin-sealed type semiconductor device, a surface mounting type in which a lead is directly soldered to a substrate is becoming the mainstream instead of the conventional pin insertion type. In such a package, when stored in a high temperature and high humidity environment, the resin absorbs moisture, and when the solder is heated (during reflow), the moisture is a tab (an element mounting portion; the same applies to the present application hereinafter) and a resin. Vapor is generated at the interface with the part, and cracks are likely to occur in the corners on the lower surface of the tab. This crack is commonly called a reflow crack because it occurs during solder reflow.
【0003】このようなリフロ−クラックを防止する従
来技術としては、特開昭60−208847号公報に記
載のようにパッケ−ジの裏面に穴をあけ、発生する蒸気
を逃がす方法がある。As a conventional technique for preventing such reflow cracks, there is a method of making holes on the back surface of the package and allowing the generated vapor to escape, as described in JP-A-60-208847.
【0004】また、樹脂部とタブの界面の接着強さを向
上させ、すきまを防止する技術として、タブの反素子搭
載面(素子搭載側面の裏側に当たる面のこと。以下同
じ。)に凹凸を設ける方法として特開昭58−1995
48号公報、同60−186044号公報に示される技
術、更にタブ相当部に穴を形成したものとして同59−
16357号公報、実開昭60−118252号公報に
記載の技術がある。As a technique for improving the adhesive strength at the interface between the resin portion and the tab and preventing the clearance, the anti-element mounting surface of the tab (the surface that contacts the back surface of the element mounting side surface; the same applies hereinafter) is uneven. As a method for providing, Japanese Patent Laid-Open No. 58-1995
No. 48, No. 60-186044, the same as the technique shown in FIGS.
There are techniques described in Japanese Patent No. 16357 and Japanese Utility Model Laid-Open No. 60-118252.
【0005】[0005]
【発明が解決しようとする課題】上記従来技術のうち、
パッケ−ジ下面に穴をあける方法は、リフロ−クラック
は妨げるもののパッケ−ジ外部と内部に水分の通路を作
ることになり、チップ電極の腐食が生じる可能性があ
る。Of the above-mentioned conventional techniques,
The method of making holes in the lower surface of the package prevents reflow cracks, but creates moisture passages inside and outside the package, which may lead to corrosion of the chip electrodes.
【0006】また、タブの反素子搭載面に単純な凹凸を
設ける方法は、タブと樹脂部との接着面内の変位を拘束
する効果はあるものの、両者を引き離す方向の変位につ
いては、凹部に入り込んだ樹脂部が簡単に抜けるために
効果が期待できない。Further, although the method of providing a simple unevenness on the anti-element mounting surface of the tab has the effect of restraining the displacement in the bonding surface between the tab and the resin portion, the displacement in the direction of separating the tab and The resin part that entered can be easily removed, so no effect can be expected.
【0007】樹脂封止半導体をリフロ−半田付けする際
に、樹脂中に含まれた水分が気化して、この蒸気圧がタ
ブ〜樹脂界面にあるボイド又は非接着部等の空孔作用を
し、タブ−樹脂界面の剥離を進行させる。剥離進行によ
って空孔が大きくなっても、周囲の水分が拡散により供
給され、この結果、空孔の圧力は緩和されず、樹脂部は
変形し、タブ端部の最大応力発生個所を起点にクラック
を生じる(図6のクラック10参照。)。When the resin-sealed semiconductor is reflow-soldered, the water contained in the resin is vaporized, and this vapor pressure acts as a void in the tab-resin interface or a non-bonded portion. , The tab-resin interface is peeled off. Even if the pores become large due to the progress of peeling, the surrounding moisture is supplied by diffusion, as a result, the pressure in the pores is not relaxed, the resin part deforms, and cracks start from the point where the maximum stress occurs at the tab end. (See crack 10 in FIG. 6).
【0008】前記の特開昭59−16357号公報では
タブの一部を抜き去り、この部分に樹脂を充填する技術
が開示されている。この技術を用いて熱応力による剥離
を防ぐとともに、等価的に樹脂部の厚さを増大させるこ
とにより、耐湿性の向上がある程度は図れる。しかし、
リフロ−半田付け時の蒸気圧により、樹脂部がタブから
剥離した場合に生ずる変形により、最大応力発生個所の
応力はタブの一部が抜き去られない場合と大差なく、こ
の構造では、リフロ−半田付けの際の樹脂部割れに対す
る効果は充分ではない。The above-mentioned Japanese Patent Laid-Open No. 59-16357 discloses a technique of removing a part of the tab and filling the part with resin. By using this technique to prevent peeling due to thermal stress and equivalently increase the thickness of the resin portion, the moisture resistance can be improved to some extent. But,
Due to the vapor pressure generated during reflow soldering, the resin part is deformed when it is separated from the tab, and the stress at the point of maximum stress is not much different from when the tab is partially removed. The effect of cracking the resin portion during soldering is not sufficient.
【0009】実開昭60−118252号公報に記載の
技術では封止樹脂を係止する貫通穴として裏面側から表
面側に向かって広くなる構造が示されているが、このよ
うな単純構造では貫通穴の板厚内に確実に樹脂を係止す
ることは難しい。The technique disclosed in Japanese Utility Model Laid-Open No. 60-118252 discloses a structure in which the through hole for locking the sealing resin widens from the back surface side to the front surface side. However, in such a simple structure. It is difficult to securely lock the resin within the plate thickness of the through hole.
【0010】本発明の目的は蒸気圧により生じるリフロ
−クラックを防止することにある。An object of the present invention is to prevent reflow cracks caused by vapor pressure.
【0011】[0011]
【課題を解決するための手段】上記目的は、タブに特殊
な形状の貫通穴を設け、この穴により樹脂部をタブに拘
束し、リフロ−クラックが生じるタブ下面コ−ナ部の樹
脂部に発生する応力を低減することにより達成される。The above object is to provide a through hole having a special shape in the tab, and the resin portion is constrained to the tab by this hole so that the resin portion of the lower corner portion of the tab where reflow crack occurs This is achieved by reducing the stress generated.
【0012】リフロ−半田付けの際の樹脂クラックを防
ぐには、樹脂部とタブが剥離しても、タブ端の最大応力
発生個所に大きな応力が生じないようにする必要があ
る。この要求は、樹脂部とタブに付着力がなくなった場
合でも、樹脂部の変形を防ぎ得る構造、すなわち樹脂部
が蒸気圧によりタブから抜け出ない係止構造にすること
により達成できる。In order to prevent resin cracks during reflow soldering, it is necessary to prevent a large stress from being generated at the maximum stress generating portion at the tab end even if the resin portion and the tab are separated. This requirement can be achieved by a structure that can prevent the deformation of the resin portion even when the adhesive force between the resin portion and the tab is lost, that is, a locking structure in which the resin portion does not come out of the tab due to vapor pressure.
【0013】本願第1番目のリ−ドフレ−ムの発明は、
半導体素子を搭載するタブと、タブの周辺にてタブと一
体に接続したリ−ド群とからなるリ−ドフレ−ムにおい
て、タブ全面の内、少なくとも半導体素子が搭載される
部位直下に貫通穴を形成し、かつ貫通穴はタブの板厚内
で封止樹脂が抜け出ぬようにくびれ、または段付きの係
止部を形成していることを特徴とする。The invention of the first lead frame of the present application is as follows.
In a lead frame including a tab on which a semiconductor element is mounted and a lead group integrally connected to the tab around the tab, a through hole is formed at least just under the portion where the semiconductor element is mounted on the entire tab surface. And the through hole is formed with a constricted portion or a stepped portion so that the sealing resin does not escape within the thickness of the tab.
【0014】本願第2番目の半導体装置の発明は、半導
体素子と、半導体素子を搭載するタブと、タブの周辺に
配置したリ−ド群と、リ−ド群の内のインナ−リ−ド部
及びタブ並びに半導体素子を封止する樹脂部とを備えた
半導体装置において、タブ全面の内、少なくとも半導体
素子が搭載される部位直下に貫通穴を形成し、かつ貫通
穴はタブの板厚内で封止樹脂が抜け出ぬようにくびれ、
または段付きの係止部を形成していることを特徴とす
る。A second semiconductor device invention of the present application is to provide a semiconductor element, a tab for mounting the semiconductor element, a lead group arranged around the tab, and an inner lead of the lead group. In a semiconductor device including a portion, a tab, and a resin portion that seals the semiconductor element, a through hole is formed at least immediately below a portion where the semiconductor element is mounted on the entire tab surface, and the through hole is within the tab thickness. So that the sealing resin does not come out,
Alternatively, it is characterized in that a stepped locking portion is formed.
【0015】本願第3番目の半導体装置の発明は、半導
体素子と、半導体素子を搭載するタブと、タブの周辺に
配置したリ−ド群と、リ−ド群の内のインナ−リ−ド部
及びタブ並びに半導体素子を封止する樹脂部とを備えた
半導体装置において、タブ全面の内、少なくとも半導体
素子が搭載される部位直下に貫通穴を形成し、かつ貫通
穴はタブの板厚内で封止樹脂が抜け出ぬように係止部を
形成し、アウタ−リ−ド端部は基板に対し面付けされた
面付け実装タイプであることを特徴とする。A third semiconductor device invention of the present application is a semiconductor device, a tab on which the semiconductor device is mounted, a lead group arranged around the tab, and an inner lead of the lead group. In a semiconductor device including a portion, a tab, and a resin portion that seals the semiconductor element, a through hole is formed at least immediately below a portion where the semiconductor element is mounted on the entire tab surface, and the through hole is within the tab thickness. The locking portion is formed so that the sealing resin does not come out, and the outer lead end portion is a surface mounting type in which the outer lead end surface is mounted on the substrate.
【0016】この貫通穴は、タブの板厚方向に対して全
体に傾斜している(テ−パ部を有する)態様、タブの板
厚内にくびれ部を形成している態様等が挙げられる。ま
た、タブの少なくとも一箇所に素子搭載面側開口面積が
素子搭載面の裏側面の開口面積よりも大となるような貫
通穴に限られず、板厚内に封止樹脂の一部が確実に係止
されれば有効である。The through hole may be, for example, a mode in which the tab is entirely inclined with respect to the plate thickness direction (having a taper part), a mode in which a constricted part is formed within the plate thickness of the tab, and the like. . Further, the opening area on the element mounting surface side is not limited to at least one portion of the tab that is larger than the opening area on the back side surface of the element mounting surface. It is effective if locked.
【0017】貫通穴の素子搭載面側面積はタブの素子搭
載面側面積の24%以上からタブと素子との接合面積の
80%以下の範囲にあることが望ましく、またタブの素
子搭載面の貫通穴の周囲には溝を設けることが好まし
い。The area of the through hole on the element mounting surface side is preferably in the range of 24% or more of the area on the element mounting surface side of the tab to 80% or less of the bonding area of the tab and the element. It is preferable to provide a groove around the through hole.
【0018】[0018]
【作用】リフロ−クラックが生じるタブ下面コ−ナ部の
樹脂部の応力を概略的に求めるには、タブ下方の樹脂部
を図5に示すように一様の圧力がかかる周辺拘束の長方
形平板にモデル化すれば良い。このとき、最大の応力
は、長辺中央に発生し、その値は次式(数1)で与えら
れる。In order to roughly determine the stress in the resin portion of the bottom corner portion of the tab where reflow cracks occur, the resin portion under the tab is surrounded by a rectangular flat plate to which uniform pressure is applied as shown in FIG. It can be modeled as At this time, the maximum stress occurs in the center of the long side, and the value is given by the following equation (Equation 1).
【0019】[0019]
【数1】 [Equation 1]
【0020】ここで、βは長辺と短辺の長さの比で決ま
る応力係数、aは短辺の長さ、hは板厚、pは水蒸気の
圧力を表わす。(数1)式から明らかなように、タブサ
イズaの2乗で発生応力は増加する。従って素子寸法が
大きくなると、半田リフロ−クラック(図6符号10)
が生じ易くなる。それ故、応力を低減するには、短辺の
長さを短くするか、或いは板厚を厚くすれば良い。Here, β is a stress coefficient determined by the ratio of the length of the long side to the length of the short side, a is the length of the short side, h is the plate thickness, and p is the pressure of water vapor. As is clear from the equation (1), the generated stress increases with the square of the tab size a. Therefore, when the element size becomes large, solder reflow crack (10 in FIG. 6)
Is likely to occur. Therefore, in order to reduce the stress, the length of the short side may be shortened or the plate thickness may be increased.
【0021】ところが、板厚を厚くするということは、
パッケ−ジを厚くすることになり、例えばフラットパッ
ケ−ジのように薄型を特徴とするパッケ−ジには適用で
きない。また、タブの寸法は、チップの寸法より小さく
できないので、チップ寸法により決定される。However, increasing the plate thickness means that
This makes the package thicker, and cannot be applied to a thin package such as a flat package. In addition, the size of the tab cannot be made smaller than the size of the chip, and thus is determined by the chip size.
【0022】そこで本発明では、タブの一部に樹脂拘束
部を設け、タブの剥離部分を分割した。これにより、実
効的なタブ寸法aが小さくなるので、樹脂部の応力が低
減し、樹脂部のリフロ−クラックを防止することができ
る。Therefore, in the present invention, a resin restraining portion is provided on a part of the tab and the peeled portion of the tab is divided. As a result, the effective tab size a is reduced, so that the stress in the resin portion is reduced and reflow cracking of the resin portion can be prevented.
【0023】[0023]
【実施例】以下、本発明のリ−ドフレ−ム及び半導体装
置の実施例をその原理、比較例とともに図面に従って説
明する。Embodiments of the lead frame and semiconductor device of the present invention will now be described with reference to the drawings along with their principles and comparative examples.
【0024】図1は単純なテ−パ状貫通穴付きリ−ドフ
レ−ムの斜視図であり、図2はこれを用いた面付け実装
型半導体装置の断面図である。FIG. 1 is a perspective view of a simple lead frame having a taper-like through hole, and FIG. 2 is a sectional view of a surface-mounting type semiconductor device using the same.
【0025】タブ1はその両端をタブ吊りリ−ド3にて
支吊され、略中央に貫通穴2を形成している。この貫通
穴2は図2の断面からも明らかなように素子4方向に次
第に広がり、素子4とは反対の側に徐々に狭くなってい
る。尚、図2において符号5は樹脂部、6は水蒸気、7
はリ−ド、8は半田、9は基板を示す。Both ends of the tab 1 are suspended by tab suspension leads 3 and a through hole 2 is formed substantially at the center. As is clear from the cross section of FIG. 2, the through hole 2 gradually expands in the direction of the element 4 and gradually narrows on the side opposite to the element 4. In FIG. 2, reference numeral 5 is a resin portion, 6 is water vapor, and 7
Is a lead, 8 is a solder, and 9 is a substrate.
【0026】タブ1と樹脂部5の界面に水蒸気6が発生
し、この圧力により、樹脂部5が膨らんでいる。このと
き、タブ下面コ−ナ部の樹脂部5に応力が発生するが、
本例によるタブ1の貫通穴2が樹脂部5を拘束するの
で、図2と図6(従来図)を比較してわかるように、a
寸法は従来のタブの2分の1以下になる。従って、(数
1)式より発生する応力を4分の1以下に低減すること
ができ、リフロ−クラックが防止できる。ただ本例では
貫通穴内での樹脂の確実な係止拘束には難があり、テ−
パの角度によっては収縮等の影響もあって抜け出てしま
うおそれがある。そこで本発明は以下の工夫を施こし
た。Water vapor 6 is generated at the interface between the tab 1 and the resin portion 5, and the pressure causes the resin portion 5 to swell. At this time, stress is generated in the resin portion 5 of the corner portion of the tab lower surface,
Since the through hole 2 of the tab 1 according to this example restrains the resin portion 5, as shown in a comparison between FIG. 2 and FIG. 6 (conventional view), a
The size is less than half that of conventional tabs. Therefore, the stress generated by the equation (1) can be reduced to a quarter or less, and reflow cracks can be prevented. However, in this example, it is difficult to securely lock and restrain the resin in the through hole, and the tape
Depending on the angle of the pad, there is a risk of contraction and the like, and there is a risk that it will come out. Therefore, the present invention has been devised as follows.
【0027】本発明の第1実施例、第2実施例を図3、
図4に示す。第1実施例では、貫通穴2の反素子搭載面
における面積よりも小さい面積の部分が貫通穴2の内部
に設けられている。また、第2実施例では、貫通穴2が
タブ1に対して斜めに開けられている。タブに対する貫
通穴の傾き角は、概略10°程度でよい。両実施例とも
樹脂部が貫通穴2に入り込んでタブ1に樹脂部が拘束さ
れるので、リフロ−クラックの防止が確実に図れること
になる。The first and second embodiments of the present invention are shown in FIG.
As shown in FIG. In the first embodiment, a portion having an area smaller than the area of the anti-element mounting surface of the through hole 2 is provided inside the through hole 2. Further, in the second embodiment, the through hole 2 is formed obliquely with respect to the tab 1. The inclination angle of the through hole with respect to the tab may be about 10 °. In both of the embodiments, the resin portion enters the through hole 2 and is restrained by the tab 1, so that the reflow crack can be surely prevented.
【0028】本発明の貫通穴の平面形状は、図1から図
3に示すような円形である必要はなく、楕円形、矩形、
十字型でも同様の効果がある。また、貫通穴の数は、タ
ブ1に必要な剛性を損なわない程度に複数個設けること
により、より一層の効果を上げることができる。The planar shape of the through hole of the present invention does not have to be circular as shown in FIGS. 1 to 3, but may be elliptical, rectangular,
The cross shape has the same effect. Further, by providing a plurality of through holes so that the tab 1 does not impair the required rigidity, the effect can be further enhanced.
【0029】貫通穴に入り込んだ樹脂部に生じる応力σ
hは、(数2)式で表わされる。Stress σ generated in the resin portion that has entered the through hole
h is represented by the equation (2).
【0030】[0030]
【数2】 [Equation 2]
【0031】ここで、Atはタブの面積、Ahは穴の内側
の面積の最小値である。この応力が樹脂部の破壊応力σ
Bを超えると、樹脂部が破壊するので、(数3)式、従
って(数4)式が成り立たなくてはならない。Here, A t is the area of the tab and A h is the minimum value of the area inside the hole. This stress is the fracture stress σ of the resin part
If it exceeds B , the resin portion will be destroyed, and therefore the equation (3) and therefore the equation (4) must be established.
【0032】[0032]
【数3】 [Equation 3]
【0033】[0033]
【数4】 [Equation 4]
【0034】通常、半田リフロ−時には、パッケ−ジは
約220℃に加熱され、この温度における水の飽和蒸気
圧は0.24kgf/mm2である。また、この温度に
おける樹脂部の破壊応力は約1kgf/mm2であるか
ら、これらの値を(数4)式に代入すると(数5)式と
なる。Normally, during solder reflow, the package is heated to about 220 ° C., and the saturated vapor pressure of water at this temperature is 0.24 kgf / mm 2 . Further, since the fracture stress of the resin portion at this temperature is about 1 kgf / mm 2 , substituting these values into the equation (4) gives the equation (5).
【0035】[0035]
【数5】 [Equation 5]
【0036】すなわち、穴の最小面積は、タブの面積の
24%以上にすることが望ましい。また貫通穴が過度に
大きくなるとタブの剛性が低下するので、チップ搭載面
に凹凸が生じ、チップとタブとの接合が困難となる。更
にワイヤボンディングの際に、タブの反素子搭載面から
加える熱が、チップに伝わりにくなる。従って貫通穴の
大きさに最適には上限があり、本発明者等の実験確認に
よれば貫通穴の面積は搭載するチップの80%以下が望
ましい。上記穴の範囲は各貫通穴毎にもまた貫通穴の合
計に対しても適用し得る。That is, it is desirable that the minimum area of the holes is 24% or more of the area of the tab. Further, if the through hole is excessively large, the rigidity of the tab is reduced, so that the chip mounting surface becomes uneven, and it becomes difficult to bond the chip and the tab. Further, during wire bonding, the heat applied from the surface of the tab opposite to the element mounting becomes difficult to be transferred to the chip. Therefore, there is an upper limit to the optimum size of the through hole, and according to the experiments and confirmation by the present inventors, the area of the through hole is preferably 80% or less of the mounted chip. The range of holes described above can be applied to each through hole as well as to the total number of through holes.
【0037】次に、本発明による貫通穴の製造方法につ
いて述べる。Next, a method of manufacturing a through hole according to the present invention will be described.
【0038】図7に従来のエッチング技術でタブに貫通
穴をあける方法を示す。タブの両側に同一形状のエッチ
ングパタ−ン14a,14bを密着し、エッチング液1
5の中に浸漬する。エッチングは、タブの両面から進行
するので、図8のように、わずかに中央部が狭い穴があ
く。しかし、従来の方法では、穴の内側の面積がほとん
ど一様なので、樹脂が入り込んでも、これを拘束するに
は至らない。尚、図8の工程の如く両面からのエッチン
グを途中で止めればその処理(エッチングの処理液の濃
度や時間)の程度によってくびれ部を板厚内に形成する
ことも可能となり、本発明の実施例に係るリ−ドフレ−
ムの製造にも流用可能である。FIG. 7 shows a method of forming a through hole in a tab by a conventional etching technique. Etching patterns 14a and 14b of the same shape are adhered to both sides of the tab, and the etching solution 1
Immerse in 5. Since the etching proceeds from both sides of the tab, a hole having a slightly narrow central portion is formed as shown in FIG. However, in the conventional method, since the area inside the hole is almost uniform, even if the resin enters, it cannot be restricted. If the etching from both sides is stopped in the middle as in the process of FIG. 8, it is possible to form the constricted portion within the plate thickness depending on the degree of the treatment (concentration and time of the treatment liquid for etching). Lead frame according to example
It can also be used for the production of aluminum.
【0039】図9に、本発明の第1実施例の貫通穴をあ
ける方法を示す。タブ上面のエッチングパタ−ン14c
の穴は、下面のエッチングパタ−ン14dの穴より大き
い。このような状態でエッチング液15に浸漬すると、
図10のような穴があくので、第1実施例を実現するこ
とができる。FIG. 9 shows a method of forming a through hole according to the first embodiment of the present invention. Etching pattern 14c on top of tab
The holes are larger than the holes in the etching pattern 14d on the lower surface. When immersed in the etching solution 15 in such a state,
Since the holes shown in FIG. 10 are formed, the first embodiment can be realized.
【0040】図11に、本発明の第2実施例の貫通穴を
あける方法を示す。エッチングパタ−ン14e,14f
の穴の大きさは等しいが、位置がずれている。従って、
図12のように、タブに対して斜めにあいた穴、すなわ
ち第2実施例を実現することができる。FIG. 11 shows a method of forming a through hole according to the second embodiment of the present invention. Etching patterns 14e, 14f
The holes have the same size but are out of position. Therefore,
As shown in FIG. 12, it is possible to realize a hole that is oblique to the tab, that is, the second embodiment.
【0041】図13に、プレスにより本発明を実現する
方法を示す。まず、従来の技術により、タブに貫通穴を
開け、この部分に凸型のプレス金型16aをプレスす
る。この方法により、図14に示すように、反素子搭載
面における穴の内側の面積よりも大きな面積の部分を設
けることができる。FIG. 13 shows a method of realizing the present invention by pressing. First, according to a conventional technique, a through hole is formed in the tab, and a convex press die 16a is pressed on this portion. By this method, as shown in FIG. 14, a portion having an area larger than the area inside the hole on the anti-element mounting surface can be provided.
【0042】次に本発明の第3実施例を図15及び図1
6に基づいて説明する。タブの貫通孔はテ−パにはなっ
ていないが素子搭載面は反素子搭載面よりも穴径が大き
い。また本実施例では減肉部17が形成され、これが板
厚内で段付き部となり、封止樹脂を確実に係止してい
る。更に穴は複数設けられている。尚、符号18はダイ
ボンディング材である。Next, a third embodiment of the present invention will be described with reference to FIGS.
6 will be described. The through hole of the tab is not a taper, but the element mounting surface has a larger hole diameter than the non-element mounting surface. Further, in the present embodiment, the thinned portion 17 is formed, and this becomes a stepped portion within the plate thickness to securely lock the sealing resin. Further, a plurality of holes are provided. Reference numeral 18 is a die bonding material.
【0043】図15はタブ1に貫通穴2を設け、かつ、
タブ1上部に減肉部17を設けて段付き部を形成したも
のである。この構造によれば、ダイボンディング材18
が素子4とタブ1の間を完全に埋めていても樹脂部5は
タブ上部に充填される。リフロ−半田付けの際にタブ1
と樹脂部5が剥離しても、タブ上部に充填された樹脂部
の為、樹脂部5はタブ1から抜け出ることはなく、蒸気
圧による変形は図16のようになる。ここで、タブ残存
部の最大幅dを次の式で与えられる値以下にすれば、樹
脂部にクラックは生じない。FIG. 15 shows that the tab 1 is provided with a through hole 2 and
The reduced thickness portion 17 is provided on the upper portion of the tab 1 to form a stepped portion. According to this structure, the die bonding material 18
Although the space between the element 4 and the tab 1 is completely filled with, the resin portion 5 is filled in the upper portion of the tab. Reflow-tab 1 for soldering
Even if the resin part 5 is peeled off, the resin part 5 does not come out of the tab 1 because it is the resin part filled in the upper part of the tab, and the deformation due to the vapor pressure is as shown in FIG. Here, if the maximum width d of the tab remaining portion is set to be equal to or less than the value given by the following equation, no crack is generated in the resin portion.
【0044】[0044]
【数6】 [Equation 6]
【0045】ここで、KICはリフロ−温度における樹脂
の破壊靭性値であり、pはリフロ−時に発生する蒸気圧
である。Here, K IC is the fracture toughness value of the resin at the reflow temperature, and p is the vapor pressure generated during the reflow.
【0046】図17は他の実施例で貫通穴2を上部に広
がる形状としたものを複数形成したもので、これによっ
ても上記と同様の効果が出せる。これらの貫通穴2は円
形でも良いが、矩形に近い形または図18に示すような
長円に近い形の方が補強効果は大である。FIG. 17 shows another embodiment in which a plurality of through holes 2 are formed so as to spread upward and the same effect as above can be obtained. The through holes 2 may be circular, but the reinforcing effect is larger when the shape is close to a rectangle or an ellipse as shown in FIG.
【0047】最後に、本発明を実施する際の問題点とこ
れを解決する方法について述べる。図19は、本発明の
タブ1に素子を接合するため、接着剤18を塗布した状
態を示したものである。図20は、図19の状態の後
に、素子4を搭載し、接合した状態を示す。図に示すよ
うに、接着剤18の量が過多であると、貫通穴2の側面
に接着剤18が流れだす恐れがある。図20の状態で、
接着剤が硬化した後に樹脂部をモ−ルドすると、樹脂部
と接着剤との間に剥離が生じ易く、本発明の効果がなく
なる恐れがある。Finally, a problem in implementing the present invention and a method for solving the problem will be described. FIG. 19 shows a state in which the adhesive 18 is applied to bond the element to the tab 1 of the present invention. FIG. 20 shows a state in which the element 4 is mounted and joined after the state of FIG. As shown in the figure, when the amount of the adhesive 18 is excessive, the adhesive 18 may flow out to the side surface of the through hole 2. In the state of FIG. 20,
If the resin part is molded after the adhesive is cured, peeling between the resin part and the adhesive is likely to occur, and the effect of the present invention may be lost.
【0048】このような問題点を解決するには、図21
に示すように、タブ1の素子搭載面の貫通穴のまわりに
接着剤17の流出防止溝19を設ければ良い。図22
は、接着剤流出防止溝19を設けたタブ1に素子4を搭
載した状態を示す。図に示すように、余分な接着剤は、
溝18に留められるので、貫通穴に流れ出すことはなく
なる。To solve such a problem, FIG.
As shown in FIG. 5, an outflow prevention groove 19 for the adhesive 17 may be provided around the through hole on the element mounting surface of the tab 1. FIG. 22
Shows a state in which the element 4 is mounted on the tab 1 provided with the adhesive outflow prevention groove 19. As shown in the figure, the extra adhesive
Since it is retained in the groove 18, it does not flow out into the through hole.
【0049】[0049]
【発明の効果】本発明によれば、タブと樹脂部が剥離し
たときのタブ下方の樹脂部を拘束する距離が短くなるの
で、水蒸気の圧力による樹脂部の応力が低減し、リフロ
−クラックを防止することができる。According to the present invention, when the tab and the resin portion are separated, the distance for restraining the resin portion under the tab is shortened, so that the stress of the resin portion due to the pressure of water vapor is reduced and reflow cracks are prevented. Can be prevented.
【図1】単純なテ−パ状貫通穴付きリ−ドフレ−ムの斜
視図である。FIG. 1 is a perspective view of a lead frame having a simple taper-shaped through hole.
【図2】図1のリ−ドフレ−ムを用いた面付け実装型半
導体装置の断面図である。FIG. 2 is a cross-sectional view of an imposition mounting type semiconductor device using the lead frame of FIG.
【図3】本発明の実施例に係るリ−ドフレ−ムの断面図
である。FIG. 3 is a cross-sectional view of a lead frame according to an embodiment of the present invention.
【図4】本発明の実施例に係るリ−ドフレ−ムの断面図
である。FIG. 4 is a sectional view of a lead frame according to an embodiment of the present invention.
【図5】リ−ドフレ−ムの応力計算に用いる計算モデル
の斜視図である。FIG. 5 is a perspective view of a calculation model used for the stress calculation of the lead frame.
【図6】従来例に係る半導体装置の断面図である。FIG. 6 is a sectional view of a semiconductor device according to a conventional example.
【図7】従来例に係るリ−ドフレ−ムの貫通穴形成工程
を示す部分断面図である。FIG. 7 is a partial cross-sectional view showing a step of forming a through hole of a lead frame according to a conventional example.
【図8】従来例に係る、或いは板厚内にくびれ部を形成
する場合のリ−ドフレ−ムの貫通穴形成工程を示す部分
断面図である。FIG. 8 is a partial cross-sectional view showing a step of forming a through hole of a lead frame according to a conventional example or when a constricted portion is formed in the plate thickness.
【図9】本発明の実施例に係るリ−ドフレ−ムの貫通穴
形成工程を示す部分断面図である。FIG. 9 is a partial cross-sectional view showing a step of forming a through hole in a lead frame according to an embodiment of the present invention.
【図10】図9の貫通穴形成工程を経て得られるリ−ド
フレ−ムの部分断面図である。10 is a partial cross-sectional view of a lead frame obtained through the through hole forming step of FIG.
【図11】本発明の実施例に係るリ−ドフレ−ムの貫通
穴形成工程を示す部分断面図である。FIG. 11 is a partial cross-sectional view showing a step of forming a through hole in a lead frame according to an embodiment of the present invention.
【図12】図11の貫通穴形成工程を経て得られるリ−
ドフレ−ムの部分断面図である。12 is a reel obtained through the through hole forming process of FIG.
It is a fragmentary sectional view of a dframe.
【図13】本発明の実施例に係るリ−ドフレ−ムの貫通
穴形成工程をプレス金型とともに示した部分断面図であ
る。FIG. 13 is a partial cross-sectional view showing a through-hole forming process of the lead frame according to the embodiment of the present invention together with a press die.
【図14】図12の貫通穴形成工程を経て得られるリ−
ドフレ−ムの部分断面図である。14 is a reel obtained through the through hole forming process of FIG.
It is a fragmentary sectional view of a dframe.
【図15】本発明の実施例に係る半導体装置の断面図で
ある。FIG. 15 is a sectional view of a semiconductor device according to an example of the present invention.
【図16】本発明の実施例に係る半導体装置の断面図で
ある。FIG. 16 is a sectional view of a semiconductor device according to an example of the present invention.
【図17】本発明の実施例に係る半導体装置の断面図で
ある。FIG. 17 is a sectional view of a semiconductor device according to an example of the present invention.
【図18】本発明の実施例に係るリ−ドフレ−ムの斜視
図である。FIG. 18 is a perspective view of a lead frame according to an embodiment of the present invention.
【図19】本発明の実施例に係るリ−ドフレ−ムの貫通
穴形成工程を示す部分断面図である。FIG. 19 is a partial cross-sectional view showing a step of forming a through hole in a lead frame according to an embodiment of the present invention.
【図20】図19の実施例に係るリ−ドフレ−ムに素子
を搭載した状態の断面図である。20 is a cross-sectional view showing a state in which an element is mounted on the lead frame according to the embodiment of FIG.
【図21】本発明の実施例に係るリ−ドフレ−ムの貫通
穴形成工程を示す部分断面図である。FIG. 21 is a partial cross-sectional view showing a step of forming a through hole in a lead frame according to an embodiment of the present invention.
【図22】図21の実施例に係るリ−ドフレ−ムに素子
を搭載した状態の断面図である。22 is a cross-sectional view showing a state in which an element is mounted on the lead frame according to the embodiment of FIG.
1…タブ、2…貫通穴、3…タブ吊りリ−ド、4…素
子、5…樹脂部、6…水蒸気、7…リ−ド、8…半田、
9…基板、18…ダイボンディング材、19…接着剤流
出防止溝。DESCRIPTION OF SYMBOLS 1 ... Tab, 2 ... Through hole, 3 ... Tab suspension lead, 4 ... Element, 5 ... Resin part, 6 ... Water vapor, 7 ... Lead, 8 ... Solder,
9 ... Substrate, 18 ... Die bonding material, 19 ... Adhesive outflow prevention groove.
フロントページの続き (72)発明者 三浦 英生 茨城県土浦市神立町502番地 株式会社日 立製作所機械研究所内 (72)発明者 立道 昭弘 茨城県土浦市神立町502番地 株式会社日 立製作所機械研究所内 (72)発明者 北林 千加子 茨城県土浦市神立町502番地 株式会社日 立製作所機械研究所内 (72)発明者 清水 一男 群馬県高崎市西横手町111番地 株式会社 日立製作所高崎工場内 (72)発明者 初田 俊雄 茨城県土浦市神立町502番地 株式会社日 立製作所機械研究所内 (72)発明者 尾崎 敏範 茨城県土浦市神立町502番地 株式会社日 立製作所機械研究所内 (72)発明者 服部 敏雄 茨城県土浦市神立町502番地 株式会社日 立製作所機械研究所内 (72)発明者 坂田 荘司 茨城県土浦市神立町502番地 株式会社日 立製作所機械研究所内Front page continuation (72) Inventor Hideo Miura 502 Jinritsu-cho Machinery Research Center, Tsuchiura-shi, Ibaraki Machinery Research Laboratories, Ltd. (72) Inventor Akihiro Tachimichi 502 Jinre-machi, Tsuchiura-shi, Ibaraki Machinery Research Laboratories, Hiritsu Manufacturing Co., Ltd. (72) Inventor Chikako Kitabayashi 502 Jinritsucho, Tsuchiura-shi, Ibaraki Machinery Research Laboratory, Hiritsu Manufacturing Co., Ltd. (72) Inventor Kazuo Shimizu 111 Nishiyote-cho, Takasaki-shi, Gunma Hitachi Ltd. Takasaki Plant (72) Invention Toshio Hatsuda, 502 Jinritsucho, Tsuchiura-shi, Ibaraki Machinery Research Laboratory, Hiritsu Manufacturing Co., Ltd. (72) Inventor, Toshinori Ozaki 502, Jinritsucho, Tsuchiura-shi, Ibaraki Machinery Research Laboratory, Hiritsu Manufacturing Co., Ltd. (72) Inventor, Toshio Hattori 502 Jinritsu-cho, Tsuchiura-shi, Ibaraki Machinery Research Laboratory, Hiritsu Seisakusho Co., Ltd. (72) Inventor, Shoji Sakata, 502, Jinre-machi, Tsuchiura-shi, Ibaraki Machinery Research Center, Hiritsu Seisakusho, Ltd.
Claims (3)
辺にて該タブと一体に接続したリ−ド群とからなるリ−
ドフレ−ムにおいて、前記タブ全面の内、少なくとも前
記半導体素子が搭載される部位直下に貫通穴を形成し、
かつ該貫通穴はタブの板厚内で封止樹脂が抜け出ぬよう
にくびれ、または段付きの係止部を形成していることを
特徴とするリ−ドフレ−ム。1. A lead comprising a tab on which a semiconductor element is mounted and a lead group integrally connected to the tab around the tab.
In the dframe, a through hole is formed at least just under the portion where the semiconductor element is mounted, on the entire surface of the tab,
Further, the lead frame is characterized in that the through hole is formed with a constricted portion or a stepped portion so that the sealing resin does not come out within the thickness of the tab.
ブと、該タブの周辺に配置したリ−ド群と、該リ−ド群
の内のインナ−リ−ド部及びタブ並びに前記半導体素子
を封止する樹脂部とを備えた半導体装置において、前記
タブ全面の内、少なくとも前記半導体素子が搭載される
部位直下に貫通穴を形成し、かつ該貫通穴はタブの板厚
内で封止樹脂が抜け出ぬようにくびれ、または段付きの
係止部を形成していることを特徴とする半導体装置。2. A semiconductor element, a tab on which the semiconductor element is mounted, a lead group arranged around the tab, an inner lead portion and a tab of the lead group, and the semiconductor. In a semiconductor device having a resin portion for encapsulating an element, a through hole is formed at least directly under the portion where the semiconductor element is mounted in the entire tab surface, and the through hole is sealed within the tab thickness. A semiconductor device, characterized in that a locking portion having a constriction or a step is formed so that the stop resin does not come out.
ブと、該タブの周辺に配置したリ−ド群と、該リ−ド群
の内のインナ−リ−ド部及びタブ並びに前記半導体素子
を封止する樹脂部とを備えた半導体装置において、前記
タブ全面の内、少なくとも前記半導体素子が搭載される
部位直下に貫通穴を形成し、かつ該貫通穴はタブの板厚
内で封止樹脂が抜け出ぬように係止部を形成し、アウタ
−リ−ド端部は基板に対し面付けされた面付け実装タイ
プであることを特徴とする半導体装置。3. A semiconductor element, a tab on which the semiconductor element is mounted, a lead group arranged around the tab, an inner lead portion and a tab of the lead group, and the semiconductor. In a semiconductor device having a resin portion for encapsulating an element, a through hole is formed at least directly under the portion where the semiconductor element is mounted in the entire tab surface, and the through hole is sealed within the tab thickness. A semiconductor device characterized in that an engaging portion is formed so that the stop resin does not come out, and an outer lead end portion is an imposition mounting type in which the outer lead end is impositioned on a substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4257759A JP2546472B2 (en) | 1992-09-28 | 1992-09-28 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4257759A JP2546472B2 (en) | 1992-09-28 | 1992-09-28 | Semiconductor device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7101905A Division JP2570209B2 (en) | 1995-04-26 | 1995-04-26 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0629448A true JPH0629448A (en) | 1994-02-04 |
| JP2546472B2 JP2546472B2 (en) | 1996-10-23 |
Family
ID=17310706
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4257759A Expired - Lifetime JP2546472B2 (en) | 1992-09-28 | 1992-09-28 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2546472B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6777266B2 (en) * | 1999-04-28 | 2004-08-17 | Siliconware Precision Industries Co., Ltd. | Dual-chip integrated circuit package and method of manufacturing the same |
| JP2004291172A (en) * | 2003-03-27 | 2004-10-21 | Seiko Instruments Inc | Reinforcement and substrate processing method using the reinforcement |
| US7768137B2 (en) | 2003-11-06 | 2010-08-03 | Infineon Technologies Ag | Semiconductor chip with flip chip contacts and a passivation layer with varying thickness portions surrounding contact surfaces of the semiconductor chip |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5253665A (en) * | 1975-10-29 | 1977-04-30 | Hitachi Ltd | Semiconductor device |
| JPS60118252U (en) * | 1984-01-18 | 1985-08-09 | 沖電気工業株式会社 | Lead frame for resin-sealed semiconductor devices |
| JPS60181051U (en) * | 1984-05-14 | 1985-12-02 | 日立電線株式会社 | Structure of lead frame |
-
1992
- 1992-09-28 JP JP4257759A patent/JP2546472B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5253665A (en) * | 1975-10-29 | 1977-04-30 | Hitachi Ltd | Semiconductor device |
| JPS60118252U (en) * | 1984-01-18 | 1985-08-09 | 沖電気工業株式会社 | Lead frame for resin-sealed semiconductor devices |
| JPS60181051U (en) * | 1984-05-14 | 1985-12-02 | 日立電線株式会社 | Structure of lead frame |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6777266B2 (en) * | 1999-04-28 | 2004-08-17 | Siliconware Precision Industries Co., Ltd. | Dual-chip integrated circuit package and method of manufacturing the same |
| JP2004291172A (en) * | 2003-03-27 | 2004-10-21 | Seiko Instruments Inc | Reinforcement and substrate processing method using the reinforcement |
| US7768137B2 (en) | 2003-11-06 | 2010-08-03 | Infineon Technologies Ag | Semiconductor chip with flip chip contacts and a passivation layer with varying thickness portions surrounding contact surfaces of the semiconductor chip |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2546472B2 (en) | 1996-10-23 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |