JPH06295263A - Memory system - Google Patents

Abstract

(57) [Summary] [Object] To realize a computer system with stable processing speed and always high-speed operation by dividing the main memory into a cache memory application area and a non-application area. [Structure] Based on an address for storing data in the main memory 3, the cache memory 2 is divided into an area where it is used and an area where it is not used. Then, when reading frequently used data, the cache memory 2 is used by switching the cache memory use / non-use switching mechanism 6, and when reading frequently used data, the cache memory 2 is not used.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system having a cache memory used for, for example, various monitor display devices and industrial computer devices, and more particularly to a cache system based on an address of data stored in a main memory. The present invention relates to a memory system that decides whether or not to use a memory.

[0002]

2. Description of the Related Art FIG. 4 is a diagram showing a memory system configuration of a conventional computer system described, for example, in "Nikkei Electronics" (June 8, 1992). In FIG. 4, 1 is a CPU, 2 is a cache memory, 3 is a main memory, and 4 is a data bus. In this computer system, a cache memory 2 having a high data access speed is arranged between a CPU 1 and a main memory 3 having a low data access speed.

FIG. 5 is a flow chart for explaining memory access control in a conventional computer system. Next, the operation of this conventional computer system will be described. When there is a data request from the CPU 1, it is determined whether or not this data exists in the cache memory 2 (step S51). If the data exists in the cache memory 2 (hereinafter referred to as cache hit), the CPU 1 reads the data from the cache memory 2 to shorten the data read time (step S52). On the other hand, when the required data does not exist in the cache memory 2, the CPU 1 determines that the main memory 3
More data is read (step S53), and thereafter
The cache memory 2 is updated so that the data hits the cache (step S54).

[0004]

Since the conventional computer system is configured as described above, for example, when data with a low frequency of use is continuously read in the cache memory 2, data that does not exist in the cache memory 2 can be read. Since the reading is continuous and the data reading from the main memory 3 and the updating of the cache memory 2 are continuously performed, there is a problem that the time required for the CPU 1 to read the data increases.

The present invention has been made to solve the above problems, and in a computer system having a cache memory, a mechanism for switching between use and non-use of the cache memory, and an arbitrary area in the main memory are cached. An object of the present invention is to obtain a memory system having a mechanism for setting a cache memory application area that uses memory and a cache memory non-application area that does not use cache memory.

[0006]

The memory system according to the first aspect of the present invention is based on an address value for storing data in the main memory 3, and the main memory is an area that uses a cache memory and an area that does not use a cache memory. Based on the data address value on the main memory used by the CPU, the use / non-use area setting unit (cache memory use area setting unit 8) which performs separate setting and the setting of the use / non-use area setting unit A use / non-use determining unit (cache memory use / non-use determining unit 7) for determining whether to use the cache memory, and the main memory or the cache memory according to an instruction of the use / non-use determining unit. A connection means (cache memory use / non-use switching mechanism 6) for connecting to the CPU is provided. In the memory system according to the second aspect of the present invention, the data area using the cache memory is the variable length area of the main memory,
The use / non-use area setting unit sets the data area not using the cache memory to an area other than the variable length area of the main memory. In the memory system according to the third aspect of the present invention, a setting instruction means (man-machine interface section 30) for instructing the use / non-use area of the cache memory on the main memory by the user to the use / non-use setting section is provided. Provided.

[0007]

In the memory system according to the first aspect of the present invention, first, the use / non-use area setting unit (cache memory use area setting unit 8) determines the main memory based on the address value for storing the data in the main memory. Is divided into areas that use cache memory and areas that do not use cache memory. Next, the use / non-use determining unit (cache memory use / non-use determining unit 8) sets the use / non-use area setting unit, based on the address value of the data on the main memory used by the CPU, It is determined whether to use the cache memory. Finally, by the connection means (cache memory use / non-use switching mechanism 6), according to the instruction of the use / non-use determination unit,
The main memory or cache memory is connected to the CPU. In the memory system according to the second aspect of the present invention, when the main memory is divided into an area using the cache memory and an area not using the cache memory, the data area using the cache memory is a variable length area of the main memory, and the cache memory is The unused data area is an area other than the variable length area of the main memory. In the memory system according to the third aspect of the present invention, the user changes from the setting instruction means (man-machine interface unit 30) to the use / non-use setting unit,
The use / non-use area of the cache memory on the main memory is set.

[0008]

【Example】

Example 1. 1 is a diagram showing the configuration of a computer system according to a first embodiment of the present invention. Incidentally, the same or corresponding parts as those of the conventional example (FIG. 4) are designated by the same reference numerals and the description thereof will be omitted. Reference numeral 5 is a cache memory control unit, 6 is a cache memory use / non-use switching mechanism as a connecting unit, 7 is a cache memory use / non-use determination unit as a use / non-use determination unit, and 8 is a use / non-use area determination unit. Is a cache memory application area setting unit, 101 is a cache memory application area, and 102 is a cache memory non-application area. The CPU 1 uses the cache memory 2,
The cache memory use / non-use switching mechanism 6 for switching the non-use switches the use or non-use of the cache memory. The cache memory use / non-use switching mechanism 6 is controlled by the cache memory control unit 5
By. Then, these settings are easily set using software. For example, if a predetermined symbol (1) is input corresponding to the data displayed on the screen from the keyboard and the cache memory use (0) is input, the cache memory is not used. In this way, the cache memory use / non-use switching mechanism 6
In order to switch between, the use / non-use of the cache memory 2 is determined by the address indicating the location where the data of the main memory 3 is stored. That is, first, the software designer divides the main memory 3 into a plurality of memory areas (fixed length blocks) in advance, and for each of these blocks, the cache memory application area 101 that uses the cache memory 2,
It is selected which of the cache memory non-application areas 102 that does not use the cache memory 2 is used. Then, the cache memory 2 in each of these blocks
The use or non-use of is registered in the cache memory use area setting unit 8. The cache memory use / non-use determination unit 7 controls the cache memory use / non-use switching mechanism 6 according to the setting contents of the cache memory use area setting unit 8. The setting contents of each block in the main memory 3 in the cache memory use area setting unit 8 can be dynamically set. That is, the use / non-use of the cache memory of data in the memory area can be set by the software even while the computer system is operating.
Therefore, for example, when the content of the main memory 3 is rewritten, the cache memory applicable area 101 and the cache memory non-applicable area 102 can be reset.

FIG. 2 is a flow chart showing the operation of memory access control in the memory system of the first embodiment of the present invention. Next, the operation of the memory system of the first embodiment will be described. When there is a data request from the CPU 1, the cache memory use / nonuse determination unit 7
It is determined whether the data read address of the main memory 3 is the cache memory applicable area 101 (step S21).
If this read address is in the cache memory applicable area 101, the data is in the cache memory 2
It is determined whether or not it exists in the cache memory (step S22), and if it exists, the CPU 1 reads the data from the cache memory 2 (step S23).
U1 reads data from the main memory 3 (step S2
4). After that, to make this data hit the cache,
The cache memory 2 is updated (step S25). If the read address is within the cache memory non-applicable area 102, the CPU 1 reads data from the main memory 3 (step S26).

Embodiment 2. FIG. 3 is a diagram showing the configuration of a computer system according to the second embodiment of the present invention. The same or corresponding parts as those of the first embodiment (FIG. 1) are designated by the same reference numerals. In the second embodiment, the variable length area in the main memory 3 is set as the cache memory applicable area 101 that uses the cache memory 2 at the time of reading data, and the other area is set as the cache memory non-applicable area 102 that does not use the cache memory 2. To do. In this way, by designating the start address and the end address of the cache memory application area 101 and setting the cache memory application area 101, an arbitrary capacity of the cache memory application area 101 is set in an arbitrary area in the main memory 3. It is possible to set. The cache memory applicable area 101 is set by the cache memory use area setting unit 8 as in the first embodiment. Cache memory application area 10 in main memory 3 in cache memory use area setting unit 8
1 and the setting contents of the cache memory non-application area 102 can be dynamically set, as in the second embodiment. Further, the memory access control operation in this embodiment follows the flowchart of FIG. 2 as in the first embodiment.

Embodiment 3. In the third embodiment of the present invention, 30
A man-machine interface unit is provided as a setting instruction means of the. From the man-machine interface unit 30, the cache memory use / non-use setting unit 7 freely sets the data on the main memory to those using the cache memory and those not using the cache memory.

[0012]

As described above, according to the first invention, based on the address value for storing the data in the main memory,
The main memory used by the CPU is set according to the use / non-use area setting section for setting the main memory into an area using the cache memory and an area not using the cache memory, and the setting of the use / non-use area setting section. Based on the address value of the data on the memory, the use / non-use determining unit for determining whether to use the cache memory, and the main memory or cache memory and the CPU according to the instruction of the use / non-use determining unit. Since the configuration is provided with the connection means for connecting the and, the number of times data is read from the low-speed main memory is reduced, and a computer system capable of high-speed operation can be realized. According to this second invention,
Since the data area that uses the cache memory is the variable length area of the main memory and the data area that does not use the cache memory is the area other than the variable length area of the main memory, the influence of the used data is small, This has the effect of realizing a computer system with stable speed and capable of always operating at high speed. According to the third invention, since the user can set the used / unused area of the cache memory on the main memory, in addition to the effect of the first invention, it is possible to meet the convenience of the user. Therefore, the main memory can be used without waste.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a memory system according to a first embodiment of the present invention.

2 is a flowchart showing a memory access control operation in the memory system of FIG.

FIG. 3 is a diagram showing a configuration of a memory system according to a second embodiment of the present invention.

FIG. 4 is a diagram showing a configuration of a conventional computer system.

5 is a flowchart showing a memory access control operation of the system of FIG.

[Explanation of symbols]

 1 CPU 2 cache memory 3 main memory 4 data bus 5 cache memory control unit 6 cache memory use / non-use switching mechanism 7 cache memory use / non-use determination unit 8 cache memory use area setting unit 101 cache memory applicable area 102 cache memory non Application area

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[Procedure amendment]

[Submission date] September 6, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0007

[Correction method] Change

[Correction content]

[0007]

In the memory system according to the first aspect of the present invention, first, the use / non-use area setting unit (cache memory use area setting unit 8) determines the main memory based on the address value for storing the data in the main memory. Is divided into areas that use cache memory and areas that do not use cache memory. Next, the use / non-use determining unit (cache memory use / non-use determining unit 8) sets the use / non-use area setting unit, based on the address value of the data on the main memory used by the CPU, It is determined whether to use the cache memory. Finally, by the connection means (cache memory use / non-use switching mechanism 6), according to the instruction of the use / non-use determination unit,
The main memory or cache memory is connected to the CPU. In the memory system according to the second aspect of the present invention, when the main memory is divided into an area using the cache memory and an area not using the cache memory, the data area using the cache memory is a variable length area of the main memory, and the cache memory is The unused data area is an area other than the variable length area of the main memory. In the third memory system according to the invention, use of the cache memory by the user,
The unused setting is made by the cache memory use area setting unit 8 (see
Perform in 3).

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0008

[Correction method] Change

[Correction content]

[0008]

EXAMPLES Example 1. 1 is a diagram showing the configuration of a computer system according to a first embodiment of the present invention. Incidentally, the same or corresponding parts as those of the conventional example (FIG. 4) are designated by the same reference numerals and the description thereof will be omitted. Reference numeral 5 is a cache memory control unit, 6 is a cache memory use / non-use switching mechanism as a connecting unit, 7 is a cache memory use / non-use determination unit as a use / non-use determination unit, and 8 is a use / non-use area determination unit. cache memory usage area setting unit as, 101 cache memory application area, 102 Ru cache memory unapplied regions der. Using key Yasshumemori 2, the cache memory use and non-use switching mechanism 6 for switching the non-use, CPU 1 is switched whether or not to use the cache memory. The cache memory control unit 5 controls the cache memory use / non-use switching mechanism 6. And the cache memory use / unuse area
Is set by the cache memory use area setting unit. This
The setting of is easily set using software. example
If, set to that cache memory unused by entering the cache memory using the (0) by entering the pre-Me-determined symbol (1). In this way, in order to switch the cache memory use / non-use switching mechanism 6, the use / non-use of the cache memory 2 is determined by the address indicating the location where the data of the main memory 3 is stored. Chi I a to <br/>, divided in advance a plurality of memory areas of the main memory 3 (fixed length block), these each block, for example
For example, the symbol "1" indicating the cache memory usage area, or
Set the symbol "0" indicating the unused area of the cache memory
By doing so, it is selected which of the cache memory application area 101 using the cache memory 2 and the cache memory non-application area 102 not using the cache memory 2 is used. Then, the use or non-use of the cache memory 2 in each of these blocks is registered in the cache memory use area setting unit 8. The cache memory use / non-use determination unit 7 controls the cache memory use / non-use switching mechanism 6 according to the setting contents of the cache memory use area setting unit 8. The setting contents of each block in the main memory 3 in the cache memory use area setting unit 8 can be dynamically set. That is, the use / non-use of the cache memory of data in the memory area can be set by the software even while the computer system is operating. Therefore, for example, the main memory 3
When the contents of the above are rewritten, the cache memory applicable area 101 and the cache memory non-applicable area 102 can be reset.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0009

[Correction method] Change

[Correction content]

FIG. 2 is a flow chart showing the operation of memory access control in the memory system of the first embodiment of the present invention. Next, the operation of the memory system of the first embodiment will be described. When there is a data request from the CPU 1, the cache memory use / nonuse determination unit 7
It is determined whether the data read address of the main memory 3 is the cache memory applicable area 101 (step S21).
If this read address is in the cache memory applicable area 101, the data is in the cache memory 2
If it exists, the CPU 1 reads data from the cache memory 2 (step S23), and if it does not exist, CP
U 1 reads data from the main memory 3 (step S2
4). After that, to make this data hit the cache,
The cache memory 2 is updated (step S25). If the read address is within the cache memory non-applicable area 102, the CPU 1 reads data from the main memory 3 (step S26).

Claims (3)

[Claims] 1. In a memory system comprising a CPU, a main memory and a cache memory, the main memory is divided into an area using the cache memory and an area not using the cache memory based on an address value for storing the data of the main memory. The use / non-use area setting section that makes separate settings and the CPU
Based on the data address value on the main memory used by the main memory or cache according to the instruction of the use / non-use determining unit and whether to use the non-use determining unit. Memory and above C
A memory system comprising: a connection unit for connecting to a PU. 2. The use / non-use so that a data area using a cache memory is a variable length area of the main memory and a data area not using a cache memory is an area other than the variable length area of the main memory. The memory system according to claim 1, wherein the memory system is set by an area setting unit. 3. The setting instruction means for instructing a use / non-use area of a cache memory on the main memory by a user to the use / non-use setting unit, according to claim 1. Memory system.