JPH0629792A - Latch circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] Regarding a latch circuit composed of TTL circuits, D
When the input is "H", "H" of the D input can be surely latched. [Structure] A through output control circuit including a Schottky diode 50 is provided, and clock input = “H”, invert output = “L”, through output = “H” is inverted to clock input = “L”. Invert output =
After the output becomes "H", the through output becomes "L" so that both the invert output and the through output become "L".

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a TTL (transistor t).
ransistor logic) circuit.

[0002]

2. Description of the Related Art Conventionally, as a latch circuit composed of a TTL circuit, one having a circuit diagram shown in FIG. 6 is known.

In the figure, 1 is a terminal for data input (hereinafter referred to as D input), 2 is a latch circuit section, 3 is a terminal for power supply voltage Vcc, 4 is a terminal for Q output (positive phase output), 5 is a terminal for clock input, 6 is an inversion circuit (inversion circuit), 7
Is a through circuit (non-inverting circuit).

Further, in the latch circuit section 2, 8 is pn
p-type transistors, 9 to 14 are npn-type transistors, and have a Schottky barrier between the base and collector.
Diode (hereinafter referred to as Schottky diode)
Is a Schottky diode, and 16 to 22 are resistors.

In the inverter circuit 6, 23 is a pnp type transistor and 24 to 26 are npn type transistors.
A diode inserted, 27 is a pn junction diode, 28 and 29 are Schottky diodes, 30-
32 is a resistance.

In the through circuit 7, 33 is pn
p-type transistors, 34 to 37 are npn-type transistors, which are formed by inserting a Schottky diode between the base and collector, 38 and 40 are pn junction diodes, 39 and 41 are Schottky diodes, 42
˜45 are resistors.

FIG. 7 is a waveform diagram showing the relationship between the clock input in this latch circuit, the invert output which is the output of the invert circuit 6, and the through output which is the output of the through circuit 7. In this latch circuit, FIG. When the clock input is inverted from "H" (high level) to "L" (low level), the rising of the invert output and the falling of the through output start almost at the same time.

In this latch circuit, when the clock input = “H”, the latch circuit is in the through state, and the D input is “H”.
Is input, set the clock input to "H".
To "L", the "H" which is the D input is latched.

The operation of the latch circuit will be described in more detail. As shown in FIG.
In the case of “H”, in the inverter circuit 6, the transistor 2
3 = OFF (non-conductive), transistor 24 = ON (conductive), transistor 25 = OFF, transistor 26 =
When it is ON, the invert output is "L".

In the through circuit 7, the transistor 3
3 = OFF, transistor 34 = ON, transistor 3
5 = OFF, transistor 36 = ON, transistor 3
When 7 = OFF, the through output = “H”.

In this case, when D input = “H”, the transistor 8 = OFF in the latch circuit section 2 and the through output = “H”, so that the current I ₁₆ flowing through the resistor ₁₆ is , Flows into the base of the transistor 9, and the transistor 9 is turned on.

Further, in this case, the invert output = “L”
Therefore, the current I ₁₈ flowing through the resistor 18 does not flow into the base of the transistor 10 and the collector of the transistor 11 but into the inversion circuit 6, and the transistor 10 = OFF and the transistor 11 = OFF.

As a result, the current I ₂₀ flowing through the resistor ₂₀ is
It does not flow into the base of the transistor 12 but into the collector of the transistor 9 and the transistor 12 = OF
F, transistor 13 = ON, transistor 14 = OF
At F, Q output = “H”. This is D input = "H"
It is a through state in the case of.

From this state, as shown in FIG. 9, when the clock input is inverted to "L", the inverter circuit 6
Transistor 23 = ON, Transistor 24 = OFF,
Transistor 25 = ON, Transistor 26 = OFF
Then, the invert output becomes “H”.

In the through circuit 7, the transistor 3
3 = ON, transistor 34 = OFF, transistor 3
5 = ON, transistor 36 = OFF, transistor 3
When 7 = ON, the through output = “L”.

As a result, in the latch circuit section 2, the current I ₁₆ flowing through the resistor 16 does not flow into the base of the transistor 9 but into the through circuit 7, and the transistor 9 = OF.
The current I ₁₈ flowing in the resistor 18 becomes F and flows into the base of the transistor 10, so that the transistor 10 = O.
N. In this case, the transistor 11 is off
Is to be maintained.

As a result, the current I ₂₀ flowing through the resistor ₂₀ is
It flows into the collector of the transistor 10, the transistor 12 = OFF, the transistor 13 = ON, the transistor 14 = OFF, and the Q output = “H” is maintained. This state does not change even when D input = “L”, and is a state in which “H” is latched.

As shown in FIG. 10, when clock input = “H”, that is, invert output = “L”, through output = “H”, and D input = “L”, transistor 8 = ON, transistor 9 = OFF, transistor 10
= OFF. In this case, transistor 11 = half ON
It is designed to be in a state.

As a result, the current I ₂₀ flowing through the resistor ₂₀ is
It flows into the base of transistor 12 and transistor 1
2 = ON, transistor 13 = OFF, transistor 1
When 4 = ON, Q output = “L”.

From this state, as shown in FIG. 11, the clock input is inverted to "L", and the invert output =
Even when “H” and through output = “L”,
Since transistor 8 = ON, transistor 9 = O
The FF state does not change.

In this case, the current I flowing through the resistor 18
₁₈ flows into the collector of the transistor 11 which is in a half ON state, does not flow into the collector of the transistor 10, and the state of the transistor 10 = OFF does not change.

As a result, the current I ₂₀ flowing through the resistor ₂₀ is
It flows into the base of transistor 12 and transistor 1
2 = ON, transistor 13 = OFF, transistor 1
When 4 = ON, the state of Q output = "L" is maintained.

Thus, when D input = “L”,
Q output = “L” regardless of the level of the clock input. In order to set this state, the transistor 1
1 is inserted.

[0024]

In such a conventional latch circuit, when the clock input is inverted from "H" to "L", the rising of the invert output and the falling of the through output start almost at the same time. , There is a high possibility that both the invert output and the through output become “L”.

Therefore, as shown in FIG. 12, D input =
In the case of "H", if the clock input is inverted from "H" to "L", both the invert output and the through output are "L", and the transistor 10 is turned from ON to ON.
Before it is turned off, the transistor 9 turns from ON to OFF, and both of these transistors 9 and 10 are OF
It may be F.

In this case, the current I ₂₀ flowing through the resistor ₂₀ is
It flows into the base of transistor 12 and transistor 1
2 = ON, transistor 13 = OFF, transistor 1
When 4 = ON, Q output = “L”.

As described above, in this conventional latch circuit, when the D input = “H”, the D input “H” is latched when the clock input is inverted from “H” to “L”. However, there is a problem that "L" may be erroneously output.

In view of the above points, the present invention is supplied with an invert circuit for inverting a clock input, a through circuit for non-inverting a clock input, an output of the invert circuit and an output of the through circuit as control signals, and a data input. "H"
In this case, when the clock input is "H", "H" is output as the through state, and when the clock input is inverted to "L" from this through state, the "H" of the data input is latched. However, the output of the invert circuit and the output of the through circuit are both “L” from the through state.
In the latch circuit including the TTL circuit provided with a latch circuit section having a characteristic that "H" of the data input cannot be latched and "L" is erroneously output, An object of the present invention is to provide a latch circuit capable of surely latching "H" and ensuring a normal operation.

[0029]

FIG. 1 is a block diagram showing the principle of the present invention. In the figure, reference numeral 46 denotes an inverting circuit composed of a TTL circuit, which outputs an inverted output formed by inverting a clock input, and 47 is a through circuit composed of a TTL circuit, which forms a through output formed by non-inverting the clock input. It is what is output.

Reference numeral 48 is a latch circuit section composed of a TTL circuit, which is supplied with the output of the invert circuit 46 and the output of the through circuit 47 as control signals, and when the data input is "H", the clock input is "H". In the case of “”, “H” is output as a through state, and when the clock input is inverted to “L” from this through state, “H” of the data input is latched. When both the output of the circuit 46 and the output of the through circuit 47 become "L", "H" of the data input cannot be latched and "L" is erroneously output.

Reference numeral 49 is a through output control circuit for controlling the through circuit 47. When the clock input is inverted from "H" to "L", the output of the invert circuit 46 goes through a predetermined level or more and then the through output is performed. The output of the circuit 47 starts to fall, and the output of the invert circuit 46 and the output of the through circuit 47 are prevented from becoming "L" at the same time.

[0032]

In the present invention, the through output control circuit 49 for controlling the through circuit 47 is provided, and the clock input is "H".
, The output of the through circuit 47 starts to fall after the output of the invert circuit 46 becomes equal to or higher than a predetermined level, and the output of the invert circuit 46 and the output of the through circuit 47 are simultaneously set to “L”. I try not to be.

As a result, when the D input is "H" and the clock input is inverted from "H" to "L",
Avoiding a situation in which the output of the invert circuit 46 and the output of the through circuit 47 both become "L" and thus "L" is erroneously output, and "H" of the D input is reliably latched to ensure normal operation. Can be secured.

[0034]

EXAMPLES Referring to FIGS. 2 to 5, 8 and 9,
The first and second embodiments of the present invention will be described.
2, 4, and 5, parts corresponding to those in FIG. 6 are designated by the same reference numerals, and duplicate description thereof will be omitted.

First Embodiment FIG. 2 is a circuit diagram showing a first embodiment of the present invention. In the latch circuit of the first embodiment, a through output control circuit using a Schottky diode 50 is used. The other parts are provided in the same manner as the conventional latch circuit shown in FIG.

Here, the Schottky diode 50
Has its cathode connected to the output terminal 51 of the inverter circuit 6, and its anode connected to the base of the phase dividing transistor 35 of the through circuit 7.

FIG. 3 is a waveform diagram showing the relationship among the clock input, the invert output, and the through output in the first embodiment. In the first embodiment, the clock input changes from "H" to "L". , The presence of the Schottky diode 50 will cause the slew output to begin to fall after the clock input reaches a predetermined level, as described below.

In the first embodiment, when the clock input = “H”, the through state is set, and the D input is “H”.
Is input, set the clock input to "H".
Is inverted to "L" to latch "H" which is a D input, as in the conventional latch circuit shown in FIG.
When “H” and clock input = “H”, the ON and OFF states of each transistor are the same as those shown in FIG.

From this state, as shown in FIG. 4, when the clock input is inverted to "L", the inverter circuit 6
Transistor 23 = ON, Transistor 24 = OFF,
Transistor 25 = ON, Transistor 26 = OFF
Then, the invert output rises toward "H".

On the other hand, in the through circuit 7, the transistor 33 = ON and the transistor 34 = OFF,
In order to turn on the transistor 35, the base voltage is 1.6 [V] (the base-emitter voltage of the transistor 37 is 0.8 [V] + the base-emitter voltage of the transistor 35 is 0.8 [V]. ) You need to be above.

In this first embodiment, since the Schottky diode 50 is provided, in order to turn on the transistor 35, the invert output is 1.1 [V] (the base of the transistor 37). -Emitter voltage 0.8 [V] + transistor 35 base-emitter voltage 0.8 [V] -Schottky diode 50
Forward voltage of 0.5 [V]) or higher, and if this invert output is lower than 1.1 [V], the base voltage of the transistor 35 becomes lower than 1.6 [V], The transistor 35 does not become ON.

As a result, when the clock input is inverted from "H" to "L", even if the invert output starts rising, the through output does not start falling at the same time and the invert output is 1. Until it becomes 1 [V], in the through circuit 7, the transistor 33 = ON,
Transistor 34 = OFF, Transistor 35 = OF
F, transistor 36 = ON, transistor 37 = OF
F, through output = “H” will be maintained.

After that, the invert output is 1.1.
When the voltage becomes higher than [V], the base voltage of the transistor 35 becomes 1.6 [V] or higher.
When turned on, the ON / OFF relationship of each transistor is the same as that shown in FIG.

As described above, according to the first embodiment, when the clock input = “H”, the invert output = “L”, the through output = “H”, the clock input = “L” is inverted. In the case of D input = “H”, the clock input changes from “H” to “L” because the through output = “L” when the input output is closer to “H”. When inverted to, avoiding a situation in which both the invert output and the through output become “L” and thus erroneously output “L” as the Q output, and reliably latch the “H” of the D input, Normal operation can be ensured.

Second Embodiment FIG. 5 is a circuit diagram showing a second embodiment of the present invention. In the latch circuit of the second embodiment, an npn formed by inserting a Schottky diode between the base and collector. 6 is provided with a through output control circuit using a transistor 52 and a resistor 53 of the type shown in FIG.
It is configured similarly to the conventional latch circuit shown in FIG.

Here, the transistor 52 has its emitter connected to the output end 51 of the inversion circuit 6 and its collector connected to the phase dividing transistor 35 of the through circuit 7.
Is connected to a terminal 54 to which the power supply voltage Vcc is supplied via a resistor 53.

In the second embodiment, the collector-emitter voltage of the transistor 52 is, for example, 0.3.
[V], when the clock input is inverted from “H” to “L”, the invert output is 1.3 [V] (base-emitter voltage of transistor 37 is 0.8 [V] + transistor 35 Base-emitter voltage 0.8 [V]-
Transistor 52 collector-emitter voltage 0.3
Above [V], except that the transistor 35 is turned on, the operation is the same as in the first embodiment.

[0048]

As described above, according to the present invention, the through output control circuit for controlling the through circuit is provided, and when the clock input is inverted from "H" to "L", the output of the invert circuit is predetermined. Since the output of the through circuit starts to fall after the level becomes higher than the level and the output of the invert circuit and the output of the through circuit do not become “L” at the same time, when the D input is “H”, the clock input When “H” is inverted from “H” to “L”, the output of the invert circuit and the output of the through circuit both become “L”, thereby avoiding the situation of erroneously outputting “L”. It is possible to reliably latch "H" and ensure normal operation.

[Brief description of drawings]

FIG. 1 is a block diagram showing the principle of the present invention.

FIG. 2 is a circuit diagram showing a first embodiment of the present invention.

FIG. 3 shows a clock input according to the first embodiment of the present invention,
It is a wave form diagram which shows the relationship between an invert output and a through output.

FIG. 4 is a circuit diagram for explaining the operation of the first exemplary embodiment of the present invention.

FIG. 5 is a circuit diagram showing a second embodiment of the present invention.

FIG. 6 is a circuit diagram showing an example of a conventional latch circuit.

FIG. 7 is a waveform diagram showing a relationship between a clock input, an invert output, and a through output in the conventional latch circuit.

FIG. 8 is a circuit diagram for explaining the operation of a conventional latch circuit.

FIG. 9 is a circuit diagram for explaining the operation of a conventional latch circuit.

FIG. 10 is a circuit diagram for explaining the operation of a conventional latch circuit.

FIG. 11 is a circuit diagram for explaining the operation of a conventional latch circuit.

FIG. 12 is a circuit diagram for explaining a problem of a conventional latch circuit.

[Explanation of symbols]

 46 Invert Circuit 47 Through Circuit 48 Latch Circuit Section 49 Through Output Control Circuit

Claims (3)

[Claims] 1. An invert circuit (46) for inverting a clock input, a through circuit (47) for non-inverting the clock input, an output of the invert circuit (46) and an output of the through circuit (47) are controlled. When supplied as a signal and the data input is "H", when the clock input is "H", "H" is output as a through state, and the clock input is inverted to "L" from the through state. In this case, "H" of the data input is latched, but if both the output of the inversion circuit (46) and the output of the through circuit (47) become "L" from the through state. , "H" of the data input
In a latch circuit composed of a TTL circuit provided with a latch circuit section (48) having a characteristic that it cannot latch "L" and outputs "L" by mistake, the clock input is inverted from "H" to "L". If
After the output of the invert circuit (46) becomes equal to or higher than a predetermined level, the output of the through circuit (47) starts to fall, and the output of the invert circuit (46) and the output of the through circuit (47) simultaneously. A latch circuit comprising a through output control circuit (49) for controlling the through circuit (47) so that the latch circuit does not become "L". 2. The through output control circuit (49) has a cathode connected to an output end of the inversion circuit (46) and an anode connected to a base of a phase dividing transistor of the through circuit (47). 2. The latch circuit according to claim 1, wherein the latch circuit comprises a diode. 3. The through output control circuit (49) has an emitter connected to an output terminal of the inversion circuit (46) and a collector connected to a base of a phase dividing transistor of the through circuit (47). 2. The latch circuit according to claim 1, wherein the latch circuit comprises a transistor to which a required voltage is applied to the gate.