JPH0630083B2 - Data transfer device - Google Patents

Description

TECHNICAL FIELD The present invention relates to a data transfer device.

[Conventional technology]

In a conventional computer system with a bus configuration, the central processing unit can access data other than memory existing on the bus by the central processing unit issuing an I / O command to a device outside the bus to transfer data. I / O method for performing the above-mentioned processing, the central processing unit is provided with a main memory management unit for converting between a virtual address handled by a program and an actual address on the main memory, and when the central processing unit accesses the main memory. Causes the main memory management unit to determine whether or not the data corresponding to the virtual address exists in the main memory.
There is a paging method in which an area (called a page) including a virtual address is read from the next storage device and then main memory access is performed again.

[Problems to be solved by the invention]

However, the I / O method has a drawback in that a program must distinguish between accessing data that does not exist in the main memory connected to the bus and accessing the main memory.

Although the drawbacks of the paging method are eliminated, i) all main memory accesses of the central processing unit are delayed because it is necessary to perform address translation by the main memory management unit.

ii) When a page fault occurs when the central processing unit performs a write operation to the main memory, the page including the virtual address is read from the secondary storage device and then the write operation is performed, so that between the secondary storage and the main memory. The write operation is not completed until the data transfer is completed, resulting in a large overhead.

iii) In a multiprocessor system in which a plurality of central processing units are present on a single bus, each central processing unit is equipped with a main memory management unit, and address conversion is performed consistently between those main memory management units. Must be executed, the hardware amount of the main memory management unit increases and the overhead at the time of execution also increases.

iv) In a multiprocessor system in which a plurality of central processing units are present on a single bus, a DM is used between a main memory and a secondary memory through this bus during a page fault.
Since A transfer is performed, the processing efficiency is significantly reduced due to access competition on the bus. There were drawbacks such as.

The object of the present invention is to eliminate such conventional drawbacks,
It is not necessary for the program to distinguish between accessing data that does not exist in the main memory connected to the bus and accessing the main memory, and in the case of a write operation, the data transfer must be completed immediately. To provide a simple data transfer device.

[Means for solving problems]

The present invention is connected to a main memory and a central processing unit via a single bus for data transfer consisting of an address bus, a data bus and a bus control line, and stores data at addresses other than the area allocated to the main memory. A data transfer device connected to a device outside the bus to be held via a dedicated bus, wherein the value of the address bus is monitored every time the central processing unit makes a data access via the single bus, An external access detection unit that detects that the processing device has performed read / write and read modify write operations on data at an address other than the area allocated to the main memory on the single bus; and the external access detection unit. , It is detected that the central processing unit has performed a write operation on data at an address other than the area allocated to the main memory on the single bus. In this case, a write response signal is generated to the central processing unit, and the external access detection unit causes the central processing unit to address data other than the area allocated to the main memory on the single bus. When it is detected that the read and read modify write operations have been performed, a bus control signal generator that generates a Bayesler signal to the central processing unit, and the central processing unit stores the main memory on the single bus. When the write operation is performed on the data of the address other than the allocated area, the data and the address which the central processing unit is going to write are transferred to the device outside the bus, and the central processing device transfers the main data on the single bus. When a read operation or read modify write operation is performed on data at an address other than the area allocated for storage The address of the data that the central processing unit is going to read and, in the case of a read-modify-write operation, an external-bus data access request unit that transfers the data necessary for the read-modify-write operation to the external-bus device; An out-of-bus data access response unit that receives data and writes the received data in the main memory on the single bus; and a central processing unit communication unit that notifies a central processing unit of the receipt of data from the external device. It is characterized in that the data transfer between the central processing unit and the device outside the bus is realized by the same procedure as the read / write to the main memory on the single bus and the read modify write operation.

[Action]

In the present invention, the external access detection unit monitors the data access by the central processing unit on the data transfer bus.
The read / write of data other than the address of the main memory on the bus by the central processing unit (hereinafter referred to as data outside the bus) and the read of the data before another device accesses the data, Detects that a read-modify-write operation that performs a write operation on data is performed.

When the access to the data outside the bus by the central processing unit is a write operation, the outside-bus data access request section substitutes the write operation by transferring the data and the address which the central processing unit is going to write to the device outside the bus.

When the access to the data outside the bus by the central processing unit is a read operation and a read modify write operation, a bus error signal is generated to the central processing unit that has performed the read and read modify write operations. Further, the outside-bus data access request unit requests the outside-bus device to read the data, writes the data to the main memory on the bus at the time of receiving the data, and notifies the central processing unit of the receipt of the data. It performs read-out and read-modify-write operations on behalf of external data.

〔Example〕

 Next, an embodiment of the present invention will be described with reference to FIG.

FIG. 1 is a block diagram for explaining an embodiment of the present invention.

The data transfer device 1 of FIG. 1 includes an external access detection unit 2 and
Bus control signal generation unit 3 and external bus data access request unit 4
, A data access response section 5 outside the bus, and a central processing unit communication section 6, and a central processing unit 11 and a main memory 12 via an address 8 of a single bus 7, a data bus 9 and a bus control line 10. Is connected to the external device 13 via the dedicated bus 14.

In FIG. 1, every time the central processing unit 11 makes a data access through the single bus 7, the external access detection unit 2 of the data transfer device 1 monitors the value of the address bus 8 to access the data of the central processing unit 11. Is an access to data in an area allocated to the main memory 12 (hereinafter referred to as an internal access), or an access to data held by an external device outside the area allocated to the main memory 12 (hereinafter referred to as an external access). Call).

If the access attempted by the central processing unit 11 is an internal access, the data transfer device 1 does not perform the processing, and the main memory 12
Responds to the access, the data access is completed.

When the external access detection unit 2 determines that the access currently being performed by the central processing unit 11 is an external access, the data transfer device 1 performs the following processing according to the type of data access that the central processing unit attempts to perform. Operate.

i) When the external access is a write operation 1) The outside-bus data access request unit 4 transfers the write data and the write address to the outside-bus device 13 via the dedicated bus 14, and requests the outside-bus device 13 for the writing operation.

2) At the same time, the bus control signal generator 3 notifies the central processing unit 11 of confirmation of writing via the bus control line 10, that is, generates a write confirmation signal.

At this point, the central processing unit 11 considers that the external access operation is completed and moves to the next processing.

ii) When the external access is a read operation and a read-modify-write operation 1) The external-bus data access request unit 4 reads the read address to the external device 13 via the dedicated bus 14 and the read-modify-write operation in the case of the read-modify-write operation Necessary data is transferred, and the out-bus device 13 is requested to perform a read operation and a read modify write operation on behalf.

2) At the same time, the bus control signal generation unit 3 notifies the central processing unit 11 of a bus error via the bus control line 10, that is, generates a bus error signal and abandons the exclusive right of the bus.

When the external access is a read operation and a read modify write operation, unlike the write operation, it is impossible to proceed with the process until the external device 13 responds to the access. Therefore, in the present invention, once the Bayesler is generated and the bus access to the central processing unit 11 is temporarily interrupted, this allows the central processing unit 11 to execute other work especially in a multi-process environment. It will be possible. Releasing the exclusive right of the bus by the central processing unit 11 allows other devices to use the bus. You can get advantages such as.

3) When the external bus device 13 completes the read or read modify write operation, the external bus data access response unit 5 writes the data to a specific address in the main memory 12 when it receives the data from the external bus device 13.

4) The central processing unit communication unit 6 notifies the central processing unit 11 of the reception of data, and the notified central processing unit 11 stores the main memory.
The external access operation is completed by reading 12 data.

〔The invention's effect〕

As described above in detail, according to the present invention, i) the external access detection unit monitors the access of data by the central processing unit on the data transfer bus and detects the access to the data outside the bus, so that It is not necessary for the program to distinguish between the access to the in-bus data and the off-bus data.

ii) Unlike the paging method, accessing the data in the bus does not involve any overhead.

iii) Unlike the paging method, in the case of a write operation for data outside the bus, a write confirmation signal is issued to the central processing unit when the write data transfer unit captures the data to be written and the address, so the central processing unit at that time. Can move to the next operation.

iv) The amount of hardware is small compared to the paging method using the main memory management unit.

v) Even if there are multiple central processing units on the bus, it is possible to support without adding any hardware.

The effects such as

[Brief description of drawings]

FIG. 1 is a block diagram for explaining an embodiment of the present invention. 1 …… Data transfer device 2 …… External access detection unit 3 …… Bus control signal generation unit 4 …… Outside bus data access request unit 5 …… Outside bus data access response unit 6 …… Central processing unit communication unit 7 …… Single bus 8 …… Address bus 9 …… Data bus 10 …… Bus control line 11 …… Central processing unit 12 …… Main memory 13 …… External bus device 14 …… Dedicated bus

Claims (1)

[Claims] 1. Data of an address other than an area allocated to the main memory and connected to a main memory and a central processing unit through a single bus for data transfer consisting of an address bus, a data bus and a bus control line. A data transfer device connected via a dedicated bus to a device outside the bus that holds the value of the address bus value every time the central processing unit makes a data access via the single bus. An external access detection unit that detects that the central processing unit has performed read / write and read modify write operations on data at addresses other than the area allocated to the main memory on the single bus; and the external access detection unit. However, the central processing unit may have performed a write operation on data at an address other than the area allocated to the main memory on the single bus. If it is issued, a write response signal is generated to the central processing unit, and the external access detection unit causes the central processing unit to output data of an address other than the area allocated to the main memory on the single bus. A bus control signal generation unit for generating a Baesler signal to the central processing unit when it is detected that a read and a read modify write operation have been performed on the main memory on the single bus. When a write operation is performed on data at an address other than the area allocated to, the central processor transfers the data to be written and the address to the external device, and the central processor transfers the data on the single bus. When a read operation or read modify write operation is performed on data at an address other than the area allocated to main memory An address of the data to be read by the central processing unit and, in the case of a read-modify-write operation, an external-bus data access request unit that transfers data necessary for the read-modify-write operation to the external-bus device, and the external-bus device An external bus data access response unit that receives data from the external storage device and writes the received data to the main memory on the single bus; and a central processing unit communication unit that notifies the central processing unit of the reception of the data from the external device. And data for realizing data transfer between the central processing unit and the device outside the bus by the same procedure as the read / write to the main memory on the single bus and the read modify write operation. Transfer device.